Abstract: A rate multiplier for rate multiplying a pulse train comprising: an accumulator, a multiplexer for selecting one of a first and a second number of different signs to feed to the accumulator, and a pulse train gate for providing or blocking the pulse train, wherein the multiplexer and the pulse train gate are controlled by the MSB output signal of the accumulator.

Abstract: Circuitry which performs modular mathematics to solve the equation C=M.sup.k mod n and n is performed in a manner to mask the exponent k's signature from timing or power monitoring attacks. The modular exponentation function is performed in a normalized manner such that binary ones and zeros in the exponent are calculated by being modulo-squared and modulo-multiplied.

Abstract: A pulse signal generation circuit comprises a frequency setting register which is at least (n+1) bits long for setting a value of 2.sup.n or smaller as a frequency value of a pulse signal to be generated, and a cumulative addition circuit having an adder and a flip-flop which is at least (n+1) bits long. The cumulative addition circuit repeats at a rate of 2.sup.n+1 times per second, operations of making the adder add a value set in the frequency setting register to a value held in the flip-flop and then making the flip-flop hold the addition result, and outputs a signal having a value of (n+1)th bit in the flip-flop as the pulse signal.

Abstract: A multi-divide frequency divider, includes a chain of serially-connected frequency divider units, each responding to a first state of received control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a first divisor, and each responding to a second state of the control signals by using the reference clock signal to generate an output signal having a frequency that is the reference clock frequency divided by a second divisor. The output signal may be supplied to a successor frequency divider unit in the chain. Division by the first and second divisors causes the frequency divider to respectively transition through first and second predetermined state sequences.