Abstract: Computer systems and computer-implemented methods train a neural network, by: (a) computing for each datum in a set of training data, activation values for nodes in the neural network and estimates of partial derivatives of an objective function for the neural network for the nodes in the neural network; (b) selecting a target node of the neural network and/or a target datum in the set of training data; (c) selecting a target-specific improvement model for the neural network, wherein the target-specific improvement model, when added to the neural network, improves performance of the neural network for the target node and/or the target datum, as the case may be; (d) training the target-specific improvement model; (e) merging the target-specific improvement model with the neural network to form an expanded neural network; and (f) training the expanded neural network.

Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

Abstract: An optimization system has a plurality of nodes, each including: a calculation processing unit that calculates an optimum value of a determination variable representing a parameter that controls the nodes by using the ADMM; and a function value calculation unit that receives an input of a value of the determination variable and calculates the value of the objective function based on a calculation model constructed by a learning processing. An arbitrary value of the determination variable is input to the function value calculation unit, and the calculation processing unit substitutes the value of the objective function calculated by the function value calculation unit and the arbitrary value of the determination variable into a second optimization problem by dual transformation of the first optimization problem, thereby repeatedly executing a processing of calculating a value of the dual variable until the value of the dual variable satisfies a predetermined condition.

Abstract: The present disclosure relates generally to techniques for adjusting the number representation (e.g., format) of a variable before and/or after performing one or more arithmetic operations on the variable. In particular, the present disclosure relates to scaling the range of a variable to a suitable representation based on available hardware (e.g., hard logic) in an integrated circuit device. For example, an input in a first number format (e.g., bfloat16) may be scaled to a second number format (e.g., half-precision floating-point) so that circuitry implemented to receive inputs in the second number format may perform one or more arithmetic operations on the input. Further, the output produced by the circuitry may be scaled back to the first number format. Accordingly, arithmetic operations, such as a dot-product, performed in a first format may be emulated by scaling the inputs to and/or the outputs from arithmetic operations performed in another format.

Abstract: An apparatus and method of low complexity optimization solver for path smoothing with constraint variation are herein disclosed. According to one embodiment, an apparatus includes an L1 central processing unit (CPU) configured to transform an L1 trend filtering problem to a primal-dual linear programming (LP) optimization problem pair; and an L1 arithmetic logic unit (ALU) connected to the L1 CPU and configured to solve a primal problem of the primal-dual LP optimization problem pair.

Abstract: An apparatus and method of low complexity optimization solver for path smoothing with constraint variation are herein disclosed. According to one embodiment, an apparatus includes an L1 central processing unit (CPU) configured to transform an L1 trend filtering problem to a primal-dual linear programming (LP) optimization problem pair; and an L1 arithmetic logic unit (ALU) connected to the L1 CPU and configured to solve a primal problem of the primal-dual LP optimization problem pair with an extended full tableau simplex method.

Abstract: Methods and systems for performing hardware computations of mathematical functions are provided. In one example, a system comprises a mapping table that maps each base value of a plurality of base values to parameters related to a mathematical function; a selection module configured to select, based on an input value, a first base value and first parameters mapped to the first base value in the mapping table; and arithmetic circuits configured to: receive, from the mapping table, the first base value and the first plurality of parameters; and compute, based on a relationship between the input value and the first base value, and based on the first parameters, an estimated output value of the mathematical function for the input value.

Abstract: Embodiments of the present disclosure pertain to digital circuits with compressed carries. In one embodiment, an adder circuit generates a sum and carry. The carry is compressed to reduce the number of bits required to represent the carry. In one embodiment, a multiplier circuit generates output product values. The output product values may be summed to produce a sum and carry. The carry may be compressed. In other embodiments, a multiplier circuit receives an input sum and compressed carry. The compressed input carry is decompressed and added to output product values and the input sum, and a resulting carry is compressed. The output of such a multiplier is another sum and compressed carry.

Abstract: An operation management apparatus that is capable of detecting an anomaly is provided.

Abstract: An apparatus and method of low complexity optimization solver for path smoothing with constraint variation are herein disclosed. According to one embodiment, an apparatus includes an L1 controller configured to receive a raw data series z to be smoothed, where L1 represents a formulation based on L1 norm cost, receives weights w0, w1, w2, and w3 to control smoothness of an output path, and formulate an L1 trend filtering problem; an L1 central processing unit (CPU) connected to the L1 controller and configured to transform the L1 trend filtering problem to a primal-dual linear programming (LP) optimization problem pair; and an L1 arithmetic logic unit (ALU) connected to the L1 CPU and configured to solve a primal problem of the primal-dual problem pair with an extended full tableau simplex method.

Abstract: Aspects for submatrix operations in neural network are described herein. The aspects may include a controller unit configured to receive a submatrix instruction. The submatrix instruction may include a starting address of a submatrix of a matrix, a width of the submatrix, a height of the submatrix, and a stride that indicates a position of the submatrix relative to the matrix. The aspects may further include a computation module configured to select one or more values from the matrix as elements of the submatrix in accordance with the starting address of the matrix, the starting address of the submatrix, the width of the submatrix, the height of the submatrix, and the stride.

Abstract: A method of operating a data processing system when determining an unsigned normalized integer representation U of a number x is disclosed. When the number x has a value between 0 and 1, it is determined 31 whether the number x is greater than or equal to 0.5. When it is determined that the number x is greater than or equal to 0.5, the bit of the binary representation of the number x that represents the value 0.5 is inverted 32, and the unsigned normalized integer representation U of the number x is determined using the value of the binary representation of the number x having its bit that represents the value 0.5 inverted.

Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

Abstract: An imaging apparatus according to an aspect of the present disclosure includes an image sensor which, in operation, acquires m kinds (m is an integer which is 1 or larger) of light, the m kinds of light each having wavelength characteristic different from each other and outputs one or more signals each corresponding to each of the m kinds of light, and a signal processing circuit which, in operation, processes the one or more signals to generate and output n, which is larger than m, pieces of images corresponding to respective wavelength regions different from each other.

Abstract: A method of estimating interference in a received signal is disclosed. The method includes receiving a plurality of subcarriers from a remote transmitter. Each of the subcarriers is multiplied by a control signal. At least two of the subcarriers are compared to produce a differential signal. Interference is estimated in response to the differential signal.

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.

Abstract: The present invention relates to a signal processing device and method. The device receives, from a sensor which measures a physical quantity applied thereto and outputs an accumulated or integrated value of the physical quantity as an M-bit digital value, the digital value, and, when a difference between the physical quantities at two successive data acquisition times lies within a predetermined range and an absolute value of a digital counter increment is greater than 2M-1, calculate the digital counter increment as the physical quantity measured by the sensor.

Abstract: Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be grouped, or assigned into levels. The levels may be scaled and applied at unique intervals of calculational steps. A quantum device may have circuitry for applying levels of the operator at the unique intervals.

Abstract: Systems and methods are described for encoding quantized vector parameters in a bitstream are described. An exemplary method may include receiving a vector of integers used in a data compression codebook, the sum of the integers equaling a pulse sum. An initial expected magnitude may be determined for a first integer, the initial expected magnitude being based on the pulse sum, a distribution parameter, and a value corresponding to a number of integers in the vector. The actual magnitude of the first integer may be encoded based on the initial expected magnitude of the first integer. The pulse sum may be adjusted using the encoded actual magnitude. Also, the value corresponding to the number of integers in the vector may be reduced by one. Expected magnitudes for each of the remaining integers of the vector may then be calculated recursively.

Abstract: Sensor data is received from one or more sensors. The sensor data is organized within a hierarchy. The sensor data is organized within a hierarchy that is non-dyadic. A processor of a computing device generates a discrete wavelet transform, based on the sensor data and based on the hierarchy of the sensor data, to compress the sensor data. The sensor data, as has been compressed via generation of the discrete wavelet transform, is processed.

Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a (64) channel filter bank using a prototype filter length of (640) coefficients and a system delay of (319) samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip.

Abstract: A mechanism for reconstructing a signal (e.g., an image) based on a vector s, which includes measurements of the signal. The measurements have been acquired using at least a portion of a measurement vector set represented by a matrix H. Each of the measurements corresponds to a respective row of the matrix H. (For example, each of the measurements may correspond to an inner product between the signal and a respective row of the matrix product HD, wherein D is a generalized permutation matrix.) A total-variation primal-dual hybrid gradient (TV-PDHG) algorithm is executed based on data including the matrix H and the vector s, to determine an estimate for the signal. The TV-PDHG algorithm is implemented in fixed-point arithmetic.

Abstract: A normalized n-bit value is converted into a normalized m-bit value in accordance with a predetermined rounding mode. An initial m-bit value is determined, where the bits of the initial m-bit value are equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the normalized n-bit value. An output state is selected based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode. The output state indicates how the normalized m-bit value is to be determined from the initial m-bit value. In accordance with the selected output state, the normalized m-bit value is determined to be equal to one of a plurality of candidate m-bit values, wherein the plurality of candidate m-bit values consists of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one.

Abstract: A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty values, and wherein the analytic defines a continuous, monotonic mathematical function. The method includes executing the analytic using the one or more analytic inputs to determine one or more analytic outputs. The method also includes executing an uncertainty calculation to estimate one or more uncertainty outputs corresponding to the one or more analytic outputs, based, at least in part, on the one or more analytic inputs and the corresponding one or more uncertainty values. The method further includes providing the one or more analytic outputs as well as the corresponding one or more uncertainty outputs.

Abstract: A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue vector. The covariance matrix is calculated for a matrix of data including a plurality of data values for each of a plurality of parameters. The decomposed matrix includes a number of eigenvectors equal to a number of the plurality of parameters with each eigenvector including a coefficient for each parameter. The eigenvalue vector includes an eigenvalue defined for each eigenvector. A first matrix is created by rank ordering the coefficient within each parameter of the plurality of parameters for each of the plurality of parameters. A score is determined for each parameter using the created first matrix and the eigenvalue vector. A parameter set is identified based on the determined score for each parameter.

Abstract: A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of numbers in a page comparison mode to output a candidate set of winning numbers, and for automatically switching to a leaf/tree search of the candidate set of winning numbers in an element comparison mode. Operating in parallel with the multi-element comparator (232), an index generation unit (233) processes flag/sign bits from the multi-element comparator in conjunction with state machine control logic (230) to keep track of the index/indices for the peak value. Upon completion of final stage, the index generation unit returns the absolute index (235) of the peak value.

Abstract: Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a minimum operand that is a smaller one of the first component or the second component. Also included are N rotator stages, each corresponding to a unique one of N predetermined vectors, each of the N rotator stages having a first multiply circuit to multiply the maximum operand by a cosine coefficient of a predetermined vector to output a first rotation component, a second multiply circuit for multiplying the minimum operand by a sine coefficient of the predetermined vector to output a second rotation component, and an adder circuit for adding the first rotation component to the second rotation component to output one of N results, and a maximum value circuit for outputting a maximum one of the N results.

Abstract: In an embodiment a method of vectorizing a collapsed multi-nested loop includes executing, in a vector unit of a processor, the collapsed loop to obtain a vector of offsets, including for each of a plurality of iterations, calculating a scalar offset into a multi-dimensional data structure, storing the scalar offset in a data element of a first vector register, and updating a loop counter value of a multi-dimensional loop counter vector. In turn, a plurality of data elements are loaded from the multi-dimensional data structure using a base value and indexes from the vector of offsets, at least one computation is performed on the loaded plurality of data elements to obtain a plurality of results, and the plurality of results are stored into the multi-dimensional data structure using the base value and the indexes from the vector of offsets. Other embodiments are described and claimed.

Abstract: Some embodiments address a problem of detecting the absolute amount of displacement of a moving body. In various embodiments, the multi-turn absolute angle of rotation of a main shaft is calculated from a rotation angle detected by an angle sensor joined to the main shaft and a countershaft. The rotation of a main shaft (12) joined to a rotary drive source (11) is transmitted to countershafts (13, 14) at a predetermined gear ratio. The rotation angles (Ss, Sp, Sq) of the main shaft (12) and the countershafts (13, 14) are detected by angle sensors (15a, 15b, 15c), each of the rotation angles is sent to a synchronizing/integer-obtaining processor (17) by an AD-conversion-angle calculator (16) as angle detection values (?s, ?p, ?q), and period signals (p, q) obtained as integers are calculated. The period signals (p, q) are sent to a period computer (18), and the period signal (r) of the main shaft is calculated.

Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Abstract: A system including a processor for adjusting the dynamic range of an image including a plurality of pixels. The processor segments the pixels into blocks, and computes statistical values for each block based on intensity values of the pixels. The processor also adjusts the dynamic range of the image by controlling the intensity values of the pixels based on the statistical values.

Abstract: Processing a neural signal sequence occurs in accordance with a neural signal spiking model that includes an exponential component (EC) and a polynomial component (PC). The exponential component is correlated with the presence of signal sequence noise, and the polynomial component is correlated with the presence of detectable signal sequence spikes distinguishable from the noise. A neural interface includes a frequency shaping amplifier (FSA) configured for receiving input signals; an amplifier gain stage and an analog-to-digital conversion (ADC) stage; a Hilbert transformer configured for performing a Hilbert transform upon neural signal data received from the ADC stage; a linear regression engine configured for estimating EC parameters and PC parameters corresponding to Hilbert transformed neural signal data; and a neural spike probability estimator configured for generating a neural spike probability map based upon the EC parameters and the PC parameters.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2^X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 and determines a power value (log2(1+X1/223)) through an interpolation process. A logarithmic calculator determines a logarithmic value Z=log2 XY=Y(X2+log2(1+X1/223)) from the exponent X2 and the power value from the interpolation processor. The integer/fraction splitter splits the logarithmic value Z into an integer Zint and a fraction Zamari. The interpolation processor references a power of fraction table storage unit in response to the fraction Zamari and determines a power value (2^Zamari) through the interpolation process. The power calculator determines XY=2^Z=(2^Zamari)×(2^Zint), thereby resulting in the input value X to the power of Y.

Abstract: Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x coordinate value of the converted vector is positive, a y coordinate value of the converted vector is positive, and the x coordinate value is greater than or equal to the y coordinate value, a pipeline of vector rotators operable to perform a series of successive rotations of the converted vector to yield a rotated vector and to store rotation directions of the series of successive rotations, and at least one lookup table operable to yield an angle of rotation based on the rotation directions.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

Abstract: In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit.

Abstract: A decimal absolute value adder includes a first circuit adding two operands for a first result; a second circuit adding the two operands to 10 for a second result; a third circuit adding the two operands to 6 for a third result; a fourth circuit adding the two operands to 1 for a fourth result; a fifth circuit adding the two operands to 11 for a fifth result; a sixth circuit adding the two operands to 7 for a sixth result; and a selection circuit selecting the first, second, fourth or fifth result when adding two numbers of identical signs or adding two numbers of different signs resulting in a non-negative result, and selecting a 1's complement of the first, third, fourth or sixth result when adding two numbers of different signs resulting in a negative result.

Abstract: Techniques for implementing multipliers using memory blocks in an integrated circuit (IC) are provided. The disclosed techniques may reduce the number of memory blocks required to implement various multiplication operations. A plurality of generated products is normalized. The normalized products are scaled to generate a plurality of scaled products. Scaled products with the least root mean square (RMS) error are identified. The scaled products with the least RMS error are then stored in a plurality of memory blocks in an IC. The scaled products may have a reduced number of bits compared to the plurality of generated products that have not been normalized and scaled.

Abstract: Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.

Abstract: Methods for matrix processing and devices therefor are described. A systolic array in an integrated circuit is coupled to receive a first matrix as input; and is capable of operating in two modes, namely a triangularization mode and a back-substitution mode. The systolic array, when in a triangularization mode, is coupled to triangularize the first matrix to provide a second matrix. When in a back-substitution mode, the systolic array is coupled to invert the second matrix.

Abstract: A circuit for converting Boolean and arithmetic masks includes “m” converting units, wherein m is an integer greater than 1.

Abstract: Circuitry for deriving a range-reduced value of an angle represented by a number having a mantissa and an exponent includes memory that stores a table that identifies, for each one of a plurality of values of the exponent, a base fractional rotation associated with said one of said plurality of values of said exponent, and an incremental fractional rotation associated with each increment of said mantissa. The circuitry further includes a multiplier that multiplies the mantissa by the incremental fractional rotation to provide a product representing a mantissa contribution. An adder adds the base fractional rotation to any fractional portion of the mantissa contribution. The fractional portion of the result of that addition represents the range-reduced angle. That representation can be multiplied by a constant representing one complete rotation in a desired angular measurement system, to convert that representation to a value representing the range-reduced angle in that measurement system.

Abstract: A decoder, such as for example an MMSE MIMO decoder, and a method for decoding are described. An input channel matrix is obtained, and an extended channel matrix of the input channel matrix is generated. The extended channel matrix is triangularized to provide a triangularized matrix, and the triangularized matrix is inverted to provide an inverted triangular matrix. A left matrix multiplication result matrix associated with multiplication of the input channel matrix and the inverted triangular matrix is generated, and a weight matrix from the left matrix multiplication result matrix and the inverted triangular matrix is generated. A received symbols matrix is obtained, and a weighted estimation is generated and output using the weight matrix and the received symbols matrix to provide an estimate of a transmit symbols matrix for output of estimated data symbols.

Abstract: Nulling a cell of a complex matrix is described. A complex matrix and a modified Givens rotation matrix are obtained for multiplication by a processing unit, such as a systolic array or a CPU, for example, for the nulling of the cell to provide a modified form of the complex matrix. The modified Givens rotation matrix includes complex numbers c*, c, ?s, and s*, wherein the complex number s* is the complex conjugate of the complex number s, and wherein the complex number c* is the complex conjugate of the complex number c. The complex numbers c and s are associated with complex numbers of the complex matrix including the cell to be nulled. The modified form is then output by the processing unit. The modified Givens rotation matrix may be implemented as a systolic array or otherwise used for processing complex numbers or matrices.

Abstract: A phasor-based pulse detection system includes a first multiplier stage configured to apply a first delayed conjugate multiplication operation to an input signal. The system can also include a second multiplier stage coupled to the first multiplier stage and configured to apply a second delayed conjugate multiplication operation to an output of the first multiplier stage, and an absolute value unit coupled to the second multiplier stage and configured to perform an absolute value operation on an output of the second multiplier stage. The system can further include video filter stage coupled to the absolute value unit and configured to perform a video filtering operation on an output of the absolute value unit. The system can also include a hysteresis detector coupled to the video filter stage, the hysteresis detector configured for detecting a signal in a filtered video signal received from the video filter stage.