Abstract: A method of determining components present in a sample from spectral data obtained from the sample including resolving each of a plurality of models of the spectral data, the plurality of models including models having a different number of component reference spectra selected from a set of predetermined component reference spectra; selecting a one of the plurality of models based upon a model selection criterion and determining one or more components present in the sample based upon the selected model. The model selection criterion includes a measure for each model, which balances improvements in fit quality of the model to the spectral data against a complexity penalty determined from the number of component reference spectrum used in the model.

Abstract: Embodiments of the present disclosure include systems and methods for compiling tensor operators for neural network models based on tensor tile configurations. A tensor expression for a neural network model is received. A tensor tile configuration for the tensor expression is determined based on specifications associated with a set of hardware devices. Based on the tensor tile configuration, a set of code for implementing the tensor expression for the neural network model is generated. The set of code is for execution on the set of hardware.

Abstract: A method and apparatus for performing deep learning operations. A computation apparatus includes an adder tree-based tensor core configured to perform a tensor operation, and a multiplier and accumulator (MAC)-based vector core configured to perform a vector operation using an output of the tensor core as an input.

Abstract: A system and corresponding method perform image super-resolution (SR). The system comprises an element-unshuffled downsampler and an image SR module. The image SR module performs image SR on a low-resolution (LR) representation of a high-resolution (HR) original image. The HR original image is at a higher resolution relative to a resolution of the LR representation. The image SR module produces a reconstructed version of the HR original image via the image SR performed. The image SR is based on element-unshuffled downsampling of the LR representation. The element-unshuffled downsampler performs the element-unshuffled downsampling. The image SR module outputs the reconstructed version produced. The system performs the image SR with fewer parameters and less computation cost relative to conventional image SR.

Abstract: A system for in-memory computing comprises a volatile memory comprising at least a first layered subarray, wherein each subarray comprises a plurality of memory cells, and a plurality of sub-sense amplifiers connected to a read bitline of the first subarray of the memory, configured to compare a measured voltage of the read bitline to at least one threshold and provide at least one binary output corresponding to a logic operation based on whether the voltage of the read bitline is above or below the threshold. A method for in-memory computing is also disclosed.

Abstract: Processing circuitry receives coded information of a motion vector difference (MVD). The processing circuitry calculates cost values associated with value combinations for a plurality of bits in coding bits of the MVD, at least one of the plurality of bits is a bit in a codeword for indicating a magnitude for the MVD. The processing circuitry determines a combination of prediction values for the plurality of bits from the value combinations, the combination of prediction values is associated with a lowest cost value in the cost values. The processing circuitry decodes the coded information of the MVD to obtain one or more indicators for the combination of prediction values, the one or more indicators indicates whether the plurality of bits is correctly predicted by the combination of prediction values. The processing circuitry determines the MVD based on the combination of prediction values and the one or more indicators.

Abstract: A computer-implemented method includes identifying a multiplicity-bit size, constructing a multiplicity of independent Value Ranges, identifying an individual multiplicity-bit value as an initial first multiplicity-bit value, dividing each constructed Value Range into a multiplicity of contiguous Value-Range Bands that do not overlap and collectively encompass all possible values within the Value Range, using PRN values that range between the highest and lowest value within the Value Range associated with the first multiplicity-bit value, to identify a second multiplicity-bit value associated with the Value-Range Band the PRN falls within, concatenating the identified second multiplicity bit value to the first multiplicity-bit value to create a concatenated bit sequence of multiplicity-bit values, designating the second multiplicity-bit value a first bit value, and repeating the second multiplicity-bit identification sequence, concatenating all identified second multiplicity-bit values to the existing concate

Abstract: With respect to an information processing device which anonymizes data composed of records including one or more items through statistical processing, the information processing device includes a memory, and a processor configured to classify respective records constituting the data into one or more first sets, based on masking target items, a dictionary, and a selected hierarchy level, classify the respective records into one or more second sets with respect to a number of records belonging to each of the one or more first sets, and calculate a number of records of each of the one or more second sets and a ratio of records belonging to each of the one or more second sets to the records constituting the data, change the selected hierarchy level based on the ratio and priority set in advance, and create a statistically processed record by statistically processing records belonging to a same first set.

Abstract: Described herein is a simulation of an input quantum circuit, comprising a machine-readable specification of a quantum circuit. Aspects include partitioning the input quantum circuit into a group of sub-circuits based on at least two groups of qubits identified for tensor slicing, wherein the resulting sub-circuits have associated sets of qubits to be used for tensor slicing. The simulating can occur in stages, one stage per sub-circuit. A set of qubits associated with a sub-circuit can be used to partition the simulated quantum state tensor for the input quantum state circuit into quantum state tensor slices, and the quantum gates in that sub-circuit can used to update the quantum state tensor slices into updated quantum state tensor slices. The updated quantum state tensor slices are stored to secondary storage as micro slices.

Abstract: A system and method for data processing and storage using quantum and deoxyribonucleic acid (DNA) computing. The method includes receiving a request for a search data item. The request includes a first information represented by classical binary bits. The request is converted into a converted request. The converted request includes the first information represented by quantum bits. One or more servers are searched based on the converted request using a quantum search algorithm. Search results are generated. The search results are ranked according to ranking rules. A highest-ranked result includes a second information represented by quantum bits. The highest-ranked result is converted to a converted highest-ranked result. The converted highest-ranked result includes the second information represented by DNA bits. The converted highest-ranked result is encrypted to generate an encrypted and converted highest-ranked result. The encrypted and converted highest-ranked result is stored in one or more DNA strands.

Abstract: Provided is an optimization method including executing a ground state search for an interaction model by a ground state search in a surrogate interaction model including D (D is a natural number of three or more) variable groups each having N continuous variables by using an information processing apparatus, the interaction model having a third-order or higher-order energy function including N (N is a natural number) continuous variables and discrete variables. The ground state search is executed based on simulated annealing. An interaction relation of the surrogate interaction model has a complete D-part graph structure. A coupling is set between i-th variable pairs in the respective variable groups of the surrogate interaction model. The information processing apparatus is operated to simultaneously update all variables of one variable group from among the D variable groups when performing a state transition in the surrogate interaction model.

Abstract: Techniques for adjusting outlier datasets for training chatbot systems in natural language processing are disclosed. In one particular aspect, a method is provided that includes receiving a dataset that includes training or inference data. An initial set of outlier data points can be identified within the dataset based on a score of the outlier data points being above or below a threshold. The initial set can be adjusted by identifying one or more nearest neighbors, which can be included in the dataset. Outlier data points that include a label that matches a number of labels of the nearest neighbors that exceeds a predetermined threshold can be removed from the initial set of outlier data points to generate a final set. Outlier data points of the final set can be adjusted with respect to the dataset to generate a set of training data that is used to train a machine-learning model.

Abstract: An apparatus, method and system for adjusting a voltage stabilization output of a power source (10). The power source (10) forms an output voltage based on a supply current. The apparatus includes a sampling module (11), a PID adjustment module (12) and a control module (13). The sampling module (11) is configured to sample the output voltage of the power source (10) to obtain a sampled voltage (S100). The PID adjustment module (12) is configured to obtain a switching frequency signal by PID control adjustment based on the sampled voltage and a preset control parameter. The PID control adjustment includes a voltage loop control adjustment and a voltage-difference-change-rate loop control adjustment (S200). The control module (13) is configured to form the supply current according to the switching frequency signal (S300). The voltage stabilization output of the power source (10) can be realized.

Abstract: An entropy decoder is configured to, for horizontal and vertical components of motion vector differences, derive a truncated unary code from the data stream using context-adaptive binary entropy decoding with exactly one context per bin position of the truncated unary code, which is common for horizontal and vertical components of the motion vector differences, and an Exp-Golomb code using a constant equi-probability bypass mode to obtain the binarizations of the motion vector differences. A desymbolizer is configured to debinarize the binarizations of the motion vector difference syntax elements to obtain integer values of the horizontal and vertical components of the motion vector differences. A reconstructor is configured to reconstruct a video based on the integer values of the horizontal and vertical components of the motion vector differences.

Abstract: An integrated circuit comprising a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of MACs connected in series and (ii) a plurality of data paths including an accumulation data path, wherein each MAC includes a multiplier to multiply to generate product data and an accumulator to generate sum data. The integrated circuit further comprises a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with a MAC pipeline, wherein each control/configure circuit includes an accumulation data path which is configurable to directly connect to the accumulation data path of the MAC pipeline to form an accumulation ring when the control/configure circuit is configured in an accumulation mode, and an output data path configurable to directly connect to the output of the accumulation data path of the MAC pipeline when the control/configure circuit is configured in an output data mode.

Abstract: A process-in-memory architecture based on a resistive random access memory and a matrix decomposition acceleration algorithm, which is configured for transformer neural network acceleration. The present disclosure first optimizes a self-attention computing process, decomposes a weight matrix, and reduces computing and writing operands; and further reduces whole power consumption using a softmax computing array of a selection and comparison logic structure based on the resistive random access memory. The present disclosure proposes an optimized matrix multiplication computing based on Re-Transformer, and further eliminates data dependency and reduces computing delay in scaled dot-product attention by using matrix decomposition. Meanwhile, the present disclosure reduces power consumption by using hybrid softmax based on the resistive random access memory.

Abstract: A hybrid computer comprising a quantum processor can be operated to perform a scalable comparison of high-entropy samplers. Performing a scalable comparison of high-entropy samplers can include comparing entropy and KL divergence of post-processed samplers. A hybrid computer comprising a quantum processor generates samples for machine learning. The quantum processor is trained by matching data statistics to statistics of the quantum processor. The quantum processor is tuned to match moments of the data.

Abstract: A software architecture where the software architecture processes a method, wherein the method includes defining initial conditions for a set of Büttiker probes. The set of Büttiker probes include various interaction equations between one or several many-body systems. The method includes computing properties of particles with quantum transport methods. A quantum transport method of the quantum transport methods include a set of Büttiker probes. The particles include the particles of one or several many-body systems. Further, the method includes calculating a current for each Büttiker probe of the set of Büttiker probes. The current includes at least one of momentum current, particle current, energy current, spin current, color charge or chirality current. The method includes setting up a set of continuity equations such that for each continuity equation a calculated current of a Büttiker probe is in a particular relation with an another calculated current of an another Büttiker probe.

Abstract: A transformer compute apparatus and method of operation therefor. The apparatus receives matrix inputs in a first format and generates projection tokens from these inputs. Among others, the apparatus includes a first cache device configured for processing first projection tokens and a second cache device configured for processing second projection tokens. The first cache device stores the first projection tokens in a first cache region and stores these tokens converted to a second format in a second cache region. The second cache device stores the second projection tokens converted to the second format in a first cache region and stores the converted second projection tokens after being transposed. Then, a compute device performs various matrix computations with the converted first projection tokens and transposed second projection tokens. Re-processing data and expensive padding and de-padding operations for transposed storage and byte alignment can be avoided using this caching process.

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Abstract: A strain gauge has a mounting structure for mounting to a portion being measured. A base member of the strain gauge is partly fixed, by an adhesive, to the portion being measured. The base member includes a first base portion and a second base portion that are mutually separately positioned in a longitudinal direction, a resistance element being provided in the first base portion and a terminal being provided in the second base portion. The first base portion is fixed by a layer of adhesive to the portion being measured, and the layer of the adhesive is not provided on the second base portion such that the second base portion is not fixed to the portion being measured.

Abstract: Methods, systems, and apparatus, for totally corrective boosting with cardinality penalization are described. One of the methods includes obtaining initialization data identifying training examples, a dictionary of weak classifiers, and an active weak classifier matrix. Iterations of a totally corrective boosting with cardinality penalization process are performed, wherein each iteration performs operations comprising selecting a weak classifier from the dictionary of weak classifiers that most violates a constraint of a dual of the primal problem. The selected weak classifier is included in the active weak classifier matrix. The primal problem is optimized, and a discrete weight vector is determined. Weak classifiers are identified from the active weak classifier matrix with respective discrete weights greater than a threshold. The regularized risk is optimized, and a continuous weight vector is determined.

Abstract: In an example embodiment, a model is trained to specifically identify reversal points in data and then to rank these reversal points in order of importance. A reversal point shall be defined as a point in which a particular metric, specifically a first order derivative, crosses over from positive to negative or vice-versa. Users are more likely to be interested in abnormal and significant changes in data, and thus the machine-learned model is trained to evaluate a reversal point based on two dimensions: abnormality and significance.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate multireference parallelization of variational quantum computing to achieve high accuracy with short circuit depths. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a trial component that prepares a multireference trial state based on a qubit operator, by applying a unitary circuit operator to a sum of selected initial configurations.

Abstract: Heterogeneous monitoring nodes may each generate a series of monitoring node values over time associated with operation of an industrial asset. An offline abnormal state detection model creation computer may receive the series of monitoring node values and perform a feature extraction process using a multi-modal, multi-disciplinary framework to generate an initial set of feature vectors. Then feature dimensionality reduction is performed to generate a selected feature vector subset. The model creation computer may derive digital models through a data-driven machine learning modeling method, based on input/output variables identified by domain experts or by learning from the data. The system may then automatically generate domain level features based on a difference between sensor measurements and digital model output.

Abstract: A secure joining system is a secure joining system including a plurality of secure computing apparatuses. The plurality of secure computing apparatuses include a vector joining unit 11n, a first vector generation unit 12n, a first permutation calculation unit 13n, a first permutation application unit 14n, a second vector generation unit 15n, a third vector generation unit 16n, a second permutation calculation unit 17n, a second permutation application unit 18n, a fourth vector generation unit 19n, a fifth vector generation unit 110n, a first inverse permutation application unit 111n, a first vector separation unit 112n, a second inverse permutation application unit 113n and a second vector separation unit 114n, a third permutation application unit 115n, a fourth permutation application unit 116n, and a first joined table generation unit 117n.

Abstract: Provided are an area allocation device and the like that can efficiently allocate memory volume for processing of matrix operations. The area allocation device specifies array identifiers representing positions of elements storing a value different from a predetermined value in each array of subarray information in array information, arrays consisting of a plurality of element, the array information including a plurality of information representing the arrays, the subarray information corresponding to at least a part of the arrays; calculates a number of the specified array identifiers; and allocates a memory area having a memory volume depending the calculated number.

Abstract: A bilevel coordinated optimization method for fixed and mobile charging facilities on highways, includes: constructing an optimization model framework which includes an upper-layer coordinated location optimization model and a lower-layer coordinated capacity optimization model, where the upper-layer coordinated location optimization model is used to optimize locations of charging stations and determine locations and time points of charging demands that require truck mobile charger (TMC) deployment, while the lower-layer coordinated capacity optimization model is used to optimize TMC and fixed charger (FC) capacities at candidate sites, improving an utilization rate of FCs; and performing equivalent linearization on a nonlinear problem using a big-M method and converting the problem into a mixed-integer linear programming model, and implementing a data exchange process between upper and lower layers using analytical target cascading.

Abstract: In one aspect, a method includes identifying (i) a computational problem that is a candidate for a quantum computation, and (ii) one or more numerical algorithms for solving the candidate computational problem; providing input task data identifying (i) the candidate computational problem, and (ii) the one or more numerical algorithms, to a numerical quantum experimentation system, wherein the numerical quantum experimentation system comprises multiple universal numerics workers, a universal numerics worker, of the multiple universal numerics workers being configured to solve the candidate computational problem using the one or more numerical algorithms; receiving, from the numerical quantum experimentation system, data representing results of the one or more numerical algorithms to solve the candidate computational problem; and determining whether the received data indicates that a quantum computation applied to the candidate computational problem has a greater efficacy at a solution than a classical computat

Abstract: A method includes determining a free water level in the reservoir, analyzing a free water pressure trend of the free water phase, determining a presence of anomalous pressures and salinities within the free water phase, determining whether gas down to models and water up to models fit the reservoir, determining a bi-modal pore throat distribution of the plurality of pores within the reservoir, and generating a difference map to model the water distribution in the reservoir.

Abstract: Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) processing elements (PEs). Selective variation of the precision of an array of MAC PEs may reduce power consumption of a neural processor. Power may be conserved by dynamically controlling the precision of analog to digital (ADC) output bits for one or more MAC PEs. Dynamic control of ADC output bit precision may be based on precision information determined during training and/or post-training (e.g., quantization) of an artificial intelligence (AI) neural network (NN) model implemented by the neural processor. Precision information may include a range of dynamic precision for each of a plurality of nodes of a computation graph for the AI NN model.

Abstract: An information processing device is provided with a data receiving unit having a function of receiving first algorithm data that is data stating a first algorithm from a first information processing device, a computation execution unit having a function of executing computations based on the first algorithm stated in the first algorithm data received by the data receiving unit and using data stored in a first storage unit in the computations on a basis of the first algorithm data and the data stored in the first storage unit, and a data transmitting unit having a function of transmitting second algorithm data that is data stating a second algorithm according to the first algorithm to a second information processing device.

Abstract: A method for obtaining server-side and client-side calculations performed in a document includes presenting, on a client computer, the document stored on a server and receiving an input, where the input causes a calculation in the document. The client computer performs the calculation on the client computer and sends the input to the server to concurrently perform the calculation on the server. The client computer obtains a first result from the calculation performed on the client computer and a second result from the calculation performed on the server, selects the first result or the second result as a selected result based on which of the first result or the second result is obtained quicker from the calculation performed on the client computer and the calculation performed on the server, and presents, in the document, the selected result to the user.

Abstract: A method for controlling a motor-vehicle electronic control unit with a view to acquiring the measurement of a physical quantity using a digital sensor connected to the electronic control unit, in which method the sensor sends measurement digital data with a send period and the electronic control unit processes these measurement data with a processing period, the send period being shorter than the processing period. At the end of each processing period, the average value of the measured physical quantity is determined over an interval of N preceding processing periods.

Abstract: A method comprises receiving a kernel used to convolve with an input tensor. For a first dimension of the kernel, a square block of values for each single dimensional vector of the kernel that includes all rotations of that single dimensional vector is generated. For each additional dimension of the kernel, group blocks of an immediately preceding dimension into sets of blocks, each set of blocks including blocks of the immediately preceding dimension that are aligned along a vector that is parallel to the axis of the dimension; and generate, for the additional dimension, one or more blocks of values, each block including all rotations of blocks within each of the sets of blocks of the immediately preceding dimension. The block of values corresponding to the last dimension in the additional dimensions of the kernel is output as the expanded kernel.

Abstract: A downhole multi-modality inspection system includes a first imaging device operable to generate first imaging data and a second imaging device operable to generate second imaging data. The first imaging device includes a first source operable to emit energy of a first modality, and a first detector operable to detect returning energy induced by the emitted energy of the first modality. The second imaging device includes a second source operable to emit energy of a second modality, and a second detector operable to detect returning energy induced by the emitted energy of the second modality. The system further includes a processor configured to receive the first imaging data and the second imaging data, and integrate the first imaging data with the second imaging data into an enhanced data stream. The processor correlates the first imaging data and the second imaging data to provide enhanced data for detecting potential wellbore anomalies.

Abstract: An example electronic user device includes memory; instructions; and processor circuitry to execute the instructions to identify a stylus grip pattern indicative of a grip of a user on a stylus based on signal data corresponding to signals output by a sensor of the stylus; select one of a first stylus mode or a second stylus mode for the stylus based on the stylus grip pattern; interpret an interaction between the stylus and the electronic user device based on the selected one of the first stylus mode or the second stylus mode; and cause the electronic user device to respond to the interaction.

Abstract: Provided an apparatus configured to calculate a periodicity of time series data, generate a plurality of subsequences, from the time series data, a length of each subsequence set to the periodicity, calculate feature values of the plurality of subsequences; categorize the plurality of subsequences, based on the feature values thereof, into one or more groups, find a periodicity of the subsequences belonging in common to one group, based on an occurrence order of the subsequences belonging in common to the one group and perform missing event detection by identifying the subsequence, occurrence of which is expected according to the periodicity of the subsequences belonging in common to the one group, but not found.

Abstract: An optical element includes: a glass substrate; an optical function portion made of a resin; and a bonding portion that bonds the glass substrate and the optical function portion to each other. The bonding portion has a glass transition point of 85° C. or lower. The glass transition point of the bonding portion may be 50° C. or lower.

Abstract: In a general aspect, quantum computing system performance is tested. Systems and methods for testing hardware in a quantum computing system are described. The methods may include certification/decertification of data produced by the quantum computing system, detection of faults, correction of errors and/or recalibration/replacement of the quantum computing system or a quantum computing subsystem.

Abstract: Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

Abstract: The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located.

Abstract: Examples described herein generally relate to performing conformance testing of a computational operation. A reference result including one or more reference intermediate products and a reference accumulator output at a first level of precision can be generated for the computational operation and based on one or more inputs. A hardware result can similarly be created using hardware at a second level of precision. The reference result can be compared to the hardware result to determine a variance value. A conformance result can be output based on whether the variance value is within a threshold range.

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Abstract: The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i?1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Abstract: Embodiments of quantum ring oscillator-based coherence preservation circuits including a cascaded set of stages are described. Embodiments of such quantum ring oscillator-based coherence preservation circuits allow the internal (superpositioned) quantum state information of stored qubits to be preserved over long periods of time and present options for the measurement and potential correction of both deterministic and non-deterministic errors without disturbing the quantum information stored in the structure itself.

Abstract: Systems and methods are described for detecting anomalies within data, such as time series data. In one example, unlabeled data, such as time series data, may be obtained. At least one data point, representing an artificial anomaly, may be inserted into the data. The data may then be divided into a number of different windows. The windows may have a fixed size and may at least partially overlap in time. The data contained within different windows may be compared, to each other and to the injected data point, to determine an anomaly score for individual windows. The anomaly score may indicate a likelihood that a given window contains an anomaly. In a specific example, a convolution neural network may be trained based on the data and inserted data points representing anomalies, where a contrastive loss function is used to represent different portions of the data in the neural network.

Abstract: A method and system for rotating a vector, including at least one lookup table (LUT) including data corresponding to the vector being rotated around a first angle and a second angle, processing circuitry configured for accessing the at least one LUT for incrementally rotating the vector around the first and second angles, where accessing includes identifying an LUT input entry and selecting a corresponding LUT output entry, the corresponding output entry including an incremental angular rotation (IAR) of the vector around the first angle or the second angle, and a comparator configured to generate a comparator signal based upon comparing a counter incremented by the IAR with the first angle or the second angle, the processing circuitry further configured to iteratively access the at least one LUT, based on the comparator signal, for completing the incremental rotation of the vector around the first angle and the second angle.

Abstract: The present disclosure relates to a method and an apparatus for representation of a sparse matrix in a neural network. In some embodiments, an exemplary operation unit includes a buffer for storing a representation of a sparse matrix in a neural network, a sparse engine communicatively coupled with the buffer, and a processing array communicatively coupled with the sparse engine. The sparse engine includes circuitry to: read the representation of the sparse matrix from the buffer, the representation comprising a first level bitmap, a second level bitmap, and an element array; decompress the first level bitmap to determine whether a block of the sparse matrix comprises a non-zero element; and in response to the block comprising a non-zero element, decompress the second level bitmap using the element array to obtain the block of the sparse matrix. The processing array includes circuitry to execute the neural network with the sparse matrix.

Abstract: A method of video decoding can include receiving a bit stream including coded bits of bins of syntax elements. The syntax elements are of various types that correspond to transform coefficients of a transform block in a coded picture. Context modeling is performed to determine a context model for each bin of the syntax elements. In a given frequency region of the transform block, for one type of the syntax elements, a group of the transform coefficients having different template magnitudes within a predetermined range share a same context model, or one of the transform coefficients uses the same context model for possible different template magnitudes of the one of the transform coefficients. The possible different template magnitudes are within the predetermined range. The coded bits are decoded based on the context models determined for each bin of the syntax elements to determine the bins of the syntax elements.