Abstract: A method and apparatus for computing leading zero count with offset (LZCO) using a parallel nibble calculation scheme. The invention receives as its input a first operand and a second “offset” operand. The first operand is identified by a plurality of nibbles, each comprising four bits. The LZCO calculator calculates the lower two bits of the result for each nibble while simultaneously (or in parallel) calculating the upper remaining bits of the result for each nibble. The LZCO also selects the resulting nibble calculation for the lower two bits and the upper bits according to the nibble that corresponds to the highest order nibble without all zero values.

Abstract: Method and apparatus are described for anticipating the number of leading zeros or leading ones in a sum of mantissas irrespective of the sign of the result or the relative magnitudes of the input operands using a leading zero anticipation (LZA) device. An algorithm is presented for leading zero and leading one anticipation that may be used to remove leading zeroes or ones from sums produced in arithmetic units. This algorithm and the design of the combinational logic does not require a comparison of input operands nor does it need two separate counters for leading zeros and leading ones as in most other LZAs. The present invention is especially applicable to redundant format addition.

Abstract: A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.

Abstract: One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.

Abstract: An apparatus and method is provided for determining locations of a predetermined value in a sequence of data bits. Each location is determined independently of the others thereby allowing them to be found more quickly. This has particular application to block memory loads and block stores to memory, wherein ones in the register list in the instruction word indicate the registers to be loaded or stored. Thus, in these applications the present invention enables the positions of these ones to be determined quickly.

Abstract: An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.

Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.

Abstract: When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.

Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.

Abstract: A device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic circuit activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder generates a signal encoding the priority of the highest priority inactive all-zero signal, and muxes select first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal.

Abstract: A low voltage swing priority encoder comprising pass cells to provide differential voltages indicative of the leading one of a binary tuple. A tree structure with bypass paths allows for the minimization of the number of pass cells in a signal propagation path so as to reduce signal delay. The pass cells are responsive to control voltages indicative of various Boolean functions of the binary tuple, and a pulse voltage signal is applied to the pass cells. In response to the control voltages and the pulse voltage signal, the pass cells provide differential voltages so that voltage swing of the differential voltages are kept below the supply voltage to reduce dynamic power dissipation. Sense amplifiers sense the differential voltages to provide the final logic level indicative of the leading one of the binary tuple.

Abstract: A system and method of expediting bit scan instructions in a microprocessor is disclosed which employs an execution unit having zero detectors organized along predetermined boundaries for detecting in parallel, the number of leading or trailing zeros in a source operand and for writing a destination index to indicate the first non-zero bit position.

Abstract: An exemplary embodiment of the invention is a method and system for converting a number from binary to decimal. The method includes obtaining an N-bit binary number and then determining the number of multiplications necessary to complete the conversion process by first determining the number of leading zeroes. The method then divides the N-bit number into 12-bit segments where each segment is represented as a binary coded decimal number. The method then multiplies at least one binary coded decimal number by a variable in response to the number of multiplications to determine the resulting decimal value.

Abstract: A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate.

Abstract: A FOD (First-One-Detector) circuit for detecting the number of leading zeros counted from a most significant bit to a first one in a binary number includes a plurality of sub-FODs respectively having a plurality of unit blocks connected in cascade, when a fraction input is less than 16 bits, depending on the number of bits and respectively provided with a plurality of transmission transistors. When the fraction input is more than 16 bits, the plurality of sub-FODs respectively output the number of leading zeros with regard to predetermined bits of fraction inputs, and a determinative signal for determining whether the fraction inputs are all zeros. The sub-FODs respectively further include an encoding circuit for encoding the number of leading zeros outputted from the plurality of sub-FODs and the determinative signal and outputting the resultant number of leading zeros. The FOD circuit employs a fewer number of transistors and realizes a faster normalization by a quick detection of leading zeros.

Abstract: A method and circuit for determining the position of a leading logical one or a trailing logical one in a first n bit operand is disclosed. The method and circuit generates an n bit operand from the first n bit operand. One bit of the n bit operand represents a first logical value while the remaining bits of the n bit operand represent a second logical value. Thereafter, the method and circuit generates a k bit operand relating to the position of the leading or trailing logical one in the first n bit operand. The k bit operand is generated from the n bit operand.

Abstract: A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each segment. Each segment undergoes all zeros detection, all ones detection, modified zeros detection, and modified ones detection. The modified zeros detection and modified ones detection are both done based on the control field. Each detection for each segment generates a response. Then, a pair of the four responses, or a clear responses signal, is selected for each of the segments based on the control field. From the selected responses, the method determines if the normalized data field is all zeros or all ones.

Abstract: An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path, conversely, is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The execution unit may also include a plurality of add/subtract pipelines, allowing vectored add, subtract, and integer/floating point conversion instructions to be performed. The execution unit may also be expanded to handle additional arithmetic instructions (such as reverse subtract and accumulate functions) by appropriate input multiplexing.

Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.

Abstract: Zero detect of a difference of binary operands is disclosed. If the difference is zero, the bit-complement of the difference is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the difference is non-zero, the bit-complement of the difference will contain one or more zero's, and therefore incrementing the bit-complemented difference will generate a carry-out bit of zero. The operands include a minuend and M subtrahends. One embodiment includes providing a result representing a bit-complement of the difference, and then inspecting a carry-out bit generated by incrementing the result.

Abstract: A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of the floating point adder. The leading zero anticipator outputs a control signal to a shifter to shift the sum of the significand adder to eliminate the leading zeros. The number of leading zeros is also provided to an exponent circuit that reduces the magnitude of the exponent to reflect the shifted significand. The leading zero anticipator includes a pattern generator that outputs an intermediate pattern with a number of leading zeros approximately equal to the number of leading zeros in the sum. A counter circuit counts the number of leading zeros and provides one or more one-hot control signals to the shifter. In one embodiment, the significand shifter implements two stages of one-hot multiplexers to provide the desired shift.