Abstract: Certain aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may receive at least one bit indicating a particular set of control symbols, of a plurality of sets of control symbols, comprising a downlink control region identify a location of a demodulation reference signal (DMRS), associated with a data channel, based at least in part on the at least one bit indicating the particular set of control symbols comprising the downlink control region; and communicate on the data channel based at least in part on the DMRS. Numerous other aspects are provided.

Abstract: Methods for managing a communication session in a communication network are disclosed. For example, a method includes detecting, by a first endpoint comprising at least one processor, an error condition associated with the communication session, sending, by the first endpoint, a notification of the error condition to a second endpoint that is using a transport layer session and receiving, by the first endpoint, a communication from the second endpoint, proposing a response to the error condition. Another method includes receiving, by a first endpoint comprising at least one processor, a notification of an error condition associated with the communication session, selecting, by the first endpoint, a response to the error condition, and sending, by the first endpoint, a communication to a second endpoint that is using a transport layer session, proposing a response to the error condition.

Abstract: Aspects of the present disclosure relate to an apparatus comprising analogue circuitry comprising an entropy source, the entropy source being configured to provide a random output. The apparatus comprises first digital circuitry to receive the output of the entropy source and, based on said output, generate random numbers, and second digital circuitry to receive the output of the entropy source and, based on said output, generate random numbers, the second digital circuitry being a duplicate of the first digital circuitry. The apparatus comprises difference detection circuitry to determine a difference of operation between the first digital circuitry and the second digital circuitry. Each of the first digital circuitry and the second digital circuitry comprises entropy checking circuitry to check the entropy of the output of the entropy source.

Abstract: Provided are a multi-pattern policy detection system and method, wherein, in an environment that operates a plurality of policies for determining matching or non-matching by a string or a normalized format, the plurality of policies are expressed by a data structure that is searchable at a time, and are optimized to improve search performance.

Abstract: Systems and methods are disclosed for creating mechanical computing mechanisms and Turing-complete systems which include combinatorial logic and sequential logic, and which are energy-efficient.

Abstract: A system includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

Abstract: Methods and apparatus for vector-matrix comparison are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry decodes an instruction, where operands of the instruction specifies an output location to store output results, a vector of data element values, and a matrix of data element values. The execution circuitry executes the decoded instruction. The execution includes to map each of the data element values of the vector to one of consecutive rows of the matrix; for each data element value of the vector, to compare that data element value of the vector with data element values in a respective row of the matrix and obtain data element match results. The execution further includes to store the output results based on the data element match results, where each output result maps to a respective data element column position and indicates a vector match result.

Abstract: Methods and apparatus for vector-matrix comparison are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry decodes an instruction, where operands of the instruction specifies an output location to store output results, a vector of data element values, and a matrix of data element values. The execution circuitry executes the decoded instruction. The execution includes to map each of the data element values of the vector to one of consecutive rows of the matrix; for each data element value of the vector, to compare that data element value of the vector with data element values in a respective row of the matrix and obtain data element match results. The execution further includes to store the output results based on the data element match results, where each output result maps to a respective data element column position and indicates a vector match result.

Abstract: A number of non-overlapping instances of a substring occurring within a string of data elements can be determined through a method that includes partitioning and distributing the string to an ordered list of equal length segments that each have a length greater or equal to L. A substring match within a target segment of the ordered list of segments can be detected by sequentially comparing the substring with each segment of the ordered list of segments. It can be subsequently determined that the target segment contains additional data elements, and a new segment can be generated by clearing L?1 data elements following a position of the substring match in the target segment. An additional substring match can be detected by comparing the substring with the new segment.

Abstract: Move string processing via inline decode-based micro-operations expansion. An instruction is obtained, and the instruction, which is to perform a move string operation, is decoded. The decoding provides a sequence of operations to perform the move string operation. The sequence of operations includes a load to boundary operation to load an amount of data up to a specified boundary of memory. The data to be loaded as part of the move string operation.

Abstract: Compare string processing via inline decode-based micro-operations expansion. An instruction, which is to perform a compare string operation, is decoded. The decoding provides a sequence of operations to perform the compare string operation. The sequence of operations includes a first load to boundary operation to load a first set of data up to a specified boundary of memory and a second load to boundary operation to load a second set of data. The first set of data and the second set of data are loaded as part of the compare string operation.

Abstract: A method of non-supervised deinterleaving of pulse trains comprises at least one N-dimensional enrichment step, N being an integer greater than 1.

Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

Abstract: Configurable operating mode memory devices are disclosed. In at least one embodiment, a memory device is configurable into one or more operating modes. An array of memory cells can be allocated into one or more partitions where each partition is associated only with a particular mode of operation. In at least one other embodiment, a memory device is configured to store user data in a portion of a memory array and to store data corresponding to a logical function associated with a different operating mode of the memory device in a different portion of the memory array.

Abstract: In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.

Abstract: Described herein are methods and systems capable of dynamically adapting weights in response to a received stream of pulses by deinterleaving a stream of pulses according to an initial weighted distance, adjusting the weighted distance, and deinterleaving the stream of pulses according to the adjusted weighted distance.

Abstract: A computer system is operable to identify subfields that differ in two data elements using a bit matrix compare function between a first matrix filled with pattern elements and a reference pattern.

Abstract: An integrated circuit includes a search unit configured to access an input vector including a number of bits, and to find a first and a second instance of a predetermined bit value such as a logic zero or a logic one, for example. The search unit may be further configured to generate an output that includes an indication of a bit position of the first instance of the predetermined bit value within the input vector, and an indication of a bit position of the second instance of the predetermined bit value within the input vector.

Abstract: An RF test and measurement device, including a front end for receiving a time-varying signal and a real-time engine for generating digital frequency domain spectrums based on the time-varying signal. The device also includes a memory subsystem containing a frequency domain bitmap which is updated through sequential receipt and storage of the digital frequency domain spectrums. The real time engine is further configured to monitor the frequency domain bitmap for occurrence of a signal characteristic, and in response to detection of the signal characteristic, cause a capture of the time-varying signal into a storage location of the RF test and measurement device.

Abstract: The present invention relates to a method and device for detecting a transmission signal on the basis of a received signal by applying a division and detection algorithm. An embodiment of the invention provides a method of detecting a transmission signal including: obtaining a unitary matrix and an upper triangular matrix by performing a sorted QR-decomposition algorithm with respect to a matrix indicating a channel state; calculating a vector y by multiplying a transpose matrix of the unitary matrix by the received signal Y; dividing the upper triangular matrix R into a plurality of sub-upper triangular matrices and dividing the calculated vector y into a plurality of sub-vectors so as to correspond to the divided plurality of sub-upper triangular matrices; and detecting a lattice point corresponding to each of the divided sub-vectors using the divided plurality of sub-upper triangular matrices.

Abstract: A method of and apparatus for searching for a signature in a packet according to a signature location. The method may include extracting a sub-payload to be compared with a signature from a payload of a packet, generating an offset that is location information about a location of the sub-payload in the payload, generating a search key that includes the extracted sub-payload and the generated offset, and performing ternary content addressable memory (TCAM) matching to check if the generated search key matches a TCAM entry.

Abstract: An apparatus including logic to receive a data packet comprising a string of characters, said apparatus having a plurality of states and at least one state for every character position in the string of characters; logic to examine the string of characters for matches with a plurality of predefined values, beginning with an initial character; and logic to execute forward exit transitions from any of the plurality of states based upon the examination of the characters, wherein a current state of the apparatus represents a count of a number of characters from the initial character of the string of characters.

Abstract: A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data word bid and an adjacent data word bit to provide a first output bit and a second logic circuit connected to receive the first output bit and a different adjacent bit of the data word to provide a second output bit representing a corrected value of the unique bit.

Abstract: Efficient hardware implementations of a binary search algorithm are provided.

Abstract: A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits.

Abstract: A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer strings.

Abstract: A computer system is operable to identify subfields that differ in two data elements using a bit matrix compare function between a first matrix filled with pattern elements and a reference pattern.

Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Abstract: A method and device for performing a cryptographic operation by a device controlled by a security application executed outside thereof in which a cryptographic value (y) is produced a calculation comprising at least one multiplication between first and second factors containing a security key (s) associated with the device and a challenge number (c) provided by the security application. The first multiplication factor comprises a determined number of bits (L) in a binary representation and the second factor is constrained in such a way that it comprises, in a binary representation, several bits at 1 with a sequence of at least L?1 bits at 0 between each pair of consecutive bits to 1 while the multiplication is carried out by assembling the binary versions of the first factor shifted according to positions of the bits at 1 of the second factor, respectively.

Abstract: An information processing apparatus includes: a register holding a value input thereto; a first communication path through which an addition command is input; a second communication path through which a subtraction command is input; addition means adding a predetermined value to a register value held in the register according to the addition command input through the first communication path and causing the register to hold a value resulting from the addition; and subtraction means subtracting a predetermined value from a register value held in the register according to the subtraction command input through the second communication path and causing the register to hold a value resulting from the subtraction, wherein the addition means and the subtraction means operate exclusively of each other.

Abstract: Methods and apparatus, including computer systems and program products, for normalizing computer-represented collections of objects. A first minimum value can be normalized based on a second minimum value of a universal set object that corresponds to the first set object. The second minimum value is both a minimum value supported by a data type (e.g., 1-byte integer) and a minimum value defined to be in the universal set object (e.g., 0 for a universal set of all natural numbers). Similarly, a first maximum value can be normalized based on a second maximum value of the universal set object where the second maximum value is both a maximum value supported by a data type and in the universal set object. Intervals can be normalized, which can involve replacing half-open intervals with equivalent half-closed intervals. Also, a consecutively ordered, uninterrupted, sequence of values of a set object can be normalized.

Abstract: A technique to accelerate range detection in a spline calcuation. In one embodiment, an instruction and corresponding logic are provided to perform range detection within a computer or processor.

Abstract: The present application addresses a fundamental problem in the design of computing systems, that of minimising the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.

Abstract: In accordance with one or more aspects, an initial output string is generated by a random number generator. The initial output string is sent to a random number service, and an indication of failure is received from the random number service if the initial output string is the same as a previous initial output string received by the random number service. Operation of the device is ceased in response to the indication of failure. Additionally, entropy estimates for hash values of an entropy source can be generated by an entropy estimation service based on hash values of various entropy source values received by the entropy estimation service. The hash values can be incorporated into an entropy pool of the device, and the entropy estimate of the pool being updated based on the estimated entropy of the entropy source.

Abstract: A method and system are provided for determining a location of a predetermined N bit sequence in a data stream. The method comprises the steps of determining two N bit data words from consecutive bits of the data stream, and providing N, N bit comparators. A first N bits of the two N bit data words is compared with the predetermined N bit data sequence by a first of the N comparators, and a next N bits, starting at a second bit, of the two N bit data words are compared with the predetermined N bit sequence by a second of the N bit comparators. These comparisons are repeated, incrementing the starting bit, until N comparators have been employed and the first through N bits have been employed as the starting bit.

Abstract: The present invention relates to a method and device for detecting a transmission signal on the basis of a received signal by applying a division and detection algorithm. An embodiment of the invention provides a method of detecting a transmission signal including: obtaining a unitary matrix and an upper triangular matrix by performing a sorted QR-decomposition algorithm with respect to a matrix indicating a channel state; calculating a vector y by multiplying a transpose matrix of the unitary matrix by the received signal Y; dividing the upper triangular matrix R into a plurality of sub-upper triangular matrices and dividing the calculated vector y into a plurality of sub-vectors so as to correspond to the divided plurality of sub-upper triangular matrices; and detecting a lattice point corresponding to each of the divided sub-vectors using the divided plurality of sub-upper triangular matrices.

Abstract: In a signature searching system, contents of a ternary content addressable memory (CAM) are searched to obtain a first index value that corresponds to a first group of predetermined data sequences. The first group of predetermined data sequences is selected from among a plurality of groups of predetermined data sequences based, at least in part, on the first index value, and a determination made as to whether any of the predetermined data sequences within the first group is present within a stream of data.

Abstract: A device and a method for automatic, computer-based similarity weighting of text expressions. The system and method contemplate a document data bank unit, a candidate expression memory unit and a similarity weight value calculation unit. The similarity weight values agw(t1, t2) can be calculated for the individual pairs of expressions on the basis of a similarity measure occ_con(t1, t2) which takes into account both the total frequency of the common occurrence of the two expressions of one pair of expressions within one text segment in a quantity of several text segments, and the total number of different context expressions in the quantity of text segments.

Abstract: A method of generating a pseudorandom data sequence, wherein said pseudorandom data sequence is generated by a procedure for searching for a search pattern in an initial data sequence of N bits, said search procedure comprising the following steps: (a) detecting in said initial data sequence a particular search pattern of r bits that is one of a set of search patterns; (b) determining an output pattern of k bits by an operation that depends on the progress of the preceding step; and repeating the preceding steps (a) and (b) successively to form the pseudorandom data sequence from a succession of output patterns.

Abstract: Under block-aware encoding, a bitmap represented by atoms comprises a series of bitmaps for each data block in a database. Each bitmap in the series is referred to herein as a block bitmap. Each block bitmap may have a different number of bytes or bits. Gaps are represented in atoms using a pair of numbers referred to as a gap code. A gap code includes a block-skip code and slot-skip code. A block-skip code represents how many block bitmaps to advance to reach a subsequent block bitmap; a slot-skip code represents how many bytes to advance within the block bitmap to reach a byte with at least one bit set. A gap code is represented by bit positions within a byte, with some bit positions allocated to represent the block-skip code and some to represent the slot-skip code. The allocation is adjusted dynamically during encoding and decoding.

Abstract: A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of coefficient outputs for providing addition signal sequence coefficients. The correlation device comprises further a linking element for the coefficient-wise linking of an addition signal sequence coefficient with a linking coefficient to obtain a correlation result.

Abstract: A carry lookahead adder is employed to determine an equality relationship and one or more inequality relationships between two operands. The carry lookahead adder includes a hierarchy of carry lookahead stages, each carry lookahead stage using either corresponding bits of the two operands or the carry generate values and carry propagate values from the prior stage to generate carry generate values and carry propagate values for use at the next stage. Equality logic receives a subset of the carry generate values and carry propagate values and, based on this subset of values, provides an equality relationship indicator that indicates the equality relationship between the two operands, or portions thereof. Further, inequality logic also receives a subset of the carry generate values and carry propagate values, and based on this subset of values, provides an inequality relationship indicator that indicates an inequality relationship between the two operands, or portions thereof.

Abstract: A system and methods for the creation, management, and distribution of media entity fingerprinting are provided. In connection with a system that convergently merges perceptual and digital signal processing analysis of media entities for purposes of classifying the media entities, various means are provided to a user for automatically processing fingerprints for media entities for distribution to participating users. Techniques for providing efficient calculation and distribution of fingerprints for use in satisfying copyright regulations and in facilitating the association of meta data to media entities are included. In an illustrative implementation, the fingerprints may be generated and stored allowing for persistence of media from experience to experience.

Abstract: Methods and apparatus for finding a match between a target bit pattern and multiple filter bit patterns. A filter array is created from the filter bit patterns and at least one intermediate array is generated from the filter array. Specific columns of the intermediate arrays are then extracted based on bit values of the target bit pattern. A row by row AND operation is performed on these columns to arrive at a match vector. the match vector identifies which of the filter bit patterns in the filter array match the target bit pattern. The method is implemented by using multiple classifier elements operating in parallel with each classifier element handling multiple filter bit patterns.

Abstract: A method and apparatus for triggering data-path conversion utilizing PCM bit robbing signalling. The method and apparatus permits the pass-through of compressed voice packets over a PCM stream between dissimilar interconnected networks or dissimilar payload specifications in the interconnected networks, and also provides the capability to convert the packets to a different payload specification between the networks. Once a voice path is established between the two networks, the incoming PCM data stream is monitored for a voice synchronization pattern which appears periodically in a predetermined bit position in the PCM samples. Upon detection of a matching voice synchronization pattern, a pass-through mode for the voice data between the networks is initiated. A data or payload conversion operation may also be initiated on detection of the matching voice synchronization pattern.

Abstract: A longest common subprefix of two binary words p1 and p2 is identified based on bit strings ip1 and ip2 which are extensions of p1 and p2, and binary words n1 and n2 that define the length of p1 and p2. The bit strings and words are processed to set a “greater” output if p1>p2 and to set an “equal” output if p1=p2. A mask having a consecutive string of most significant bits having a first logical value is constructed to identify the matching subprefixes of p1 and p2.

Abstract: A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.

Abstract: A parallel bit correlator for recognizing a predetermined bit pattern including a predefined number m of bits in a stream of data bits including identifying successive sets of m bits in a stream of data bits and simultaneously comparing each of the sets of m bits to the predetermined bit pattern for detecting the presence of the predetermined bit pattern in the stream of data.

Abstract: A method and apparatus for detecting bits set in a data structure. A first level encoding stage receives bits for the data structure, groups the bits into a set of bit groups, and encodes the set of bit groups to form a set of output bits. A set of intermediate level encoding stages is connected to the first level encoding stage. Each level intermediate encoding stage receives output bits from a previous stage, groups the output bits into a plurality of bit groups, and encodes the plurality of bit groups to generate a plurality of output bits. A final level encoding stage is connected to a last intermediate level encoding stage within the set of intermediate level encoding stages, wherein the final level encoding receives final output bits from a last intermediate level encoding stage within the plurality of intermediate level encoding stages and encodes the final output bits to generate an indication of bits set in the data structure.

Abstract: An adaptive compression technique which is an improvement to Lempel-Ziv (LZ) compression techniques, both as applied for purposes of reducing required storage space and for reducing the transmission time associated with transferring data from point to point. Pre-filled compression dictionaries are utilized to address the problem with prior Lempel-Ziv techniques in which the compression software starts with an empty compression dictionary, whereby little compression is achieved until the dictionary has been filled with sequences common in the data being compressed. In accordance with the invention, the compression dictionary is pre-filled, prior to the beginning of the data compression, with letter sequences, words and/or phrases frequent in the domain from which the data being compressed is drawn. The letter sequences, words, and/or phrases used in the pre-filled compression dictionary may be determined by statistically sampling text data from the same genre of text.