Abstract: A method is for scaling data from a source data to a destination data, wherein a function f(x) is determined to describe the destination data, in which x is a deviation from a current reference point 0. Two source data of f(0) and f(1) with respect to the point 0 and the point 1 are used as reference data. The method is performed by setting an initial condition about a primary slop D=f(1)−f(0), f(0.5)=[f(1)+f(0)]/2, a gain factor G>1, and f′(0.5)=DG=[f(1)−f(0)]G. The f(x) is taken by a quadratic equation of f(x)=ax2+bx+c, which should pass f(0), f(1), f(0.5) and satisfy the slop f f′(0.5). Coefficients of a, b, and, c, are respectively solved in two ranges of 0 x<0.5 and 0.5≦x<1, so as to obtain the function f(x) being about symmetric to the middle point at 0.5. The same procedure is applied for a next source data. Preferably, the function is symmetric to the middle point at (0.5, f(0.5)).

Abstract: A method for an accurate approximation to Slerp function that is much faster to compute on current processors. Specifically, the present invention provides a method for obtaining an interpolated quaternion comprising forming a first product of a first quaternion and a first scaling function; forming a second product of a second quaternion and a second scaling function; and forming a sum of the first product and the second product, wherein the first scaling function is approximated by obtaining a first polynomial and wherein the second scaling function is approximated by obtaining a second polynomial, thus obtaining an interpolated quaternion that is in between the first quaternion and the second quaternion.

Abstract: The present invention provides a method of down scaling a source data to generate a destination data. By using 2 source points on a discontinued curve as reference, each piece of destination data can be generated. A midpoint of these 2 neighbor pixels is generated with a slope defined at the midpoint points. It is easy to control the sharpness of the interpolation result by adjusting the gain factor of the slope. The final interpolation curve passes the midpoint point of the 2 neighbor source points with a slope S define at the midpoint point but does not pass the 2 original neighbor pixels. Although the curve is not continuous at the source reference points but it is seen as a smooth curve by the human eyes during scaling down. The curve is a linear equation which makes the computing storage and cost very low. The BSSC method is excellent in scaling down even compared to other high order equation interpolation curve. Furthermore, a Z transform is induced to minimize the computing complexity.

Abstract: A scaling method is to scale source data to destination data, wherein three reference points of the source data denoted as −1, 0, and 1. Function f(x)=ax2+bx+c are used to describe the destination data within 0 and 1. The method includes setting a midpoint 0.5 with a quantity of f(0.5)=[f(0)+f(1)]/2 and f′(0)=f′(1)=DG, wherein D is a slope of [2f(0)−f(−1)−f(1)], and G is a gain factor to adjust the slope. Curve f(x) passes through the points of 0, 0.5, and 1. The coefficients of a, b, and c for f(x) are solved by a range of 0≦x<0.5 and a range of 0.5≦x<1, so that the f(x) is symmetric or substantially symmetric to the midpoint.

Abstract: A method for scaling a source data to a destination data, wherein two reference points of the source data denoted as 0 and 1 by quantities f(0) and f(1) are used. The quantity f(x) is used to describe the destination data with a range of 0≦x<1, and f(x) is a quadratic form with three coefficients a, b, c for f(x)=ax2+bx+c. The method comprises setting a slope factor D=[f(1)−f(0)] and a gain factor G, wherein a product DG is a slope assigned to a selected one of f′(0) and f′(1), in which G is used to adjust the slope. A constraint is applied on f(x) of quantities of f(0) and f(1) passing through the points of 0 and 1, and satisfying the slope. The coefficients of a, b, and c for f(x) are within the range of 0≦x<1, so that f(x) is used to scale the destination data.

Abstract: A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Abstract: A circuit, for digitizing an analogue signal includes an analogue to digital converter, a clip processor adapted to estimate a value for clipped digital signal samples, and a buffer adapted to dynamically store a plurality of digitized samples produced by the analogue to digital converter. The clip processor is adapted to read digitized samples from the buffer and replace clipped digitized samples with the estimated values, thereby mitigating the effects of clipping in an output of the circuit.

Abstract: A method optimizes function evaluations performed by of a VLIW processor through enhanced parallelism by evaluating the function by table approximation using decomposition into a Taylor series.

Abstract: An apparatus (20) and method (22) for transparently accessing and interpolating data are provided. Consecutive data values (24) of a function are generated and indexed. Even-indexed data values (24) are stored in an even-indexed table (30) and odd-indexed data values (24) are stored in an odd-indexed table (32). Adjacent-indexed data values (24) are acquired substantially simultaneously from even- and odd-indexed tables (30,32) with the first-indexed value (Gn) extracted from the even-indexed table (30) when an integral portion (A[N]) of a memory address (A[N+F]) is even and from the odd-indexed table (32) when the integral portion (A[N]) is odd. A fractional portion (A[F]) of the memory address (A[N+F]) is converted into an incremental value (&Dgr;).

Abstract: A method and apparatus determines interpolated intermediated values of a sampled signal. In order to determine interpolated intermediate values of a sampled signal, such as a digital mobile radio signal, the parameters a, b and c of the second-order polynomial y=ax2+bx+c are determined starting from three known sample values (x1, y1), (x2, y2) and (x3, y3), so that intermediate values can be calculated using the polynomial. Here it is assumed that the signal is sampled at constant intervals, in particular at intervals normalized to d=1, and the center sample value is assigned to the sampling instant x2=0, by which, a calculation can be carried out with low hardware complexity.

Abstract: A digital differential analyzer (DDA) is described that avoids using comparisons, and instead uses shifts, multiplies, and adds. Shifts are less costly to use in terms of processor time, and already exist in the hardware of a computer graphics system. The DDA provides improved linear interpolation procedures for use in computer graphics applications such as line drawing, computing polygon edges, texture mapping, and image scaling. The shifts are used to generate an “imposter” DDA having a larger denominator that substantially exactly simulates a DDA for a finite number of terms. The imposter DDA is a fixed point simulator of the original DDA that provides error-free approximations.

Abstract: A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock signal at a desired phase. The clock phase interpolator circuit includes selectable differential transistor pairs coupled to variable current sources. Different differential transistor pairs are driven by clock signals of different phases provided by the delay locked loop circuit. Two differential transistor pairs are selected, and currents provided to the selected differential transistor pairs are adjusted to provide an output clock of the desired phase.

Abstract: This invention is a method and apparatus for interpolation which enables simpler and cost efficient implementation in hardware or software. A function table stores values of the function at addresses corresponding to the argument points where the function is known. The input value enables identification of the function values for arguments immediately below and above the input value. Respective bits of the absolute value of the difference between these two function values enables corresponding gradient value tables. A set of gradient values are stored in these gradient value tables. The least significant bits of the input value, those bits less significant than the arguments of the stored function values, address entries in the enabled gradient value tables. The desired interpolation value is the sum of the first function value and the gradient value recalled from the gradient tables.

Abstract: Linear interpolators that are both accurate and cost effective to implement in hardware are presented. These interpolators use a multi-bit value approach that permits adders to be used instead of multipliers. The inherent error known in multi-bit value approaches is corrected by using a more accurate approximation for a distance ratio used in interpolation calculations.

Abstract: A method and apparatus determines interpolated intermediated values of a sampled signal. In order to determine interpolated intermediate values of a sampled signal, such as a digital mobile radio signal, the parameters a, b and c of the second-order polynomial y=ax2+bx+c are determined starting from three known sample values (x1, y1), (x2, y2) and (x3, y3), so that intermediate values can be calculated using the polynomial. Here it is assumed that the signal is sampled at constant intervals, in particular at intervals normalized to d=1, and the center sample value is assigned to the sampling instant x2=0, by which, a calculation can be carried out with low hardware complexity.

Abstract: A circuit is provided for performing a high-precision bilinear interpolation operation. The circuit includes a first interpolation operator for interpolating two operands representing a pair of texels using a weight high component of a weighting value. The first interpolation operator outputs a first result. A second interpolation operator interpolates the two operands representing the pair of texels using a weight low component of the weighting value. The second interpolation operator outputs a second result. A combination operator, coupled to the first and second interpolation operators, combines the first and second results to form a value of higher precision than that yielded by typical circuit implementations for bilinear interpolation operation.

Abstract: There is disclosed a resolution conversion apparatus for converting an original digital image into a digital image having a different number of pixels in accordance with an instructed conversion magnification factor. In the apparatus, a determination circuit determines the number of pixels to be interpolated in each block of the original image and positions where they are interpolated in accordance with the conversion magnification factor. The block includes a predetermined number of pixels of the original image. A converted image generation circuit generates pixel data for the interpolation pixels at the positions where they are interpolated in accordance with a predetermined interpolation equation whose coefficients are determined with the positions and data values of the pixels in the block, and combines the pixel data for the digital original image and the generated pixel data to output a converted digital image. The interpolation equation includes spline functions and Bezier functions.

Abstract: A digital sampling instrument for multi-channel interpolatative playback of digital audio data stored in a waveform memory provides improved interpolation of musical sounds by use of a cache memory.

Abstract: A method for conserving memory storage during the execution of a interpolation operation uses a pool of interpolation commands. When a interpolation operation is requested, it is performed using one of the pooled interpolation commands. If none of the pooled interpolation commands are available, the interpolation command having the smallest difference between its interpolated value and final value is selected, and its interpolated value converted to its final value. The selected interpolation command is then reassigned to interpolate the requested data.

Abstract: The present invention discloses a method and a system for performing fast division using non linear interpolation. A storage stores x-axis and y-axis coordinates (X0, Y0) of a plurality of non uniform interpolation points, and x-axis and y-axis coordinates (&Dgr;X, &Dgr;Y) representing the differences between two successive points of the plurality of non uniform interpolation points is used. The plurality of non uniform interpolation points is selected such that the x-axis difference (&Dgr;X) is a power n of 2 in the form of (&Dgr;X=2n), with n being an integer. Upon reception of an input operand X, the storage selects and outputs a set of coordinates (X0, &Dgr;Y, n, Y0) associated to the input operand.

Abstract: A digital data detection system, equipped with an interpolation apparatus, for generating decoded data by detecting information stored on a magnetic storage medium by interpolating sampled data using a phase difference signal and an interpolation coefficient is provided. The digital data detection system includes a magnetic storage medium, an analog signal acquisition circuit, a pre-amplifier, an A/D converter, an interpolation circuit, an equalizer filter, a data decoder, and a phase error detector. The interpolation circuitry includes an accumulation block, a filter coefficient generation block, a HOLD signal generation block, and an interpolator. The interpolation circuitry generates interpolated data using a phase error signal and an interpolation coefficient provided from a MCU (Main Control Unit).

Abstract: A method and apparatus for detecting data written on a recording medium are disclosed. The recording medium, such as an optical or magnetic medium, is initially sensed by a transducer to produce an analog data signal waveform. The analog data signal waveform is then digitized by an analog-to-digital convertor to produce a set of digitized data samples. The set of digitized data samples may be equalized to reduce noise. Subsequently, a mid-point sample is inserted between each two samples within the set of equalized data samples utilizing a mid-point interpolation algorithm. With the additional points provided by mid-point interpolation, the absence or presence of a detection event, such as a peak or a transition, between every two samples within the set of equalized data samples are determined.

Abstract: A digital phase synthesizer includes a source of successive phase data signals. An interpolator generates successive edge placement data signals in response to each of the successive phase data signals. A phase modulator generates an output clock signal having edges placed at times determined by the successive edge placement data signals. Similarly, a digital phase analyzer includes a source of an serial binary input signal having edges. A phase demodulator generates successive data signals representing the location of each edge of the serial binary input signal. A decimator generates phase data signals at a lower rate than the edges of the serial binary input signal.

Abstract: A multi-function look-up table for determining output values for predetermined ranges of a first mathematical function and a second mathematical function. In one embodiment, the multi-function look-up table is a bipartite look-up table including a first plurality of storage locations and a second plurality of storage locations. The first plurality of storage locations store base values for the first and second mathematical functions. Each base value is an output value (for either the first or second function) corresponding to an input region which includes the look-up table input value. The second plurality of storage locations, on the other hand, store difference values for both the first and second mathematical functions. These difference values are used for linear interpolation in conjunction with a corresponding base value in order to generate a look-up table output value.

Abstract: A down-sampling system for digital waveforms performs real-time, “on the fly”, conversions and results in data of acceptable quality for many applications including applications dealing primarily with speech data. The down-sampler comprises a weight matrix calculator and a loop in which the system takes the input data from the producer's data stream, and at one chunk at a time, the system generates the output data. The loop comprises an input receiver, a chunk receiver, an output chunk generator, a chunk decider for deciding whether there is another chunk in the input, and an input decider for deciding whether there is more input.

Abstract: The method and apparatus employ a texture filter in a graphics processor to perform a transform such as, for example, a Fast Fourier Transform. The texturizer can include an array of linear interpolators. The architecture reduces the computational complexity of the transform processes.

Abstract: A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.

Abstract: According to one approach, the present invention is embodied in a computer system and a computer implemented method for interpolating a color value for a pixel that is represented by a pair binary coordinates in a texture map. Each binary coordinate has an integer and a fractional portion. First, the fractional portions of the binary coordinates are multiplied together to generate a first sigma value. A known color value for a first of the four nearest texels is multiplied by the first sigma value to determine the first texel's contribution to the weighted average of the four nearest texels. Next, each bit of the first sigma value is inverted to generate an inverted first sigma value. Then, the fractional portion of one of the binary coordinates is added to the inverted first sigma value to generate a second sigma value. A known color value for a second of the four nearest texels is multiplied by the second sigma value to determine the second texel's contribution to the weighted average.

Abstract: A digital interpolating system transmits a digital output value that is within a linear range defined by a minimum value and a maximum value input into the system. Another input value, a control value, indicates which value within the linear range should be output by the system as an interpolated output value. The system utilizes a simple hardware design to efficiently implement an approximation of an equation of a line defined by the minimum and maximum values input into the system. The hardware design includes a plurality of switching devices, such as multiplexers or switches, and a plurality of adders to implement the approximation of the equation. By approximating the equation, the system is capable of providing the minimum and the maximum value input into the system as the interpolated output value when the control value is at a minimum and a maximum, respectively.

Abstract: An interpolation circuit for calculating the value of an arbitrary point by interpolation using the values of points on the boundaries of a domain which surrounds the arbitrary point comprises a partial product generation circuit composed of multiplexers and a partial product addition circuit for adding partial products generated by the partial product generation circuit together. When an interpolated value f(C) between f(Ci) and f(Ci+1) (where the integer part of C is Ci and the decimal part of C as a binary number of n digits is c=C.sub.n-1 2.sup.n-1 +C.sub.n-2 2.sup.n-2 + . . . +C.sub.1 2.sup.1 +C.sub.0 2.sup.0) is calculated by the interpolation circuit, each multiplexer MPk+1 (k=0, 1, . . . , n-2, n-1) corresponding to 2.sup.k of the decimal part c is supplied with two input values f(Ci) and f(Ci+1) and one selection signal Ck (k=0, 1, . . .

Abstract: A digital sampling instrument for multi-channel interpolatative playback of digital audio data stored in a waveform memory provides improved interpolation of musical sounds by use of a cache memory.

Abstract: Methods and systems consistent with the present invention provide an arithmetic unit, which uses a high speed yet small circuit, using a highly precise method for numerical interpolation that uses Newton-Raphson method.A table for referencing sampling values and operation results is stored successively and alternately in two simultaneously accessible memories 422, 423. A table reference address determining portion 4211 takes the table reference address from the input B. The access control circuit 4212 prepares an address for accessing each memory from the table reference address and reads table values. The interpolation operating portion 4213 interpolates the table value at a precision of half the final precision. The Newton-Raphson operation 4214 performs the Newton-Raphson operation once with the primary interpolated numerical value as the initial value and attains the calculation results with the final precision by precise square convergence.

Abstract: An input phase signal having a presentation range from 0 radian to a value smaller than 2.pi. radian is input to a least significant side shift register 1-1 and to a discontinuity detector 3. The discontinuity detector 3 compares the input phase signal with the same signal delayed by a time corresponding to 1 sample clock in the shift register 1-1, detects a phase discontinuity and outputs 2.pi. radian when the phase transition is 0.fwdarw.2.pi., -2.pi. radian when the phase transition is 2.pi..fwdarw.0 and 0 radian when there is no discontinuity detected. The output of the discontinuity detector 3 is added to outputs of the respective most significant side shift registers 4-1 to 4-n by adders 5-1 to 5-n, respectively. An interpolation circuit 2 performs an interpolation by adding the outputs of the least significant side shift registers 1-1 to 1-n to outputs of the adders 5-1 to 5-n.

Abstract: Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

Abstract: A communication system includes a data sampling rate converter that uses a closed-loop control arrangement to convert an input signal at a first sampling rate to a second, asynchronous, sampling rate without requiring extensive input buffering. A number of data registers in a first-in-first-out input buffer are used to receive and store data samples at the first rate and to pass the data samples from the input buffer at a controlled rate. The input buffer indicates the current capacity of the input buffer circuit for use by a frequency ratio estimation circuit, which is arranged to respond by providing an estimate of the actual ratio between the first rate and the second rate. A control circuit responds to the frequency ratio estimation circuit by generating the controlled rate at which the data samples are to be passed from the input buffer. In this manner, the data samples are passed from the input buffer at the controlled rate for processing and outputting the data at the second rate.

Abstract: A method and apparatus for resizing digital or stored images initially retrieves a one-dimensional sample of the image, such as a line of pixels. A final image size D is determined so that the absolute value of the original sample size M-2.sup.N *D is a minimum, and where N is an integer greater than or equal to 0. The discrete series of pixels in the line are then converted to a continuous function under a cubic convolution interpolation technique. From the continuous function, intermediate pixel values are determined. Pyramid filtering is employed to filter the intermediate pixel values to a final series of pixel values D. The routine is performed along the opposite dimension so as to alter the size of a two-dimensional stored image.

Abstract: An ion implantation process simulation device includes a Dual Pearson data extracting unit for generating a Dual Pearson data table from ion implantation profile data, a Dual Pearson data for interpolation obtaining unit for obtaining a parameter for use in the interpolation and extrapolation of a dose coefficient from the Dual Pearson data table, a dose coefficient interpolating/extrapolating unit for expressing an ion implantation profile by linear connection of two functions respectively representing an amorphous component and a channeling component, as well as using a dose-independent moment parameter and a coefficient of linear connection dependent on dose to interpolate and extrapolate a logarithmic value of a channeling component dose coefficient with respect to logarithmic values of all dose values, and a simulation result outputting unit for outputting a simulation result.

Abstract: An interpolated lookup table circuit includes an input port for receiving an input signal having a first plurality of bits (N bits) including a first portion (Q bits) and a second portion (N-Q bits), a lookup table (LUT) having a plurality of entries wherein each of the plurality of entries has a second plurality of bits including a third portion (V bits) and a fourth portion (D bits), selection means operatively coupled to the input port and responsive to at least the first portion of the input signal which selects one of the plurality of LUT entries based on the first portion of the lookup table input signal.

Abstract: A multiplier array is modified to perform interpolations. The interpolations use a normalized first operand A between 0 and 1. The interpolation is the function B * A+C * (1-A). Standard multipliers accept two operands as inputs, but interpolations require 3 operands (A, B, C). The AND gates in Booth encoders in a standard multiplier array are replaced by multiplexers. Each multiplexer selects a bit from one of the two operands (B or C) based on a bit of the first operand A. The interpolate operation multiplies the first operand A by the second operand B while simultaneously multiplying the bit-wise inverse of the first operand A' by the third operand C. Since one multiply is with the first operand A while the second multiply is with the inverse A' of the first operand, one of the multiplies always generates zero while the other multiply generates either a one or a zero for each bit of the first operand.

Abstract: A sampling frequency converting apparatus according to present invention is such an apparatus in which, when a first digital signal of a sampling frequency Fsi is converted into a second digital signal of an arbitrary sampling frequency Fso by using a digital filter, the ratio between the sampling frequency Fsi and the sampling frequency Fso is obtained and this input/output sampling frequency ratio is utilized as a control amount for the sampling frequency conversion. The sampling frequency converting apparatus includes a buffer memory for temporarily storing the first digital signal, an operating unit for performing an interpolation processing with respect to the input/output sampling frequency ratio at every regular time and a calculating unit which calculates a read address of the buffer memory on the basis of the input/output sampling frequency ratio interpolated by the operating unit.

Abstract: A linear interpolator for determining a weighted average between first and second terms having first and second weights, respectively. The linear interpolator includes a first multiplier for multiplying the first term and an inverse of the second weight to produce a first set of partial products, a second multiplier for multiplying the second term and the second weight to produce a second set of partial products, a carry-save addition ("CSA") tree and an adder. The CSA tree and adder combine the first set of partial products, the second set of partial products, and the first term to produce the weighted average. In another embodiment, the linear interpolator includes a plurality of multiplexers (muxes), the number of muxes being equal to the bit width of the second weight. Each mux selects between the first and second term, depending on whether the corresponding bit of the weight is a zero or one, to produce a plurality of partial products.