Abstract: A method for intra-prediction estimation is provided that includes determining a best intra-prediction mode for a block of samples, wherein at least some of the neighboring samples used for intra-prediction estimation include approximate reconstructed samples, applying approximate reconstruction to the block of samples using the best intra-prediction mode to generate a block of approximate reconstructed samples, and storing the block of approximate reconstructed samples for use in intra-prediction estimation of other blocks of samples.

Abstract: Disclosed is a method of presenting audio information to a user. The method comprising receiving samples of a waveform from a media handling component, initializing a biquad filter with a set of one or more coefficients corresponding to a set of one or more stages of the biquad filter for both a real component of the samples and an imaginary component of the samples. The biquad filter is implemented on a media processing component of the mobile media device. The method further comprises applying the biquad filter to the samples of the waveform to generate an output for presentation to the user, the output comprising a processed rendering of the real component of the samples and the imaginary component of the samples.

Abstract: An abnormal state detection device includes: an acquisition unit that acquires an image imaging a device that outputs an abnormal state using an LED; an analysis unit that analyzes the abnormal state of the device based on the light emission pattern of the LED in the image, and generates auxiliary information indicating the abnormal state based on the analysis result; and a display control unit that outputs the auxiliary information to a display unit.

Abstract: A radio frequency (RF) system may include an RF transceiver, and a baseband engine, application specific integrated circuit (ASIC) coupled to the RF transceiver and configured to perform a given baseband engine operation from among different baseband engine operations. The baseband engine ASIC may include a memory and a state machine coupled thereto and configured to store a respective set of programming instructions for each of the different baseband engine operations and to permit selection of the given set of programming instructions. The baseband engine ASIC may also include a programmable processing circuit coupled to the memory and the state machine and configured to perform butterfly computations responsive to the given set of programming instructions.

Abstract: A transmission sequence generated by a first sector radar is a sequence obtained by multiplying a predetermined code sequence by a first orthogonalized code, and a transmission sequence generated by a second sector radar is a sequence obtained by multiplying a predetermined code sequence by a second orthogonalized code. A value obtained by multiplication of the ith element of the first orthogonalized code and the ith element of the second orthogonalized code is equal to the ith element of a fundamental sequence VV_2n having a length of 2n (n is an integer greater than or equal to 1). The fundamental sequence VV_2n includes a sub fundamental sequence VV_2(n?1) having a length of n and satisfies VV_2n={VV_2(n?1), ?VV_2(n?1)} or {?VV_2(n?1), VV_2(n?1)}.

Abstract: A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words.

Abstract: A transmission signal generator produces N transmission pulses for every transmission period from N (N: an integer of 2 or more) kinds of transmission code sequences and (N×M) (M: an integer of 2 or more) kinds of orthogonal code sequences, the transmission pulses being obtained by multiplying transmission codes of the N kinds of transmission code sequences, with selected N orthogonal codes of the (N×M) kinds of orthogonal code sequences. In one transmission period, a radio transmitter converts the N transmission pulses to high-frequency signals, and transmits the signals through a transmission antenna. The (N×M) kinds of orthogonal code sequences are code sequences which satisfy a predetermined mathematical expression in M transmission periods.

Abstract: A signal is decomposed into different components using a transform, with the components then being separately presented to a person in a manner that produces a different cognitive experience than would have resulted from either (a) presentation of the original signal, or (b) presentation of a fully synthesized (inverse transformed) signal.

Abstract: The invention comprises a method for de-spreading of a data signal spread with a spread spectrum sequence. The invention is especially suited for the improvement of correlations of spread data signals after transmission. Therefor it can be integrated as software or hardware module into existing transmission systems.

Abstract: A radio communication apparatus receives control information on one or more control channel elements (CCEs) with consecutive CCE number(s). The radio communication apparatus first-spreads a response signal with a sequence defined by a cyclic shift value that is determined among a plurality of cyclic shift values from an index of physical uplink control channel (PUCCH), which is associated with a first CCE number of the one or more CCEs, and second-spreads the first-spread response signal with an orthogonal sequence that is determined among a plurality of orthogonal sequences from the index. One of cyclic shift values used for an orthogonal sequence is determined from an index of the PUCCH, which is associated with an odd CCE number, and another one of the cyclic shift values used for the same orthogonal sequence is determined from an index of the PUCCH, which is associated with an even CCE number.

Abstract: Disclosed is a method and system for simultaneously acquiring and producing results for multiple image modes using a common sensor without optical filtering, scanning, or other moving parts. The system and method utilize the Walsh-Hadamard correlation detection process (e.g., functions/matrix) to provide an all-binary structure that permits seamless bridging between analog and digital domains.

Abstract: A wireless communication apparatus capable of minimizing the degradation of the separation characteristic of response signals to be code-multiplexed. In the apparatus, a control part (209) controls both a ZC sequence to be used for the primary spread in a spreading part (214) and a Walsh sequence to be used for the secondary spread in a spreading part (217) according to the associations between sequences and CCEs established in accordance with the probability of using response signal physical-resources corresponding to CCE numbers. The spreading part (214) performs the primary spread of the response signal by use of the ZC sequence established by the control part (209). The spreading part (217) performs the secondary spread of the response signal, to which CP has been added, by use of the Walsh sequence established by the control part (209).

Abstract: A wireless communication apparatus capable of minimizing the degradation of the separation characteristic of response signals to be code-multiplexed. In the apparatus, a control part (209) controls both a ZC sequence to be used for the primary spread in a spreading part (214) and a Walsh sequence to be used for the secondary spread in a spreading part (217) according to the associations between sequences and CCEs established in accordance with the probability of using response signal physical-resources corresponding to CCE numbers. The spreading part (214) performs the primary spread of the response signal by use of the ZC sequence established by the control part (209). The spreading part (217) performs the secondary spread of the response signal, to which CP has been added, by use of the Walsh sequence established by the control part (209).

Abstract: A wireless communications device may include a wireless transmitter, a modulator connected to the wireless transmitter, and a white Gaussian noise generator connected to the modulator. The white Gaussian noise generator may include at least one pseudorandom number generator, and a fast Walsh transform module for generating white Gaussian noise based upon the pseudorandom numbers.

Abstract: An apparatus (A) is dedicated to generating sequences of signal coding elements within a signal transmission device (TD) of a CDMA network.

Abstract: Systems and methods for signal analysis using orbits of a chaotic system are provided. For example, a multiresolution analysis may be constructed and cupolets may be used to approximate arbitrary signals and compress images. Cupolets may be phase transformed to produce compact cupolets that are well-suited for producing sharp changes in signals, or to produce compact cupolets that are more oscillatory and have less or no sharp global maximum amplitudes. Alternatively, cupolets may be phase transformed to allow for optimal or near optimal adjustment to fit a signal.

Abstract: A method for performing parallel digital-to-analog conversion of an n-bit digital input data signal at a frequency of fs including receiving the n-bit digital input data signal; generating M?1 delayed input data signals, M being the number of parallel conversions channels, the M?1 delayed input data signals having respective increasing amount of unit delay, the digital input data signal and the M?1 delayed input data signals forming M digital signals; holding the M digital signals for a first time period; performing a data transformation of the M digital signals using an M×M Hadamard matrix; generating M (n+m)-bit transformed digital data signals; converting each of the M transformed digital data signals to M analog signals; and performing a reverse data transformation of the M analog signals based on the M×M Hadamard matrix to generate an output analog signal indicative of the n-bit digital input data signal.

Abstract: A generator of repetitive sets of spreading sequences comprising element (20), for counting and for forming an address and a table (30) containing L sets of S sequences, wherein the address contains q=1+log2S bits, in which one set among L (L=2q) sets is selected and wherein the log2S bits select one sequence among the S sequences in the set.

Abstract: An orthogonal code generating circuit 10 is arranged by a counter circuit unit 12, a combination circuit unit 14 of orthogonal codes, and a control circuit unit 16. Furthermore, the combination circuit unit 14 is constructed of an AND gate 14a and an exclusive-OR gate 14b. The control circuit unit 16 outputs a decode output in response to a set code designation signal CNo. When a code generation starting signal ST is inputted, a counter circuit 12 starts to output a counter output. Both the decode output and the counter output are entered to the combination circuit unit 14 which AND-gates the corresponding output bits with each other, and thereafter, exclusively OR-gates the AND-gated outputs, and then outputs the exclusively OR-gated signal as serial data of an orthogonal code. As a consequence, since the conventional ROM unit for storing thereinto the orthogonal codes can be omitted, the circuit scale of the orthogonal code generating circuit 10 can be reduced.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N?1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N-1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A system and method for parallel computation of the unordered Hadamard transform. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into M1 sub-vectors xi of length M2, and distributed to the local memories. Each processor computer a Hadamard transform (order M2) on the sub-vectors in its local memory (in parallel), generating M1 result sub-vectors ti of length M2, which compose a vector t of length M1×M2. A stride permutation (stride M2) is performed on t generating vector u. Each processor computes a Hadamard transform (order M1) on the sub-vectors uj in its local memory (in parallel), generating M1 result sub-vectors vj of length M2, which compose a vector v of length M2×M1. A stride permutation is performed on v (stride M1) generating result vector w, which is the Hadamard transform of the input signal x.

Abstract: The present invention is directed to an efficient method and apparatus for channel determination and interference vector construction in accordance with spread spectrum systems. Channel determination is performed using a first series of fast Walsh transform steps. The results of the first set of fast Walsh transform steps corresponding to valid communication system channels are compared to a threshold value. Results derived from the first set of fast Walsh transform steps are then passed through a second set of fast Walsh transform steps with the number of steps performed for a set of results determined by the symbol length associated with the channels from which the amplitude information was derived. The interference vectors thus obtained for each valid symbol length may then be combined to form a composite interference vector. The fast Walsh transform steps and other steps may be performed using shared hardware components or software modules.

Abstract: A fast Hadamard transform device is provided which prevent from increasing of circuit scale and shorten a developing TAT even if the number of bits to be operated. The device includes n of shift register units and n/2 of butterfly computation units. Input data are entered to the shift register units in response to a signal and data stored in the shift register units are supplied as quantized data by providing a signal for each “log2n*(p+log2n)” clocks.

Abstract: A system for generating a Walsh transform output vector from an “N”-component input vector includes a vector store, a plurality of Walsh transform kernels and a control module. The vector store is configured to store the input vector The Walsh transform kernels are configured to generate a Walsh transform of a predetermined radix, with at least two of the Walsh transform kernels generating respective Walsh transforms of different radices A and B, B<A.

Abstract: A system and method for parallel computation of the unordered Hadamard transform. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into M1 sub-vectors xi of length M2, and distributed to the local memories. Each processor computer a Hadamard transform (order M2) on the sub-vectors in its local memory (in parallel), generating M1 result sub-vectors ti of length M2, which compose a vector t of length M1×M2. A stride permutation (stride M2) is performed on t generating vector u. Each processor computes a Hadamard transform (order M1) on the sub-vectors uj in its local memory (in parallel), generating M1 result sub-vectors vj of length M2, which compose a vector v of length M2×M1. A stride permutation is performed on v (stride M1) generating result vector w, which is the Hadamard transform of the input signal x.

Abstract: A Fast Hadamard Transform apparatus having a plurality of transform stages, such as would be employed by a wireless telecommunication system for detecting and correcting errors that occur during the transmission of coded signal blocks, such as a Walsh codeword. Each stage of the apparatus comprises an adder and a subtractor, each having an output terminal. The adder and the subtractor are configured to receive signal pairs and generate intermediate coefficients. A first memory unit is coupled to the output terminal of the adder and to the output terminal of the subtractor, and is configured to receive a first specifiable sequence of the intermediate coefficients from the adder and a second specifiable sequence of the intermediate coefficients from the subtractor. A second memory unit is coupled to the output terminal of the subtractor so as to receive a third specifiable sequence of the intermediate coefficients from the subtractor.

Abstract: A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides sufficient transition density.

Abstract: A pipelined Fast Hadamard Transform ("FHT") architecture is disclosed that comprises log.sub.2 N identical pipeline stages, which are ideally suited for implementation in application-specific integrated circuits. One 2-port stage of the first illustrative embodiment of the present invention advantageously comprises: a first input for sequentially receiving N incoming correlation signals, I(i), at cycle i, wherein the N incoming correlation signals are based on N Walsh chips; a processor for generating N outgoing correlation signals based on the N incoming correlation signals, I(i); and a first output for sequentially outputting the N outgoing correlation signals, O(i); wherein ##EQU1## k=(i-N/2).

Abstract: A constant matrix [TS] is resolved into three constant matrices [TSC], [TSB], [TSA]. 1st.about.16th rows of the constant matrix [TSC] are calculated by a first stage of additions/subtractions (adders/subtractors 1.sub.1 .about.1.sub.16) to which elements A1.about.A16 are inputted. 1st.about.16th rows of the constant matrix [TSB] are calculated by a second stage of additions/subtractions (adders/subtractors 2.sub.1 .about.2.sub.16) to which outputs from the first stage of additions/subtractions are inputted in a predetermined pattern as shown. 1st.about.16th rows of the constant matrix [TSA] are calculated by a third stage of additions/subtractions (adders/subtractors 3.sub.1 .about.3.sub.16) to which outputs from the second stage of additions/subtractions are inputted in a predetermined pattern as shown. As a result, 1st.about.16th rows of the constant matrix [TS] are calculated by the first through third stages of additions/subtractions, outputting elements B1.about.B16.