Abstract: To compute a signature for an object comprising or represented by a set of vectors in a vector space of dimensionality D, statistics are computed that are indicative of distribution of the vectors of the set of vectors amongst a set of regions Ri, i=1, . . . , N of the vector space, at least some statistics associated with each region are binarized to generate sets of binary values ai, i=1, . . . , N indicative of statistics of the vectors of the set of vectors belonging to the respective regions Ri, i=1, . . . , N; and a vector set signature is defined for the set of vectors including the sets of binary values ai, i=1, . . . , N. The computing, binarizing, and defining operations may be repeated for two sets of vectors, and a quantitative comparison of the two sets of vectors determined based on the corresponding vector set signatures.

Abstract: A communication device including a receiving unit and a signal processing module having a simulation unit and a decision unit is provided. The receiving unit receives a first burst of a paging message provided from a base station. Base on a reference burst code and an estimated channel impulse response of the communication channel, the simulation unit generates a simulation burst. The decision unit then determines if the paging message is a dummy message in accordance with the first burst and the simulation burst. The decision unit requests the receiving unit to stop receiving the paging message once the paging message is determined to be a dummy message.

Abstract: An apparatus and method for signal detection in which a digital sample stream is fed round robin into a plurality of buffers, which are sequentially compared with a reference signal to determine a match. A processor determines the chronological order of the samples in each bit of each buffer, and directs a bitwise comparison between the signal in each buffer with the reference to determine a match, e.g., by correlation. The apparatus and method are preferably implemented with a Field-Programmable Gate Array (FPGA). This scheme permits real time correlation of a data stream with a reference without use of shift registers, or a significant number of dedicated logic blocks.

Abstract: A novel architecture is described for applying a sum and threshold function to a weightless input string and a weightless threshold string. The sum and threshold function is carried out by distributing the input bits in random manner (12) between a number of sum and threshold devices (14), whose outputs are supplied to a second layer of one or more sum and threshold devices (16).

Abstract: A correlator is disclosed and includes a data bus for receiving blocks of n bit parallel in phase (I) and n bit parallel quadrature (Q) signal data and n bit parallel I and Q reference data from respective I and Q signal channels and I and Q reference channels. The I and Q reference data are correlated with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce an I component signal output and Q component signal output along each of the individual n parallel paths. An output bus receives I and Q component signal outputs from the n parallel paths one at a time at one bit input time periods such that there is one correlation product output for every I and Q parallel n bits. A cascade adder circuit comprises at least one adder connected to the output bus and receives the I and Q component signal outputs from the output bus and delayed I and Q component signal outputs from another correlator.

Abstract: An enhanced digital signal processor (EDSP) includes execution section that includes the following constituents: a processor, an arithmetic logic unit (ALU), a memory device for holding set of instructions for execution selected from enhanced set of instructions, a memory device for holding data, another clock generator for generating a plurality of clock signals coupled to above constituents. Internal communication bus coupled to the above constituents for affording controlled communication between them, a correlator, coupled to the bus, for communication with the execution section. The correlator having an input port for receiving external input data and an output port for outputting data.

Abstract: The details of an improved correlator and efficient method of correlation are disclosed. The last M received signal samples are compared with all shifts of a given M-bit binary codeword. The correlator adds or subtracts each of the signal samples accordingly, as the corresponding shift of the codeword contains a binary "1" or "0" in that position. The total is output for each new signal sample received, with a shift of one position between the signal samples and the codeword.