Abstract: Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.

Abstract: In certain embodiments, a device includes a first filter. The first filter is operable to produce at least one correlation result by at least correlating an input signal sequence with a link sequence. The first filter includes a delay element. The device also includes a second filter sharing the delay element of the first filter.

Abstract: In order to attain an optimally compressed, narrow pulse peak at the filter output of a correlation filter for the purpose of reception, the interfering secondary maxima of the autocorrelation function of binary codes must be as small as possible. The invention uses specially designed signal codes which are used to generate the associated complementary signal code from the received sequence by means of evaluation in the reception filter. The subsequent parallel formation of the autocorrelation functions of the received signal code and the complementary signal code exhibits secondary maxima having an opposite mathematical sign, thus resulting in the desired prefect pulse peak having secondary maxima which are equal to zero during summation at the filter output.

Abstract: A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of coefficient outputs for providing addition signal sequence coefficients. The correlation device comprises further a linking element for the coefficient-wise linking of an addition signal sequence coefficient with a linking coefficient to obtain a correlation result.

Abstract: A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of coefficient outputs for providing addition signal sequence coefficients. The correlation device comprises further a linking element for the coefficient-wise linking of an addition signal sequence coefficient with a linking coefficient to obtain a correlation result.

Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. Substantially the same hardware can be utilized for processing in-phase and quadrature phase components of the data word (X0-XM-1). The coefficients (C0-CM-1) can represent real numbers and/or complex numbers. The coefficients (C0-CM-1) can be represented with a single bit or with multiple bits (e.g., magnitude). The coefficients (C0-CM-1) represent, for example, a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.

Abstract: A parallel correlator and method includes temporarily storing in a series of P sequence registers, each of length R1, serial bit-sequences of a code of length N=P*R1. In a first-level of processing, certain unique bit sequences are inverted to reduce the number of unique bit sequences by half. Identical bit-sequences are then combined and temporarily stored in a first-level sub-accumulation register. Alternatively, bit sequences differing by only one bit may be combined in a common first-level sub-accumulation register. Further levels of similar processing may be imposed, where each subsequent level taps and inverts only a portion of the bits in the above level of processing, thereby reducing the number of unique bit sequences. Finally, all negative energy is combined in one register position, inverted, and added to all positive energy in the other register positions.

Abstract: A correlation device is provided that includes an adder for adding an input signal sequence and an auxiliary signal sequence to obtain an addition signal sequence, and a delay element for delaying the addition signal sequence to obtain the auxiliary signal sequence, whereby the delay element has a plurality of coefficient outputs for providing addition signal sequence coefficients. The correlation device comprises further a linking element for the coefficient-wise linking of an addition signal sequence coefficient with a linking coefficient to obtain a correlation result.

Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM?1) with encoding coefficients (C0-CM?1), wherein each of (X0-XM?1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. X0 is multiplied by each state (C0(0) through C0(k?1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k?1). This is repeated for data bits (X1-XM?1) and corresponding coefficients (C1-CM?1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated until a final layer of results is generated.

Abstract: In accordance with the invention, in a nonrecursive digital filter, the number of times each bit of input data passes through a shift register is reduced to save power. Despreading data is sent to a first shift register and a second shift register, each having a number of stages obtained by dividing the usual number of stages by two, and both shift registers alternately perform a shift operation at both edges of a shift clock. Multiplexers are provided for selecting the odd-numbered codes of reference codes stored in a reference-code register when the shift clock is in an OFF state and for selecting the even-numbered codes when the shift clock is in an ON state, and multiplexers are provided that perform the selections analogous to the above.

Abstract: A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k-1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k-1). This is repeating for data bits (X1-XM-1) and corresponding coefficients (C1-CM-1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated.

Abstract: An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes. A data shift register receives input data and loads the input data. A reference shift register receives reference data and loads and circulates the reference data. A pulse correlator connected to the shift register and the reference shift register correlates the input data with the corresponding reference data and provides a pulse correlator output. An accumulator connected to the pulse correlator receives and adds the pulse correlator outputs from the correlation processes to produce a correlator output corresponding to the predetermined number of correlation processes.

Abstract: Once slot synchronization has been obtained in a first step, during a second step there is acquired, by means of correlation of the received signal (r) with the synchronization codes, the information corresponding to the codegroup and to the fine slot synchronization. The synchronization codes are split into codesets. In a first step, a synchronization code identifying a corresponding codeset (CS) is identified by means of correlation and search for the maximum value of correlation energy. In a second step, the received signal (r) is correlated with the remaining codes belonging to the codeset identified. The information thus obtained, which corresponds to all the synchronization codes comprised in the codeset identified, is used for obtaining frame synchronization and codegroup identification. Preferential application is in mobile communication systems based upon standards, such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract: A signal processing apparatus and method and a provision medium arranged to enable detection of a unique pattern in a short time with high accuracy. A value representing a correlation between an input signal and a reference signal is calculated and the calculated correlation value is compared with a predetermined threshold value. The invention makes it possible to detect, for example, a unique word in a short time with high accuracy without influence of noise.