Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.

Abstract: This arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in parallel sums of and/or differences between a plurality of input variables or sums of and/or differences between a plurality of values obtained by multiplying said plurality of input variables by a constant. The arithmetic unit also includes a processing unit having a plurality of shift units for shifting outputs from said plurality of first units by respectively predetermined numbers of digit-shifts and a plurality of second units for calculating concurrently sums of outputs from said plurality of shift units. The arithmetic can be used, for example, as a high speed discrete cosine unit, a high speed Hartley transform unit or a high speed Hough transform unit.

Abstract: The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of the present invention will set an H indicator for a given dit n if the sum of An and Bn is less than or equal to two, will set a P indicator if the sum is three, and will set a G indicator if the sum is greater than three.

Abstract: The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.

Abstract: The present invention uses N-nary logic to perform addition or subtraction, along with carry propagate logic, within one gate. The gate produces as outputs a 1-of-4 result value and a 1-of-3 HPG indicator. The preferred embodiment of the present invention implements subtraction using three's complement addition. In an alternative embodiment, four's complement addition is implemented to achieve the subtract function and the HPG indicator is a 1-of-2 signal that combines the H(alt) and P(rop) indications.

Abstract: The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.

Abstract: Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunneling devices can achieve increased speed and density over binary circuits and multiple-valued circuits implemented in conventional IC technologies since multiple binary bits are very efficiently processed by architectures which make use of devices with multiple negative transconductance regions.

Abstract: A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.

Abstract: A memory, which consumes less electric power and has a longer life, stores a redundant binary code produced by replacing each digit of data in binary representation, with a separate 2-bit string allocated to a value which the digit can take. If a value to be output before or after a value is output from the memory is known, a redundant binary representation and a redundant binary code associated therewith are determined such that the number of transitions can be reduced. Thus, a memory which consumes less electric power and has a longer life can be provided.

Abstract: An arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in parallel sums of and/or differences between a plurality of input variables or sums of and/or differences between a plurality of values obtained by multiplying said plurality of input variables by a constant. The arithmetic unit also includes a processing unit having a plurality of shift units for shifting outputs from said plurality of first units by respectively predetermined numbers of digit-shifts and a plurality of second units for calculating concurrently sums of outputs from said plurality of shift units. The arithmetic can be used, for example as a high speed discrete cosine unit, a high speed Hartley transform unit or a high speed Hough transform unit.

Abstract: A divider which multiplies both divisor and dividend by a first multiplier generated from the divisor to compute an intermediate divisor and an intermediate quotient, and iterates such computations by the number of times needed, so that the intermediate divisor approaches a predetermined value, and the intermediate quotient approaches the quotient obtained by dividing the dividend by the divisor. This makes it possible to implement a fast divider with a configuration simpler than that of a conventional divider which feeds back the outputs of multipliers many times depending on the accuracy required, which involves delay times in the multiplication and makes the configuration complicated.