Abstract: An apparatus and method are described for comparing elements between two immediate values. For example, a method according to one embodiment includes the following operations: reading values of a first set of elements stored in a first immediate value, each element having a defined element position in the first immediate value; comparing each element from the first set of elements with each of a second set of elements stored in a second immediate value; counting the number of times the value of each element of the first set of elements is found in the second set of elements to arrive at a final count for each element of the first set of elements; and transferring the final count for each element to a third immediate value, wherein the final count is stored in an element position in the third immediate value corresponding to the defined element position in the first immediate value.

Abstract: A numeric value display method uses a display processing section. When an operation to read out a numeric value from storage means and display it is executed, if the numeric value has a greater number of digits than the number of digits which can be displayed on a numeric value display device, the display processing section divides the numeric value into a predetermined number of digits and displays a part of the numeric value on the numeric value display device in such a manner that it is possible to know which part of the numeric value is displayed. Moreover, each time operation keys are pressed, the display processing section resets a display diction variable (P) required for controlling the display position for each of the divided parts of digits preset and switches the part of the numeric value to be output to the numeric value display device.

Abstract: A fast incrementer using zero detection and an increment method thereof. The incrementer performs a logic combination on an operand, first logic state inclusion information for each b-bit group of the operand, flag information for each b-bit group of the operand, and an increment value, and outputs a whole increment value for the operand.

Abstract: A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding output string. A least significant bit of the auxiliary string is independent from the bits of the first string, and any other bit of the auxiliary string. The method is particularly convenient for generating an overflow flag when the number to be output exceeds the representation interval. An overflow flag is generated by logically combining the most significant bits of the first and auxiliary strings.

Abstract: An IC may be provided with an efficient programmable counter that affords speed, modest size, low power consumption and easy programmability, by cascading a number of PRBS counters modified to include the all-zeroes state, so that they have a full 2n different states for n-many flip-flops in the counter. For example, a forty-bit counter can be formed by cascading five eight-bit PRBS counters that have each been modified to have 28=256 different states. The result is a fast forty-bit counter that is of modest power consumption and nearly minimal device count, and yet is nearly as easy to program as a standard binary counter.

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation.