Abstract: The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.

Abstract: An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder 470 connected to the partial production reduction tree. Unbiased rounding logic 476 is provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signal 477 which is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero.

Abstract: An Hadamard transform coding circuit changes a rounding method for each Hadamard transform block to prevent a rounding operation from providing an error biased in one direction, as seen in a picture in its entirety, for data compression and rounding. More specifically, after Hadamard transform there exist decimal parts 0.0, 0.25, 0.5 and 0.75, and if a numerical value is simply rounded off a probability would be increased that the numerical value is biased to increase in absolute value. Accordingly for 0.5 a rounding operation to provide an integer switches for each block. Thus a motion image decoding apparatus can be provided to reduce error accumulation and suppress flickering, color variation and other similar noticeable degradations.

Abstract: An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction portion of the binary floating-point number; and replacing each bit of the fraction portion with the sign bit, thereby producing a floor of the binary floating-point number.

Abstract: Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each floating-point operation, the operand processing section receives and processes one or more input operands to provide a preliminary result. The operand flush section determines whether the preliminary result falls within one of a number of ranges of values and sets the preliminary result to one of a number of set values if the preliminary result falls within one of the ranges. In a specific implementation, a first range of values is defined to include values greater than zero and less than half of a minimum normalized number (i.e., 0<|y|<+amin/2), a second range of values is defined to include values equal to or greater than +amin/2 and less than +an, (i.e.

Abstract: A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.

Abstract: A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The first and second data operands are mathematically related, making this re-encoding process possible. A device, for example, a shifter, bus network, multiplexer, or buffer, processes the first and second data separately, successively in time, and in a self-timed manner, and communicates the processed first and second data onto a fourth set of logic paths. A decoder receives the processed first and second data in succession from the device on the fourth set of logic paths. The decoder decodes the first and second data onto separate respective fifth and sixth sets of logic paths, which have an encoding that corresponds to the original first and second sets of logic paths.

Abstract: Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.

Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

Abstract: A round off mechanism maintains a mean value of the operand while rounding twos complement binary data. Positive data values are incremented at the first discard bit prior to truncation of the discard bits, as are negative data values having a one within the most significant discard bit and at least one other discard bit. The discard bits are simply truncated for all other negative data values.

Abstract: Various methods for performing rounding operations in a computer processor are described. A machine instruction sets the rounding mode, which is automatically applied to subsequent machine instructions. Using machine instructions to round results according to the selected rounding mode has several advantages over software-implemented rounding techniques, such as faster execution and concise code. A variety of rounding modes can be specified. Depending in part on the specified rounding mode and on the sign of the value to be rounded, a rounding term is added to the value to be rounded. Adding this rounding term ensures that the desired result is obtained. The value thus obtained is then right-shifted.

Abstract: A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position.

Abstract: A stream cipher cryptosystem includes a pseudo-random bit generator receiving a key and providing a vulnerable keystream vulnerable to crytanalysis, and a non-linear filter cryptographic isolator to convert the vulnerable keystream into a protected keystream. The non-linear filter cryptographic isolator includes a multiplier for performing a multiplication function on the vulnerable keystream to provide a lower partial product array and an upper partial product array, and a simple unbiased operation (SUO) for combining the lower partial product array and the upper partial product array to provide the protected keystream. In example encryption operations, a plaintext binary data sequence is combined with the protected keystream to provide a ciphertext binary data sequence. In example decryption operations, a ciphertext binary data sequence is combined with the protected keystream to provide a plaintext binary data sequence.

Abstract: A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discriminant. If a critical pattern is found in the discriminant, this indicates that standard rounding may give an incorrect result and further calculation is needed. The method can work for various rounding modes and types of floating point representations. The method can be implemented in a system as part of a processor instruction set or any combination of hardware, microcode, and software.

Abstract: A method for extending the data width of a graphics processing channel in a computer graphics system. The method includes the first step of providing a plurality of graphics processing channels having pre-defined output data widths or capacities. The next step is combining at least a portion of an output from at least two of the plurality of graphics processing channels. Another step is defining at least one extended graphics processing channel with an extended data width. The extended graphics processing channel is formed with output portions from the plurality of graphics processing channels.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

Abstract: Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectable bias, a reduced precision signal, having minimized or eliminated rounding error, is generated. The selectable bias corresponds to a predetermined characteristic of one of bias, an error signal, the input datum, the reduced precision datum, and a combination thereof.

Abstract: During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.

Abstract: One embodiment of the present invention provides a system for compiling computer code to perform a subtraction operation between a first interval and a third interval to produce a resulting interval. The system operates by receiving source code within a compiler. The system next determines if a subtraction operation within the source code is a dependent subtraction operation, wherein the third interval is the sum of the first interval and a second interval. If so, the system produces executable code for the subtraction operation that computes a left endpoint for the resulting interval and a right endpoint for the resulting interval. If the left endpoint of the third interval is negative infinity, the left endpoint of the resulting interval is assigned to be negative infinity.

Abstract: A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital circuit to significantly increase speed. Generally, an unincremented result and an incremented result are produced in parallel and then either one is selected as a rounded result based upon specified rounding criteria, thereby eliminating the time consuming need for an incrementor to perform rounding at or near the end of the FP fused multiply adder.

Abstract: A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the remaining significand by the calculated exponent difference, a first bit inverter, an adder, a leading-zero anticipation circuit for anticipating the consecutiveness of leading zeros from the significands, a leading-zero counter for counting the anticipated number of leading zeros, a left shifter for shifting an output value from the adder, a second bit inverter for taking two's complement of an output value from the left shifter, an incrementer for incrementing an output value from the second bit inverter by one, a compensation shifter for shifting an output value from the incrementer, an exponent subtracter for subtracting the number counted by the leading-zero counter from the larger exponent, and a decrementer for decrementing an output exponent from the exponent subtracter by one.

Abstract: A method and apparatus for finding the hard-to-round double precision operands x when processed by a function f(x)and using these hard-to-round numbers to optimize f(x) hardware and software f(x) algorithms to ensure proper rounding begins by segmenting all proper x operands into analysis domains (FIG. 8). The analysis domains are split into sub-domains (1202-1208) where a linear generator is used to generate candidate hard-to-find values for each sub-domain (1210). A quadratic filter is used to reduce the list of candidates to a final list of hard-to-round values for f(x) (1212). The hard-to-round double precision values are used to set a precision of hardware or software f(x) algorithm to ensure proper rounding or all valid x operations while simultaneously ensuring that too much precision, and therefore, reduced performance, is avoided.

Abstract: A processor representation of a floating-point data item is converted to a representation of a truncated integer item, without changing the rounding mode of a processor. When the current rounding mode is unknown, the floating-point item is converted to an integer representation in whatever mode the processor happens to be in. One of multiple correction values is applied, in response to the sign of the original data, a difference between the integer and the original data, and whether the item is an integer. When the current rounding mode is known, the processor produces two integer representations, and selects one or the other of them as an output integer data item, in response to the sign of the original item and the relative sizes of the two representations.

Abstract: A floating point calculation method according to the present invention includes steps of: receiving input data; performing calculation for data for an exponent portion of the input data for outputting a calculation result; branching into cases in accordance with the calculation result for setting a value of each bit of output data in accordance with a combination of a designation signal designating by which one of rounding up and rounding down the integer representation is to be performed and a sign bit of the input data; and outputting the output data.

Abstract: A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

Abstract: There is disclosed a method and apparatus for rounding numerals according to the number of significant digits or a rounding interval. The method starts with entering a numerical value x to be rounded and the number of significant digits n or a rounding interval w. The entered numerical value x is stored in a first storage portion of the apparatus. The entered number of significant digits n or rounding interval w is stored in a second storage memory. The numerical value x stored in. the first storage portion is rounded in a digit place determined by the number of significant digits n or rounding interval w stored in the. second storage portion. The numerical value x is rounded while using the number of significant digits n or rounding interval w as it is.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: A method comprising identifying a sample rate of received audio content, receiving a conversion sample rate, and converting the received audio content to the received conversion sample rate. Wherein the conversion comprises utilizing a repeating sequence of packets where all but one of the packets of each sequence are truncated to a whole number of samples, while the remaining packet is rounded up to the next whole number of samples if the conversion fails to resolve packet size to a whole number.

Abstract: A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the result D is a canonical-form extended-precision floating point number having a high order component and a low order component. The processor is a fused multiply-add processor with a multiplier, an adder, a normalizer and a rounder. The post-adder data path, the normalizer and the rounder each have a data width sufficient to represent post-adder intermediate results to permit the high and low order words of a correctly-rounded result D to be computed. The mantissas of the extended-precision result D are provided such that the high order word mantissa is stored to double precision registers.

Abstract: An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two.

Abstract: In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and division operations. A bit sequence that represents a directed boundary condition for a mathematical operation is identified. This sequence is then recast in terms of a series of integer equations. A recurrence is used to solve these equations to produce difficult test data. When solving the equations, any intermediate terms that exceed the computer's precision are discarded. The logic then conducts the mathematical operation under inspection using the test cases. The logic's computed value is then compared to an expected value. If the computed value equals the expected value, the logic has accurately performed the operation. If not, the logic is faulty.

Abstract: The present invention provides a system and method to efficiently round real numbers. The system includes a rounding apparatus to accept an input value that is a real number represented in floating-point format, and to perform a rounding operation on the input value to generate an output value that is an integer represented in floating-point format. The system also includes a memory to store a computer program that utilizes the rounding apparatus. The system further includes a central processing unit (CPU) to execute the computer program. The CPU is cooperatively connected to the rounding apparatus and the memory.

Abstract: An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point processor includes an AND circuit, a selection circuit, and a multiplexor. The AND circuit generates an AND signal and its complement from a normalized mantissa. The selection circuit generates a select_AND signal and its complement from the normalized mantissa. The multiplexor, which is coupled to the AND circuit and the selection circuit, chooses either the AND signal or its complement signal as a rounded normalized mantissa according to the select_AND signal and its complement signal from the selection circuit.

Abstract: In a chain of linear time-invariant operations (401), all bias introduced between operations collectively produce a total deterministic error at the final output of the chain of operations (401). In the present invention, truncation is used in place of rounding after each operation by simply not rounding in software. Recognizing that all the bias introduced by replacing rounding with truncation results in a single deterministic error at the final output, in the present invention the total bias (403) is predetermined and subtracted from each data sample of the final output sequence.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

Abstract: A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles. The address generator of the processor, includes circuitry which concatenates the most significant bits of a base address of a table to the least significant bits of an index, to thereby rapidly generate addresses of indexed locations in a table.

Abstract: A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both a low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low rounding bit increment result. In this manner, the present rounding adder circuit eliminates the need to perform a no increment calculation used to select a result, as in the prior art.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computatoin will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computatoin will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.

Abstract: An object is to obtain a floating-point arithmetic unit with improved throughput. The floating-point arithmetic unit comprises a mantissa adder-subtracter portion (MAP) for performing arithmetic operation of mantissa data (A, B) in floating-point data, an increment portion (INP) for performing increment to a bit in the arithmetic result (D) which corresponds to the LSB when it is assumed that the MSB in the arithmetic result (D) is not shifted, a round-off decision portion (RJP) for deciding whether to round up the bit one place lower than the LSB, and a selector (S1) for selectively outputting the arithmetic result from the increment portion (INP) or the arithmetic result (D) from the mantissa adder-subtracter portion (MAP).

Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Abstract: A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles. The address generator of the processor, includes circuitry which concatenates the most significant bits of a base address of a table to the least significant bits of an index, to thereby rapidly generate addresses of indexed locations in a table.

Abstract: A floating point unit is provided which conveys the rounding mode in effect upon dispatch of a particular instruction with that particular instruction into the execution pipeline of the floating point unit. Upon dispatch of a control word update instruction into the execution pipeline, the rounding mode is updated according to the updated control word provided for the control word update instruction. Instructions subsequent to the control word update instruction thereby receive the updated rounding mode as those instructions are dispatched. The updated rounding mode is available to the subsequent instructions prior to retiring the control word update instruction. The rounding mode is therefore updated without serializing the update. If the control word update instruction modifies the value in a field other than the rounding mode, the instructions subsequent to the control word update instruction may be discarded and re-executed subsequent to updating the control word register with the updated control word.

Abstract: The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed operand is denormalized and providing characteristic bits. A rounding bit is generated based on the characteristic bits. The rounding bit is merged with the denormalized operand to generate the rounded result operand.

Abstract: A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate.

Abstract: A floating point unit includes a rounding unit that rounds the two least significant bits of a sum. After a sum of the two mantissas is generated the at least one least significant bit is separated from the sum. When addition is performed, two least significant bits are separated from the sum. A half add unit may be used to generate the sum along with a set of carry data, and thus at least one least significant bit of the carry data is also separated. A rounding unit receives the separated at least one least significant bit of the sum and carry data and produces a carry in bit as well as rounded at least one least significant bit. The sum and carry data are then summed in a later stage of the floating point unit to form both a unincremented sum and an incremented sum, which are stored in a multiplexer. The carry in bit is used to select one of the unincremented sum and incremented sum.

Abstract: The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for shifting of the intermediate result prior to normalization or rounding. The exponent is pre-incremented prior to normalization. During normalization, the most significant bit of the intermediate fraction is shifted into the carry bit and the exponent is decremented accordingly. Selection logic then selects one of six possible formatting procedures to generate a mathematically correct output fraction in proper ANSI/IEEE 754-1985 floating point format, and formatting logic generates the output fraction according to the selected formatting procedure.

Abstract: The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is pre-incremented by one prior to normalization. During normalizaion, the most significant binary “1” of the fraction is shifted left until it resides in the carry bit. For each left shift performed, the incremented exponent is decremented once.