Abstract: A method for computing the alignment sticky bit in floating-point operations is provided. The method includes computing a pre-computed sticky bit. A significand is aligned based on an alignment counter. A shifter sticky OR is computed. The alignment sticky bit is computed based on the pre-computed sticky bit by ORing the pre-computed sticky bit and the shifter sticky OR when the alignment counter comprises a value greater than or equal to a predefined value.

Abstract: Floating point adder circuitry 16, 18, 20 is provided with far-path circuitry 18 and near-path circuitry 20. The far-path circuitry utilises a count of trailing zeros TZ and a difference in the input operand exponents to form respective suffix values which are concatenated with the mantissas of the input addends and serve when summed to generate a carry out taking the place of a conventionally calculated sticky bit. Within the near-path, minimum value circuitry 46 is used to calculate the lower of a leading zeros count of the intermediate mantissa produced in a subtraction and the larger of the input operand exponent values such that a left shift applied to the intermediate mantissa value is not able to produce a invalid floating point result due to applying a left shift to remove leading zeros that is too larger and accordingly corresponds to an exponent which cannot be validly represented.

Abstract: The three-term input floating-point adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent with a width of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, a carry save adder (CSA) which reduces the mantissas from the pre-processing circuit from three terms to two terms, a carry look-ahead adder (CLA) which carries out addition on the mantissas of the two terms, a normalization circuit which makes a left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which output

Abstract: A method for computing the alignment sticky bit in floating-point operations is provided. The method includes computing a pre-computed sticky bit. A significand is aligned based on an alignment counter. A shifter sticky OR is computed. The alignment sticky bit is computed based on the pre-computed sticky bit by ORing the pre-computed sticky bit and the shifter sticky OR when the alignment counter comprises a value greater than or equal to a predefined value.

Abstract: A sticky bit value of the product of mantissas X and Y is predicted by a circuit that comprises a bit pattern generation circuit 25A that generates a bit pattern B, based on a trailing zero bit pattern of the multiplier Y, having all values of the sticky bit S corresponding to any number C of the trailing 0s of the multiplicand X; a priority encoder 21 for providing the number C depending on X; and a sticky bit selection circuit 26A for selecting one bit in the bit pattern B as a value of the sticky bit S depending on the value C.

Abstract: For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.

Abstract: In a shift and shift-out detecting circuit, a plurality of partial shift circuits respectively have bit shift quantities which are different from each other, and are connected in series. Each of the plurality of partial shift circuits receives a shift result as a previous shift result from the partial shift circuit of a previous stage and a corresponding shift instruction, shifts the previous shift result by the corresponding bit shift quantity in response to the shift instruction to produce a current shift result, and outputs the current shift result to the partial shift circuit of a subsequent stage. A plurality of shift-out detecting circuits are respectively provided for the plurality of partial shift circuits. Each of the plurality of shift-out detecting circuits detects a shift-out of “1” bit from the current shift result and the corresponding shift instruction and generates a partial sticky signal when the shift-out is detected.

Abstract: A method for generating the sticky-bit includes encoding the first operand to represent the number of trailing zeros in the first operand. Then the second operand is encoded to represent the number of trailing zeros in the second operand. The encoded values are then added together to form a sum representing the number of trailing zeros in the multiplication result. The sum total number of trailing zeros is then compared to a predetermined constant. The constant is equal to the number of bits used in determining the sticky-bit. If the sum is larger than the constant, then the sticky-bit is given a value of zero and, conversely, if the sum is smaller than the constant, the sticky-bit is given a value of one.

Abstract: In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed, the setting of the truncation indicator is inhibited under certain conditions to facilitate later handling of the result. Determinations are made as to whether the result and truncation fields of the result word are zero and as to whether the overflow field is non-zero. If the result and truncation fields are zero, the setting of the truncation indicator is inhibited notwithstanding a non-zero value in the overflow field. Break point position information is processed to obtain masks of bits having logic "1" values for testing the result and truncation fields and logic "0" values for testing the overflow field, the masks then being logically ANDed with the result word. If the result of the ANDing process is a logic "0", the truncation indicator is inhibited from being set.

Abstract: Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit.

Abstract: A circuit for generating the sticky-bit includes a first encoder, a second encoder and an adder circuit. The first and second encoders respectively provide encoded values representing the number of trailing zeros in the first and second operands of the multiplication operation. The adder receives the encoded values from the encoders and a constant. The constant represents the number of bits used in determining the sticky-bit. The adder circuit then adds the encoded values together to generate a sum representing the number of trailing zeros in the resultant. The adder circuit then compares the sum to the constant. If the sum is larger than the constant, then the sticky-bit is given a value of zero and, conversely, if the sum is smaller than the constant, the sticky-bit is given a value of one.

Abstract: A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.