Abstract: A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain.

Abstract: A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.

Abstract: A system and method which multiplies the bits using integer multiplication is set forth. More specifically, performing a floating point operation using integer multiplication includes performing a high precision multiplication of an input ‘x’ having a first bit width using a plurality of integer multiplication operations of a second bit width, the second bit width being smaller than the first bit width, the plurality of integer multiplication operations each generating a result corresponding the first bit width.

Abstract: A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.

Abstract: A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M.

Abstract: A Montgomery multiplication device calculates a Montgomery product of an operand X and an operand Y with respect to a modulus M and includes a plurality of processing elements. In a first clock cycle, two intermediate partial sums are created by obtaining an input of length w?1 from a preceding processing element as w?1 least significant bits. The most significant bit is configured as either zero or one. Then, two partial sums are calculated using a word of the operand Y, a word of the modulus M, a bit of the operand X, and the two intermediate partial sums. In a second clock cycle, a selection bit is obtained from a subsequent processing element and one of the two partial sums is selected based on the value of the selection bit. Then, the selected partial sum is used for calculation of a word of the Montgomery product.

Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.

Abstract: A computer program product for converting from a first floating point format to a second floating point format, each floating point format having an associated base value and being represented by a significand value and a exponent value, comprising an executable algorithm to perform the steps of: determining the second exponent value by multiplying the first exponent value by a predefined constant and taking the integer portion of the result, the predefined constant being substantially equivalent to the logarithm of the first base value divided by the logarithm of the second base value; determining a bias value substantially equivalent to the second base value raised to the second exponent value divided by the first base value raised to the first exponent value; and determining the second significand value by multiplying the first significand value by the bias value.

Abstract: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Abstract: A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.

Abstract: A programmable integrated circuit device is programmed to normalize multiplication operations by examining the input or output values to determined the likelihood of overflow or underflow and then to adjust the input or output values accordingly. The examination of the inputs can include an examination of the number of adder stages feeding into the inputs, as well as a count of leading bits ahead of the first significant bit. Adjustment of an input can include shifting the mantissa by the leading bit count and adjusting the exponent accordingly, while adjustment of the output can include shifting the mantissa by the sum of the leading bit counts of the inputs and adjusting the exponent accordingly. Or the output can be examined to find its leading bit count and the output then can be adjusted by shifting the mantissa by the leading bit count and adjusting the exponent accordingly.

Abstract: An apparatus including a processor, a computer readable storage medium, and a lookup memory. The computer readable storage medium generally contains computer executable instruction that when executed by the processor perform operations involving fixed point multiplication. The lookup memory generally stores values used in the fixed point multiplication. The values stored in the lookup memory are approximated based upon a predetermined value to prevent overflow in the fixed point multiplication.

Abstract: A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result, a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero, and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term. The shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation.

Abstract: A method and apparatus provides for performing floating-point division using input check/output correction floating-point division logic and a floating-point division fix-up instruction (e.g., an instruction, command, signal or other indicator). In one example, the apparatus includes a processor having a floating-point arithmetic logic unit (ALU) that includes the input check/output correction floating-point division logic. The input check/output correction floating-point division logic is responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to examine a first input representing a numerator and a second input representing a denominator to determine whether a special case of floating-point division occurs.

Abstract: Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the invention permit calculation of common logarithms of real numbers stored within character arrays, where each element of the array corresponds to a digit in the real number.

Abstract: A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder.

Abstract: A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand. The effective figures depend on the format of the multiplier and the multiplicand. The partial product control circuit controls the status of the enable signal according to a multiplication command designating the format. The multiplication array is constituted by a dynamic circuit. The dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal. When the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.

Abstract: A multipurpose arithmetic functional unit selectably performs planar attribute interpolation, unary function approximation, and double-precision arithmetic. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.

Abstract: A floating point multiplier circuit includes partial product generation logic configured to generate a plurality of partial products from multiplicand and multiplier values. The plurality of partial products corresponds to a first and second portion of the multiplier value during respective first and second partial product execution phases. The multiplier also includes a plurality of carry save adders configured to accumulate the plurality of partial products generated during the first and second partial product execution phases into a redundant product during respective first and second carry save adder execution phases. The multiplier further includes a first carry propagate adder coupled to the plurality of carry save adders and configured to reduce a first and second portion of the redundant product to a multiplicative product during respective first and second carry propagate adder phases. The first carry propagate adder phase begins after the second carry save adder execution phase completes.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. When the operands to the multiply operation are available, they are inspected. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-forwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream.

Abstract: A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the product of the first floating point operand and the second floating point operand. Additionally, the results circuit provides a resulting status embedded within the resulting floating point operand.

Abstract: Disclosed herein is a technique for computing a complex gradient using multiple conics. In connection with a computer system having a graphics processing unit (GPU) in addition to the normal central processing unit (CPU), gradients can be computed in real time. The conics may be rendered and adjusted in a number of ways, providing a rich palette for creation of gradient graphics. The computational efficiency of the algorithms disclosed herein, when executed on typical GPU hardware, allows rendering frame rates high enough to provide animated gradient images.

Abstract: The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is designed and/or controlled to multiply a first whole number by a floating-point number to obtain a product of the multiplication, while the first whole number corresponds either to the applied measured value or the provided adjustment factor; and, the floating-point number corresponds to the other measured value or to the adjustment factor. The computer has a second memory region for the storing of the floating-point number in a format of a second whole number, and the computer is designed and/or controlled to carry out a multiplication of the first whole number and the second whole number.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly on the input side of this selection unit. The first selection units are coupled to each other such that a horizontal and/or vertical logical interconnection of the arithmetic/logic units within a group, and/or a logical interconnection of arithmetic/logic units to an upstream group can be implemented. Second selection units are in each case connected on the output side of a column of arithmetic/logic units. The second selection units of a group are connected on the output side to one bus each, and a microprocessor is coupled to this bus.

Abstract: The first and second n-bit significands are multiplied producing a pair of 2n-bit vectors, and half adder logic produces a corresponding plurality of carry and sum bits. A product exponent is checked for correspondence with a predetermined exponent value. A sum operation generates a first result equivalent to the addition of the pair of 2n-bit vectors. First adder logic uses corresponding m carry and sum bits, the least significant of them carry bits being replaced with the increment value prior to the first adder logic performing the first sum operation. Second adder logic performs a second sum operation and uses the corresponding m?1 carry and sum bits replacing the least significant m?1 carry bits with the rounding increment value prior to the second adder logic second sum operation. The n-bit result is derived from either the first rounded result, the second rounded result or a predetermined result value.

Abstract: Methods and apparatus for providing JPEG decoder functions are described. In particular, features and methods of the present invention are directed to an efficient way of implementing a non-common decoding path function used in an MQ-coder, such as the type used to decode JPEG-2000 images. The methods of the present invention are well suited for implementation on general purpose computers such as conventional personal computers (PCs) and can provide improved decoding speed, compared to known systems which use processing branches as part of a non-common decoding path function by reducing and, in some implementations completely avoiding, branches. Thus, branch prediction penalties associated with known decoding schemes are reduced or avoided leading, in many cases, to faster decoding rates when using a general purpose processor of a given speed or computational capability.

Abstract: A digital processing system and method are described that encodes a fixed point number into a mantissa by removing redundant sign bits by shifting the significant bits to the left. The number of bits shifted is recorded as the exponent. In one embodiment the mantissa and exponent are combined into a single word of memory for the system which allows efficient loading of the value from memory. The mantissa and exponent can be used in multiplication calculations with a second fixed point number to achieve increased dynamic range. When the mantissa is multiplied by the fixed point number, the initial result is larger by a factor of 2exponent, and a bit-shift to the right by the number of bits represented by the exponent removes this factor.

Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

Abstract: An FMA arithmetic unit has a timing control circuit. The timing control circuit controls bypass selectors to bypass intermediate resisters on performing floating point addition/subtraction, controls another bypass selector to bypass another intermediate register on performing floating point multiplication, and controls still another bypass selectors to bypass a register file/other arithmetic unit result register and operand registers on performing successive FMA arithmetic operations.

Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: A shift register has shift register units. The nth shift register unit includes first to third level control units and first and second driving units. The first and second level control units respectively provide a first clock signal and a first voltage to an output terminal. The first driving unit and the first level control unit are coupled to a first node, and a voltage on the first node is a first control signal. The first driving unit turns on and off the first level control unit in response to an input signal and second and third control signals. The second driving unit turns on and off the second level control unit in response to the first control signal. The third level control unit provides the first voltage to the output terminal in response to a front edge of the first control signal of the (n+2)th shift register unit.

Abstract: Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-integer value. The multiplier value is determined by extracting information from a first portion of a bitfield based on the scaled-integer value. The scale value is determined by extracting information from a second portion of the bitfield based on the scaled-integer value. The first and second portions of the bitfield are configurable to include signed integer values. The example method then performs an arithmetic operation based on the multiplier value and the scale value.

Abstract: An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit arithmetic circuit or the finite field GF(2^m) based unit arithmetic circuit, and an adder circuit which has a buffer for storing interim result data, adds the interim result data to the result data obtained by one of the integer unit arithmetic circuit and the finite field GF(2^m) based unit arithmetic circuit which is selected by the selector, propagates a carry in an integer unit arithmetic operation, and propagates no carry in a finite field GF(2^m) based unit arithmetic operation.

Abstract: Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The processing elements are configurable to perform operations corresponding to either the prime field or the binary extension field. In an example, the processing elements include a dual-field adder having a field-select input that permits selection of a field arithmetic. In a representative example, multipliers are implemented as integrated circuits having processing units that each receive a single bit of one operand and partial words of the remaining operand.

Abstract: Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.

Abstract: In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented by a*(2^n) where a mantissa is a and an exponent is n, the mantissa is stored as a fixed point number in the upper U bits of N-bit field (N?(U+L)) and the exponent is stored as an integer in the lower L bits. For the multiplication of two real numbers represented in such a format, these two real numbers are multiplied as fixed point numbers so as to make only the upper significant bits of the multiplication result a mantissa, while these two real numbers are added as integers so as to make only the lower significant bits of the addition result an exponent. As a result, the multiplication result can be obtained in a floating point format.

Abstract: A method and apparatus for performing cryptographic computations employing recursive algorithms to accelerate multiplication and squaring operations. Products and squares of long integer values are recursively reduced to a combination of products and squares reduced-length integer values in a host processor. The reduced-length integer values are passed to a co-processor. The values may be randomly ordered to prevent disclosure of secret data.

Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.

Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.

Abstract: A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.

Abstract: A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.

Abstract: A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.

Abstract: A system and method for reducing the power consumption of a floating point unit of a processor wherein the processor iteratively performs floating point calculations based upon one or more input operands. The exponential value of a floating point is precalculated within an iterative loop through a superscalar instruction buffer resident on the processor that holds at least 3 iterations of the largest single cycle iteration possible on the processor, and the precalculated exponent value is used to generate a bit mask that enables a minimal number of fractional data flow bits. Alternately, a look-ahead can be used to obtain the exponent value from at least two subsequent iterations of the loop.

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. Because the products being summed are in carry-save format, post-normalization is avoided within the adder feedback loop. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. Variable shifters are avoided in the adder mantissa path. A single mantissa shift of thirty-two bits is provided by a conditional shifter.

Abstract: A fast, scalable, systolic modular multiplier based on projection onto planar ring structures is presented. Systolic paradigms of limited fan-out on all signal paths and nearest neighbor interconnections guarantee optimally fast clock rates. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.