Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.

Abstract: A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in a summer (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Abstract: A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.

Abstract: A system for adding or subtracting numbers in signed floating point notation performs exponent and mantissa handling operations in parallel. The system includes a comparator, for determining a greater-magnitude and a lesser magnitude floating point number, operating in parallel with a selector for performing a one's complement and single-bit shift on a mantissa portion of the lesser-magnitude floating point number. The system further includes a remaining shift circuit, for determining an additional amount by which the lesser-magnitude mantissa portion should be shifted; and a shifter. The system also includes an absolute add circuit, for determining whether an absolute addition or an absolute subtraction is to be performed, and a single-bit shift circuit, for indicating whether a shift of at least one bit is required.

Abstract: An improved floating point unit is disclosed. The floating point unit includes a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand. The combined adder-shifter includes an adder portion that operates to generate a number of sum bits for exponent difference between the two floating point operands. The adder portion favors generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits. The combined adder-shifter also includes a shifter portion that operates to shift the mantissa portion of the at least one floating point operand in accordance with the sum bits.

Abstract: An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU includes a shifter, a bypass datapath, and a bypass multiplexer. The shifter receives an operand input and a control input, and shifts the operand input in accordance with the control input. The bypass datapath bypasses the operand input around the shifter. The bypass multiplexer is coupled to the shifter and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable an integer addition if the operand is an integer operand, and selects the shifter to enable a floating point addition or floating point to integer conversion if the operand is a floating point operand. In an alternate embodiment, the FPU includes an alignment unit, an arithmetic logic unit (ALU), a bypass datapath, and a bypass multiplexer. The alignment unit receives a first input and a second input, and aligns them.

Abstract: A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.

Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.

Abstract: An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two.

Abstract: A preloadable floating point unit includes first and second preload registers that hold a next operand and a next top of array (TOA) for use with a next FPU instruction held in an instruction queue pending completion of the current FPU instruction.

Abstract: An execution unit configured to execute vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path includes an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit, which selects one of the output values as a preliminary subtraction result based on a final selection signal received from a selection unit.

Abstract: An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path, conversely, is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path includes an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one.

Abstract: An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path, conversely, is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path may include an adder unit configured to generate a first and second output value. The first output value is equal to the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit, which selects one of the output values as a preliminary subtraction result.

Abstract: With the use of outputs of priority encoders serving as selection signals, final carry signals at respective bits in an adder can be selected as signals indicating whether or not prediction error is present. Accordingly, it is possible to detect earlier whether or not prediction error in a cancelling bit prediction circuit is present.

Abstract: A modular computational structure includes a pipeline having first and second adder stages. Each adder stage includes a pair of adders which operate in parallel, and outputs ports of the first adder stage are coupled to input ports of the second adder stage. Rounding logic and an accumulator are included in the second stage. By varying the inputs to the first and second stages a variety of complex arithmetic functions suitable for video encoding can be implemented. Examples of the operations include completion of multiply and multiply-and-accumulate operations, averages of two values, averages of four values, and merged difference and absolute value calculation.

Abstract: In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit mask; performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits. Further, an apparatus for parallel processing a signed value to form an absolute value comprises: means for performing an arithmetic shift right of N-1 bit to form a bit mask; means for performing an exclusive-OR logical operation with the signed value of N bits and the bit mask to form a result; and means for subtracting the bit mask from the result of the exclusive-OR logical operation to form the absolute value of the signed value of N bits.

Abstract: A method and apparatus for adding floating point numbers. A ones-complement difference between first and second exponents respectively included in first and second floating point values is generated. Depending on whether a sign bit of the ones-complement difference is in a first state or a second state, either a first mantissa included in the first floating point value or a second mantissa included in the second floating point value is shifted. The first and second mantissas are added after one of the first mantissa and the second mantissa has been shifted.

Abstract: An apparatus for generating an end-around carry to an end-around carry adder in a floating-point pipeline within a computer system is disclosed. The apparatus for generating an end-around carry includes a shift-comparison logic circuit, a sign-comparison circuit, and a logic gate. The shift-comparison logic circuit produces a shift-count signal and the sign-comparison logic circuit produces an effective operation signal. Coupled to the shift-comparison logic circuit and the sign-comparison logic circuit, the logic gate combines the shift-count signal and the effective operation signal with a carry-out signal generated by an end-around carry adder to provide an end-around carry signal for the end-around carry adder.

Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.

Abstract: If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder (34) will invert one of its inputs results from an inversion-determination circuit (FIG. 11) that determines whether the sole set bit in a decoded normalization-shift signal (NORM.sub.-- SHIFT) occupies the same position as a set bit in a signal (FRAC.sub.-- A.sub.-- GT.sub.-- B) representing what the possible normalization amounts will be if a first of the mantissas is greater than the other, second mantissa. Consequently, a bit-comparison operation (56) that employs no full-width carry-propagate addition can determine the amount of normalization shifting to be performed by bit shifters (30 and 32) disposed in respective processing trains that generate mantissa inputs to the mantissa adder (34).

Abstract: A circuit for performing prefix computation in an asynchronous digital processor by implementing a serial process and a tree process for the same prefix computation in parallel. The first output from either processes is selected and used for the subsequent operation. For a prefix computation with N inputs, an average-case latency of O(loglog N) can be achieved. Buffering can be used for a full-throughout operation.

Abstract: A floating point subtraction is performed on a first and second floating point number to obtain an exponent result and a fraction result, the first floating point number has a first exponent and a first fraction and the second floating point number has a second exponent and a second fraction. A first adder determines an exponent difference between the first and second exponents and, concurrently with determining the exponent difference, a prediction circuit predicts a massive cancellation prediction and a second adder determines the difference between the first and second fraction and generates a massive cancellation fraction result. Then it is determined whether the massive cancellation result is valid and if so, the massive cancellation fraction result is selected as a basis for the fraction result. If not, a result from the no massive cancellation path is selected as the basis for the fraction result.