Feedback Patents (Class 708/506)
  • Patent number: 8862957
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Weijun Tan, Shaohua Yang, Kelly K. Fitzpatrick, Xuebin Wu, Fan Zhang
  • Patent number: 7653127
    Abstract: Bit-Edge Zero Forcing Equalizer. A novel solution is presented by which a BE-ZFE (Bit-Edge Zero Forcing Equalizer) is employed to drive an error term within a data signal to an essentially zero value. This new BE-ZFE looks at values of data that occur at the bit edges of a data signal and drives the associated error term to zero. The new BE-ZFE is appropriately implemented within communication systems that are phase (or jitter) noise limited. Some examples of such communication systems include high-speed serial links one type of which serviced using a SERDES (Serializer/De-serializer) where data that is originally in a parallel format is serialized into a serial data stream and then subsequently de-serialized back into a parallel data stream.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: January 26, 2010
    Assignee: XILINX, Inc.
    Inventors: Brian T. Brunn, Stephen D. Anderson
  • Patent number: 6701427
    Abstract: A data processing apparatus for processing floating point instructions is responsive to a floating point instruction to apply a floating point operation to a number of operands to produce a final result, result data being generated during a predetermined pipelined stage with further processing then being performed on the result data in one or more subsequent pipelined stages to generate the final result. Exception determination logic determines whether an exception may occur during application of the floating point operation to the operands, and to prevent the execution unit applying the floating point operation to those operands if it is determined that an exception may occur. The exception determination logic is arranged to use at least some of the predetermined control data to compensate for differences between the forwarded result data and the final result relevant when determining whether an exception may occur when processing the second floating point instruction.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 2, 2004
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, Arun Kumar Varadarajan Rajagopal