Parallel Patents (Class 708/507)
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Patent number: 12197887Abstract: Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.Type: GrantFiled: March 13, 2020Date of Patent: January 14, 2025Assignee: Altera CorporationInventors: Roberto DiCecco, Joshua Fender, Shane O'Connell
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Patent number: 11269651Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.Type: GrantFiled: September 10, 2019Date of Patent: March 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Klein, Nicol Hofmann, Cedric Lichtenau, Osher Yifrach
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Patent number: 10275391Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.Type: GrantFiled: January 23, 2017Date of Patent: April 30, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicol Hofmann, Michael Klein, Cédric Lichtenau
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Patent number: 10140091Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.Type: GrantFiled: September 27, 2016Date of Patent: November 27, 2018Assignee: Altera CorporationInventor: Martin Langhammer
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Patent number: 10037192Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.Type: GrantFiled: October 21, 2015Date of Patent: July 31, 2018Assignee: Altera CorporationInventor: Martin Langhammer
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Patent number: 10007487Abstract: Systems and methods for using single-precision floating-point operation digital signal processing (DSP) blocks in conjunction to perform double-precision floating-point operations.Type: GrantFiled: June 30, 2016Date of Patent: June 26, 2018Assignee: Altera CorporationInventor: Tomasz Sebastian Czajkowski
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Patent number: 10003360Abstract: An electronic device for finding error locations in a codeword includes a plurality of power control units configured to find error locations in the codeword. The plurality of power control units are coupled in parallel. Each of the plurality of power control units includes a plurality of corresponding input control circuits to individually turn on or off the corresponding power control unit.Type: GrantFiled: October 3, 2016Date of Patent: June 19, 2018Assignee: Macronix Internatonal Co., Ltd.Inventor: Kuan Chieh Wang
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Patent number: 9600278Abstract: A specialized processing block on a programmable integrated circuit device includes a first floating-point arithmetic operator stage, and a floating-point adder stage having at least one floating-point binary adder. Configurable interconnect within the specialized processing block routes signals into and out of each of the first floating-point arithmetic operator stage and the floating-point adder stage. The block has a plurality of block inputs, at least one block output, a direct-connect input for connection to a first other instance of the specialized processing block, and a direct-connect output for connection to a second other instance of the specialized processing block. A plurality of instances of the specialized processing block are together configurable as a binary or ternary recursive adder tree.Type: GrantFiled: July 15, 2013Date of Patent: March 21, 2017Assignee: Altera CorporationInventor: Martin Langhammer
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Publication number: 20130173682Abstract: A process for propagating an error in a floating-point calculation is disclosed. A floating-point error occurring from the floating-point arithmetic calculation is trapped, and a special value is generated. Information regarding the error is stored as a payload of the special value. Program operations are resumed with the special value applied to further calculations dependent on the floating-point arithmetic calculation.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: MICROSOFT CORPORATIONInventor: Marko Radmilac
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Patent number: 8295412Abstract: An apparatus and method for signal detection in which a digital sample stream is fed round robin into a plurality of buffers, which are sequentially compared with a reference signal to determine a match. A processor determines the chronological order of the samples in each bit of each buffer, and directs a bitwise comparison between the signal in each buffer with the reference to determine a match, e.g., by correlation. The apparatus and method are preferably implemented with a Field-Programmable Gate Array (FPGA). This scheme permits real time correlation of a data stream with a reference without use of shift registers, or a significant number of dedicated logic blocks.Type: GrantFiled: September 30, 2010Date of Patent: October 23, 2012Assignee: The United States of America as represented by the Secretary of the NavyInventor: Jeremy R. O'Neal
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Patent number: 8244650Abstract: A recursive approach to quantum computing employs an initial solution, determines intermediate solutions, evaluates the intermediate solutions and repeats using the intermediate solution, if the intermediate solution does not satisfy solution criteria. A best one of the intermediate solutions may be employed in the recursion.Type: GrantFiled: June 9, 2008Date of Patent: August 14, 2012Assignee: D-Wave Systems Inc.Inventor: Geordie Rose
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Patent number: 8051123Abstract: A multipurpose arithmetic functional unit selectively performs planar attribute interpolation, unary function approximation, double-precision arithmetic, and/or arbitrary filtering functions such as texture filtering, bilinear filtering, or anisotropic filtering by iterating through a multi-step multiplication operation with partial products (partial results) accumulated in an accumulation register. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for unary function approximation and planar interpolation; the same multipliers and adders are also leveraged to implement double-precision multiplication and addition.Type: GrantFiled: December 15, 2006Date of Patent: November 1, 2011Assignee: NVIDIA CorporationInventors: Stuart Oberman, Ming Y. Siu
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Patent number: 7885405Abstract: One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more rounds of a block cipher algorithm. A plurality of N bit registers are respectively coupled to the plurality of digital logic components. An XOR component receives blocks of plaintext data and blocks of ciphertext data, and XORs blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets. The XOR component iteratively feeds the XOR'd blocks of data into a first of the plurality of the digital logic components. In addition, a circuit component is operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component.Type: GrantFiled: June 4, 2004Date of Patent: February 8, 2011Assignee: GlobalFoundries, Inc.Inventor: William Hock Soon Bong
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Patent number: 7814462Abstract: In one embodiment, a process may be performed in parallel on a parallel server by defining a data type that may be used to reference data stored on the parallel server and overloading a previously-defined operation, such that when the overloaded operation is called, a command is sent to the parallel server to manipulate the data stored on the parallel server. In some embodiments, the previously-defined operation that is overloaded may be an operation of an operating system. Further, in some embodiments, when the data stored on the parallel server is no longer needed, a command may be sent to the parallel server to reallocate the memory used to store the data.Type: GrantFiled: August 31, 2005Date of Patent: October 12, 2010Assignees: Massachusetts Institute of Technology, The Regents of the University of CaliforniaInventors: Parry Jones Reginald Husbands, Long Yin Choy, Alan Edelman, Eckart Jansen, Viral B. Shah
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Patent number: 7774393Abstract: An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.Type: GrantFiled: June 30, 2004Date of Patent: August 10, 2010Assignee: Oracle America, Inc.Inventors: Jeffrey S. Brooks, Sadar U. Ahmed
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Patent number: 7627802Abstract: A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks ({right arrow over (b)}i). Each block ({right arrow over (b)}i) is of size (M) and is related to a unit vector ({right arrow over (e)}i). A summation operation on the blocks ({right arrow over (b)}i) given by CRC({right arrow over (b)})=?bi·CRC({right arrow over (e)}i) is performed. Each CRC of the unit vectors (CRC({right arrow over (e)}i)) is stored in a lookup table. The lookup table is tagged by the “one” bits of the message block. An exclusive OR (XOR) operation is performed on each tagged row of the lookup table to calculate the CRC of the message.Type: GrantFiled: August 15, 2006Date of Patent: December 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eran Pisek, Jasmin Oz
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Patent number: 7120248Abstract: A process is provided for searching in parallel for a plurality of prime number values simultaneously includes the steps of: randomly generating a plurality of k random odd numbers (wherein k is preferably more than 2, but could also be one or more) expressed as n0,0, n1,0, . . . n((k?1)),0, each number providing a prime number candidate; determining a plurality of y additional odd numbers based on each one of the randomly generated odd numbers n0,0, n1,0, . . .Type: GrantFiled: March 26, 2001Date of Patent: October 10, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: W. Dale Hopkins, Thomas W. Collins, Steven W. Wierenga, Ruth A. Wang
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Patent number: 6637002Abstract: A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location polynomial corresponding to an error location. A multiplexer is fed by the first search circuit and the second search circuit to produce an error location from the error location polynomial.Type: GrantFiled: October 21, 1998Date of Patent: October 21, 2003Assignee: Maxtor CorporationInventors: Lih-Jyh Weng, Ba-Zhong Shen, Shih Mo, Chung Chang
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Patent number: 6570670Abstract: A method and apparatus for prioritizing the use of multifunctional printing system's basic processing resources to permit job streaming. The printing system employs a controller with an improved job contention manager (JCM). A plurality of basic resources of the printing system are provided with a queue. One or more job services, at desired times, signals the JCM to carry out a sub-job of a given job. The signal for each of the sub-jobs includes information about the respective sub-job's, job service and its priority. Responsive to the signal from the job service the JCM adds a corresponding basic resource sub-job to the queues of each basic resource which the sub-job will require to perform the sub-job. A first of the sub-jobs is placed in an “Active” state ready for processing, if the first sub-job is at the top of all of the queues, of all the basic resources, required to perform the first sub-job.Type: GrantFiled: November 29, 1999Date of Patent: May 27, 2003Assignee: Xerox CorporationInventors: David L. Salgado, Rodney L Turmon, Nicholas M. Lamendola
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Patent number: 6401194Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.Type: GrantFiled: January 28, 1997Date of Patent: June 4, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Le Trong Nguyen, Heonchul Park, Roney S. Wong, Ted Nguyen, Edward H. Yu
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Patent number: 6327605Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: GrantFiled: March 19, 2001Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka
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Patent number: 6243732Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: GrantFiled: January 7, 2000Date of Patent: June 5, 2001Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka
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Patent number: 6038582Abstract: A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.Type: GrantFiled: October 15, 1997Date of Patent: March 14, 2000Assignee: Hitachi, Ltd.Inventors: Fumio Arakawa, Norio Nakagawa, Tetsuya Yamada, Yonetaro Totsuka