Abstract: An embodiment of an apparatus performs a floating-point multiply-add process on a first multiplicand, a second multiplicand, and an addend. A leading 0 bit is added to a mantissa of the first multiplicand to form an expanded first mantissa, and a partial-product multiplication is performed on the expanded first mantissa and a mantissa of the second multiplicand to produce partial-product sum and a partial-product carry mantissas. Leading bits of the partial-product sum and carry mantissas are changed to 0 bits if they are both 1 bits, and the partial-product sum and the partial-product carry are shifted right according to an exponent difference of a product of the first multiplicand and the second multiplicand. Otherwise both the partial-product sum and carry mantissas are arithmetically shifted right according to the exponent difference. The first and second multiplicands and the addend can be complex numbers.

Abstract: Provided two CORDIC processors, each including: two input ports representing real and imaginary input ports; and two output ports representing real and imaginary output ports; wherein real and imaginary parts of a first input signal are applied to the imaginary input ports of the first and second CORDIC processors; real and imaginary parts of a second input signal are applied to the real input ports of the first and second CORDIC processors; the first and second CORDIC processors rotate the respective input signals applied thereto by 45 degrees in the clockwise direction; respective data from the real output ports of said first and second CORDIC processors constitute real and imaginary parts of a first output signal; and respective data from the imaginary output ports of said first and second CORDIC processors constitute real part and imaginary part of a second output signal.

Abstract: An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend.

Abstract: A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations.

Abstract: Improvements to optimal interval operators are developed for interval expression evaluation using arithmetic and real power operators applied to complex and hypercomplex number systems. A method for determining efficacy of numeric precision, incorporating minor changes to interval operators, provides detection of insufficient numeric evaluation precision.

Abstract: A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations

Abstract: A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations.

Abstract: A modified Gram-Schmidt QR decomposition core implemented in a single field programmable gate array (FPGA) comprises a converter configured to convert a complex fixed point input to a complex floating point input, dual port memory to hold complex entries of an input matrix, normalizer programmable logic module (PLM) to compute a normalization of a column vector. A second PLM performs complex, floating point multiplication on two input matrix columns. A scheduler diverts control of the QRD processing to the normalizer PLM or the second PLM. A top level state machine communicates with scheduler and monitors processing in normalizer PLM and second PLM and communicates the completion of operations to scheduler. A complex divider computes final column for output matrix Q using floating point arithmetic. Multiplexer outputs computed values as elements of output matrix Q or R. Complex floating point operations are performed in a parallel pipelined implementation reducing latencies.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations

Abstract: Improvements to optimal interval operators are developed for interval expression evaluation using arithmetic and real power operators applied to complex and hypercomplex number systems. A method for determining efficacy of numeric precision, incorporating minor changes to interval operators, provides detection of insufficient numeric evaluation precision.

Abstract: A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations.

Abstract: Improvements to optimal interval operators are developed for interval expression evaluation using arithmetic and real power operators applied to complex and hypercomplex number systems. A method for determining efficacy of numeric precision, incorporating minor changes to interval operators, provides detection of insufficient numeric evaluation precision.

Abstract: Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.

Abstract: The present invention describes a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a logarithmic format. In one exemplary embodiment, an ALU implements logarithmic arithmetic on complex numbers represented in a logpolar format. According to this embodiment, memory in the ALU stores a look-up table used to determine logarithms of complex numbers, while a processor in the ALU generates an output logarithm based on complex input operands represented in logpolar format using the stored look-up table. In another exemplary embodiment, the ALU performs logarithmic arithmetic on real and complex numbers represented in logarithmic format.

Abstract: A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field.

Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which a real part and an imaginary part of a product of the multiplying can be stored in a same register of the processor. First data is conveyed along at least a first interconnect of the processor. The first data has a first operand. The first operand represents a first complex number. Second data is conveyed along at least a second interconnect of the processor. The second data has a second operand. The second operand represents a second complex number. The first operand is multiplied at the execution unit by the second operand to produce a first result. The first result represents a third complex number. Third data is stored at a first register of the processor. The third data has the first result. The first result has at least the product of the multiplying.

Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which all four scalar multiplications, concomitant to multiplying two complex numbers, can be performed in parallel. A real part of a first complex number is multiplied at the execution unit by a real part of a second complex number to produce a first part of a real part of a third complex number. An imaginary part of the first complex number is multiplied at the execution unit by an imaginary part of the second complex number to produce a second part of the real part of the third complex number. A first arithmetic function is performed at the execution unit between the first part of the real part of the third complex number and the second part of the real part of the third complex number. The imaginary part of the first complex number is multiplied at the execution unit by the real part of the second complex number to produce a first part of an imaginary part of the third complex number.

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication.