Logarithmic Format Patents (Class 708/512)
  • Patent number: 11720355
    Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Patent number: 11693625
    Abstract: An integrated circuit including a plurality of logarithmic addition-accumulator circuits, connected in series, to, in operation, perform logarithmic addition and accumulate operations, wherein each logarithmic addition-accumulator circuit includes: (i) a logarithmic addition circuit to add a first input data and a filter weight data, each having the logarithmic data format, and to generate and output first sum data having a logarithmic data format, and (ii) an accumulator, coupled to the logarithmic addition circuit of the associated logarithmic addition-accumulator circuit, to add a second input data and the first sum data output by the associated logarithmic addition circuit to generate first accumulation data. The integrated circuit may further include first data format conversion circuitry, coupled to the output of each logarithmic addition circuit, to convert the data format of the first sum data to a floating point data format wherein the accumulator may be a floating point type.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: July 4, 2023
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Frederick A. Ware, Cheng C. Wang
  • Patent number: 11494676
    Abstract: A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations. The inline post processing unit is further configured to accept data from a set of registers maintaining output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the one or more non-linear mathematical operations on elements of the data from the processing block via their corresponding lookup tables, and stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 8, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Avinash Sodani, Ulf Hanebutte, Chia-Hsin Chen
  • Patent number: 11119733
    Abstract: An execution unit for a processor, the execution unit comprising: a look up table; a preparatory circuit configured to determine an index value in dependence upon the operand and search the look up table using the index value to locate an entry comprising a natural logarithm associated with the index value; control circuitry configured to provide a first value determined in dependence upon the operand and a second value determined in dependence upon the operand as inputs to at least one multiplier circuit of the execution unit so as to evaluate terms of a Taylor series expansion of a natural logarithm, wherein the control circuitry is configured to provide the natural logarithm associated with the index value and the terms of the Taylor series expansion as inputs to at least one addition circuit so as to generate a mantissa of a natural logarithm of the operand.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 14, 2021
    Assignee: GRAPHCORE, LIMITED
    Inventor: Jonathan Mangnall
  • Patent number: 10564930
    Abstract: Reduced precision computer number formats inherently limit the quantity of discrete numeric values that can be represented. Therefore, the solution values of an arithmetic function, for each numeric value that is individually and uniquely expressible utilizing such a reduced precision computer number format, can be precomputed since the quantity of unique solution values can be limited to a quantity that can be conveniently stored, such as in an array. Subsequently, rather than computing the solution value of such an arithmetic function, for a given input value, the precomputed array can be referenced and a solution value corresponding to the given input value can be read from the array. Reading numeric values from an array can be substantially faster than computing solution values of a computationally-expensive arithmetic function.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Saurabh Mohan Kulkarni, Marc Tremblay
  • Patent number: 9779272
    Abstract: Embodiments of the present disclosure are based on a recognition that some processors are configured with instructions to compute logarithms and exponents (i.e. some processors include log and exp circuits). Embodiments of the present disclosure are further based on an insight that the use of the existing log and exp circuits could be extended to compute certain other functions by using the existing log and exp circuits to transform from a Cartesian to a logarithmic domain and vice versa and performing the actual computations of the functions in the logarithmic domain, which may be computationally easier than performing the computations in the Cartesian domain.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: October 3, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Timothy J. Caputo, Donald F. Porges
  • Patent number: 8649508
    Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 11, 2014
    Assignee: Tata Consultancy Services Ltd.
    Inventor: Natarajan Vijayarangan
  • Patent number: 8631061
    Abstract: A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2^X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 and determines a power value (log2(1+X1/223)) through an interpolation process. A logarithmic calculator determines a logarithmic value Z=log2 XY=Y(X2+log2(1+X1/223)) from the exponent X2 and the power value from the interpolation processor. The integer/fraction splitter splits the logarithmic value Z into an integer Zint and a fraction Zamari. The interpolation processor references a power of fraction table storage unit in response to the fraction Zamari and determines a power value (2^Zamari) through the interpolation process. The power calculator determines XY=2^Z=(2^Zamari)×(2^Zint), thereby resulting in the input value X to the power of Y.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: January 14, 2014
    Assignee: Sony Corporation
    Inventor: Yukihiko Mogi
  • Publication number: 20130339417
    Abstract: A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juergen Haess, Michael K. Kroener, Silvia M. Mueller, Kerstin Schelm
  • Publication number: 20130103732
    Abstract: One aspect of the present invention will provide a circular floating-point number generator (400) for generating, from an input fixed-point number, a circular floating-point number including sign-bit field (S), exponent field (E), and circular-mantissa field (M). The generator assigns the input bits in the fixed-point number to a plurality of slots, generates the sign-bit field (S), generate the exponent field (E) based on a bit position of a leading significant bit, and generate the mantissa field (M) by extracting a first bit group and a second bit group and by providing a start bit of the first bit group after a last bit of the second bit group.
    Type: Application
    Filed: July 1, 2010
    Publication date: April 25, 2013
    Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Kazunori Asanaka
  • Publication number: 20120166510
    Abstract: An algorithm for efficiently compressing floating-point data in 3D meshes is disclosed. 3D meshes are represented by topology data, geometry data and property data. Geometry data specify vertex locations and are usually represented by floating-point coordinates. While geometry data are usually compressed by quantization, prediction and entropy coding, the present invention uses no prediction. A floating-point number consists of mantissa and exponent, and normally the exponent, sign and mantissa are compressed separately. A method for encoding floating-point formatted data comprises determining if a current floating-point value was previously stored in a memory, storing the current value in the memory if it was not previously stored in the memory, and encoding it. Otherwise, if the current floating-point value was previously stored in a memory, the storage position of the value within the memory is determined and a reference pointing to the storage position is encoded.
    Type: Application
    Filed: September 9, 2010
    Publication date: June 28, 2012
    Inventors: Qu Qing Chen, Tong Zhou, Zhi Bo Chen
  • Publication number: 20100030833
    Abstract: A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2?X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 and determines a power value (log2(1+X1/223)) through an interpolation process. A logarithmic calculator determines a logarithmic value Z=log2XY=Y(X2+log2 (1+X1/223)) from the exponent X2 and the power value from the interpolation processor. The integer/fraction splitter splits the logarithmic value Z into an integer Zint and a fraction Zamari. The interpolation processor references a power of fraction table storage unit in response to the fraction Zamari and determines a power value (2?Zamari)through the interpolation process. The power calculator determines XY=2?Z=(2?Zamari)×(2?Zint), thereby resulting in the input value X to the power of Y.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Applicant: Sony Corporation
    Inventor: Yukihiko Mogi
  • Publication number: 20080208939
    Abstract: A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element decoding unit is input, of information excluding a sign bit from the external information, specifying an exponent that is a bit position where a value different from a sign bit first appears, a mantissa obtaining unit obtaining information of 1-bit or a plurality of bits in a position next to the exponent as a mantissa out of the external information, a storage unit storing the exponent and the mantissa and a restoring unit restoring the external information by reading the exponent and the mantissa stored in the storage unit, wherein the element decoding unit performs iteration decoding based on the restored external information is utilized.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Inventors: Shunji Miyazaki, Kazuhisa Obuchi, Junya Mikami
  • Patent number: 7003541
    Abstract: A zero-knowledge proving system includes a proving mechanism for proving equality or inequality of two discrete logarithms and a verifying mechanism for verifying said equality or inequality. The proving mechanism stores public information including a designated operation scheme, two input numbers ? and ?, and two predetermined bases g and h, private information x which is a discrete logarithm of ? to the base g. After converting ?, ? and h to produce ??, ?? and ?? as follows: ??=?r; ??=?r; and ??=hxr, the equality of a log??? and log??? and the equality of logg?? and logh?? are proved. The verifying mechanism verifies the equality of a log??? and log??? and the equality of logg?? and logh??. Then, the received ?? and ?? are checked to determine the equality or inequality thereof, and it is determined whether the proof is acceptable, depending on the verification and the check results.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: February 21, 2006
    Assignee: NEC Corporation
    Inventors: Jun Furukawa, Kazue Sako, Satoshi Obana
  • Patent number: 6961744
    Abstract: A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the format. The logarithm unit determines a magnitude of an unbiased exponent of the floating point operand as an intermediate result based on the at least one signal, wherein the unbiased exponent is represented by unbiased exponent bits. Still further, the logarithm unit determines an exponent field and a fraction field high part of the intermediate result.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 1, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Publication number: 20040267854
    Abstract: A system and method is provided for determining a logarithm of an input value and a system and method for determining an inverse logarithm for an input value. The system and method determine an integer value relating to the logarithm and performs a linear interpolation over a range relating to the integer value. A mantissa value is produced from the linear interpolation and corrected over one or more correction stages. The inverse logarithmic system and method receive an input value comprising an integer value and a mantissa value. The mantissa value is precorrected over one or more precorrection stages. The precorrected mantissa is then combined with a value related to the integer value and multiplied by a restoration factor to produce the inverse logarithm.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Inventors: Towfique Haider, Walter H. Demmer, Bart DeCanne
  • Patent number: 6711601
    Abstract: A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: March 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshitsugu Inoue, Hiroyuki Kawai, Junko Kobara, Robert Streitenberger
  • Publication number: 20040010532
    Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (−1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2−K)+(Bx·2−N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1≦Mx<2, fx is a N-bit fraction, Ax is a value of the most significant K bits of fx, Bx is a value of the least significant (N−K) bits of fx, 0≦K<N, and p, K, N are natural numbers. The apparatus includes: a first multiplier, a logarithmic table, a first adder, a divider, a Taylor-Series approximation circuit, a second multiplier, and a second adder.
    Type: Application
    Filed: July 9, 2002
    Publication date: January 15, 2004
    Applicant: Silicon Integrated Systems Corp.
    Inventor: Chung-Yen Lu
  • Patent number: 6480873
    Abstract: A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: November 12, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Inoue, Hiroyuki Kawai, Junko Kobara, Robert Streitenberger, Keijiro Yoshimatsu, Hiroyasu Negishi
  • Publication number: 20010044815
    Abstract: A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.
    Type: Application
    Filed: February 5, 2001
    Publication date: November 22, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Inoue, Hiroyuki Kawai, Junko Kobara, Robert Streitenberger
  • Patent number: 6233595
    Abstract: A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand, wherein the integer operand is an integer power of two. Once detected, a multiplication operation meeting these criteria may be executed by using an integer adder to sum the integer power and the floating point operand's exponent to from a product exponent. The bias of the integer operand's exponent may also be subtracted. A product mantissa is simply copied from the floating point operand's mantissa. The floating point operand's sign bit may be inverted to form the product's sign bit if the integer operand is negative. Advantageously, the product is generated using integer addition which is faster than floating point multiplication. The method may be implemented in hardware or software.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: May 15, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lei Cheng, Frank J. Gorishek, IV, Yi Liu
  • Patent number: 6182100
    Abstract: A method for performing a logarithmic estimation on a positive floating-point number within a data processing system is disclosed. A floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. A fraction part of an estimate is obtained via a table lookup utilizing the fraction bits of the floating-point number as input. An integer part of the estimate is obtained by converting the exponent bits to an unbiased representation. The integer part is then concatenated with the fraction part to form an intermediate result. Subsequently, the intermediate result is normalized to yield a mantissa, and an exponent part is produced based on the normalization. Finally, the exponent part is combined with the mantissa to form a floating-point result.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: January 30, 2001
    Assignee: International Business Machines Corporation
    Inventor: Martin Stanley Schmookler
  • Patent number: 6178435
    Abstract: A method for performing a power of two estimation on a floating-point number within a data processing system is disclosed. The floating-point number includes a sign bit, multiple exponent bits, and a mantissa having an implied one and multiple fraction bits. In order to estimate the power of two of the floating-point number, the mantissa is partitioned into an integer part and a fraction part, based on the value of the exponent bits. A floating-point result is formed by assigning the integer part of the floating-point number as an unbiased exponent of the floating-point result, and by converting the fraction part of the floating-point number via a table lookup to become a fraction part of the floating-point result.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: January 23, 2001
    Assignee: International Business Machines Corporation
    Inventor: Martin Stanley Schmookler
  • Patent number: 6128638
    Abstract: A hardware implementation solves for the value of X.sup.Y, where X and Y are real (fixed point or floating point) numbers by using the formula X.sup.Y =exp (log.sub.e (X.sup.Y))=exp(ln(X.sup.Y))=exp(Y*ln(X)). A fixed point representation of X, output from a flip-flop, is used to address a floating point data output from an ln(X) ROM lookup table. The floating point data output is output from a second flip-flop and multiplied by Y in a multiplier to yield a product. The product is output from a third flip-flop to address a fixed point data output from an exp(X) ROM lookup table. The fixed point data output is latched by and output from a third flip-flop. The fixed point data output approximates X.sup.Y, using a minimal amount of die area on the semiconductor and minimal amount of processing power. Also, the present invention can be fully pipelined, such that one calculation can be conducted every cycle and operations can occur simultaneously.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: October 3, 2000
    Assignee: Silicon Graphics, Inc.
    Inventor: Jeffrey Oliver Thomas