Abstract: The present disclosure provides a compressor circuit, a Wallace tree circuit, a multiplier circuit, a chip and an apparatus. The compressor circuit includes a first full adder, a second full adder, and a first selection circuit. An output end of the first full adder is connected to an input end of the first selection circuit, and an output end of the first selection circuit is connected to an input end of the second full adder. The first selection circuit is configured to determine an input signal output by the first selection circuit to the second full adder according to a first selection signal; and the input signal output by the first selection circuit to the second full adder and a most significant bit signal of a plurality of input signals of the compressor circuit are used to control turning on and turning off of the second full adder, which can reduce circuit power consumption and delay.

Abstract: The present disclosure relates generally to techniques for enhancing packing density of carry-chains implemented on an integrated circuit. In particular, a packed-carry chain may be implemented to redistribute and/or emulate the logic of a first number of arithmetic logic cells of a first and/or second carry-chain using a second number of arithmetic logic cells less than or equal to the first number. By fitting the first and second carry-chain into such a packed carry-chain, the area consumed to perform the arithmetic operations of the first and second carry-chain may be reduced. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., wiring, area, and power).

Abstract: According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

Abstract: One example method includes identifying synchronous code including instructions specifying a computing operation to be performed on a set of data; transforming the synchronous code into a pipeline application including one or more pipeline objects; identifying a first input data set on which to execute the pipeline application; executing the pipeline application on a first input data set to produce a first output data set; after executing the pipeline application on the first input data set, identifying a second input data set on which to execute the pipeline application; determining a set of differences between the first input data set and second input data set; and executing the pipeline application on the set of differences to produce a second output data set.

Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.

Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.

Abstract: A device and method for resisting, non-invasive attacks are disclosed herein. The device includes a random number generator that generates a random number, and a multiplier that multiplies first data and second data in a unit of a bit length determined based on the random number.

Abstract: A technique realizes execution of various combinations of arithmetic operations in, for example, SIMD floating-point multiply-add arithmetic operation, with less instruction kind codes. An arithmetic operating apparatus sets, in one or more unused bits of a single arithmetic instruction, particular instruction information to instruct at least one of arithmetic operators to perform a process different from an ordinary process.

Abstract: A floating point multiply and addition/subtraction implementation is provided. Two operands are received in a standard floating point format with a code selecting a mathematic operation from addition, subtraction, and multiplication. Result mantissas and exponents are calculated simultaneously for all operations. The implementation simplifies computation of a result mantissa by dropping the least significant bits of the operands before computing the result. Underflow and overflow errors are shown by two extra bits in the exponent portion of the result. The mantissa result and the exponent result are selected by providing the operation code to a mantissa multiplexer and an exponent multiplexer. The selected mantissa and exponent are combined as output.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.

Abstract: A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.

Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).

Abstract: A method and apparatus for performing a floating-point operation with a floating-point processor having a given precision is disclosed. A subprecision for the floating-point operation on one or more floating-point numbers is selected. The selection of the subprecision results in one or more excess bits for each of the one or more floating-point numbers. Power may be removed from one or more components in the floating-point processor that would otherwise be used to store or process the one or more excess bits, and the floating-point operation is performed with power removed from the one or more components.

Abstract: A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index.

Abstract: A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2? to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing U by V, is a positive number, the dividing unit overwrites the subtraction result to U. The dividing unit repeats such operations of dividing the subtraction result by V, until the positive number determining section determines that the subtraction result of subtracting the remainder from the quotient, both found by dividing U by V, is a non-positive number. When the subtraction result becomes a non-positive number and the quotient and the remainder match, a packet length determining section determines that received data has a normal size, and notifies it to a discard determining section.

Abstract: Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathematical operation when at least one operand has n bits, the reconfigurable circuits performs a first sub-operation on m of n bits in a first reconfiguration cycle, and a second sub-operation on p of n bits in a second reconfiguration cycle. The reconfigurable IC also includes at least one storage element for storing at least a portion of the results of the first sub-operation for use during the second reconfiguration cycle in the second sub-operation.

Abstract: A bit selection circuit that arbitrarily selects, from among (2n) input bits, (2n?1) continuous output bits in the input bit arrangement (where n?3), includes: a first multiplexer selecting {(2n?2)?(20+21+ . . . +2n?3)} continuous bits in the input bit arrangement from among (2n?2) input bits, excluding two first and (2n)th input bits at both ends in the input bit arrangement, in accordance with an input first control signal; and a second multiplexer selecting (2n?1) continuous output bits in the input bit arrangement from among the {(2n?2)?(20+21+ . . . +2n?3)} bits selected by the first multiplexer, the first input bit, and the (2n)th input bit in accordance with an input second control signal.

Abstract: In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.

Abstract: The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.

Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Abstract: Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.

Abstract: Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.

Abstract: The computation time to perform scalar point multiplication in an Elliptic Curve Group is reduced by modifying the Barrett Reduction technique. Computations are performed using an N-bit scaled modulus based a modulus m having k-bits to provide a scaled result, with N being greater than k. The N-bit scaled result is reduced to a k-bit result using a pre-computed N-bit scaled reduction parameter in an optimal manner avoiding shifting/aligning operations for any arbitrary values of k, N.

Abstract: An arithmetic unit of arbitrary-precision, including: a main processing unit, which splits up the first and the second arbitrary-precision values into N-bit (where N is a natural number) operands respectively in the-least-significant-bit-first order for computing with the arbitrary-precision data and consecutively outputting a series of pairs of the first and second N-bit operands; and an N-bit arithmetic unit, which performs computing with the N-bit operands, while requesting the main processing unit to feed the next N-bit operands each time the computation completes. The carry bit generated by the operation is fed to the next N-bit operation.

Abstract: An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generated on the basis of bit signals (a0-a15, b0-b15) for the portion from the 1st digit to the 15th digit of the input data, and of carry signal CIN input to the 1st digit, and it is output from CLA 204. Then, carry signal c15 from the 16th digit to the 17th digit is generated based on said generated carry signal c14 and bit signals (a15, b15) of the 16th digit of the input data, and this is output from CIA 205. Exclusive-NOR circuit 206 then operates on said carry signals c14 and c15, and overflow detection signal OVF16 is generated.

Abstract: An arithmetic unit includes a memory, an arithmetic logic unit, a register and a combining circuit. The arithmetic logic unit executes a predetermined arithmetic operation with respect to the data read from memory. The register temporarily stores the data read from the memory. The combining circuit selects one of the arithmetic logic unit and the register. The combining circuit replaces a part of the data read from the memory with output data received from the selected one of the arithmetic logic unit and the register.

Abstract: An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry.

Abstract: One aspect of an embodiment of the invention provides a method and platform to prove to a challenger that a responder device possesses cryptographic information from a certifying manufacturer. This is accomplished by performing a direct proof by the responder device to prove that the responder device possesses the cryptographic information. The direct proof comprises at least one exponentiation being conducted using an exponent having a bit length no more than one-half a bit length of a modulus (n).

Abstract: A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a distinct data path through the adder. For each set of numbers, the system further includes a logic gate for inhibiting a carry path, from each portion of the adder corresponding to each carry path, to a next adjacent carry path. The system isolates two or more contiguous data paths through the fixed-width adder corresponding to each of the two or more sets of two binary numbers. The invention prevents unwanted signals from crossing summing lane boundaries in different processing modes. The same adder logic can thus be used for each processing mode by varying the combination of mode select control signals.

Abstract: A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified opcode, a first 3-to-2 compressor for receiving a respective least significant bit of said operands or its complement, and a Half Adder coupled to the first 3-to-2 compressor and responsive to an output thereof and to said opcode for outputting a least significant bit of a sum equal to A+B+C or A+B?C or A?B+C or A?B?C. A plurality of 3-to-2 compressors each in respect of remaining bits of the operands receive a respective bit of the operands or its complement, and a 2-input adder coupled to the 3-to-2 compressors receive respective carry and save outputs thereof and computing respective bits of the sum apart from the least significant bit.

Abstract: A converter to convert an N-bit input in a linear scale to an M-bit output in a logarithmic scale. The converter includes a set of K subrange converters each coupled to a respective number of bits of the N-bit input that represents a subrange of the N-bit input, each subrange converter to convert the subrange into a respective output that would be the M-bit output if the most significant set bit in the N-bit input was in the subrange. The converter further includes a range selector having the N-bit input as an input, to indicate which of the subranges to select for an output, and a selector having as inputs the outputs of the subrange converters and coupled to the range selector to select the output of one of the subrange converters as the M-bit output. In one embodiment, the converters operate in parallel.

Abstract: Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply operations on a series of smaller operands to form partial products, and adding the partial products together. Data manipulation instructions are used to reposition 16-bit segments of the 32-bit operands into positions that allow the multi-media parallel multiply instructions to compute partial products, and the partial products are then added together to form the result. In every embodiment, the present invention achieves better latencies than the prior art method of performing integer multiply operations provided by the IA-64 architecture.

Abstract: When performing data processing operations upon data words 2, 4 including a plurality of abutting data values a0, a1, a2, a3, b0, b1, b2 and b3 the results of the operation upon one data value may influence a neighboring data value in an undesired manner. An error correcting value 34 may be determined from the input data words 2, 4 and then combined with the intermediate result 32 to correct for any undesired interactions between adjacent data values.

Abstract: An adder or an integrated circuit including an adder, includes a hierarchical carry-select split adder capable of operating in a split mode of operation when a mode select input takes on a first state. It is also capable of operating in a hierarchical carry-select mode of operation when the mode select input takes on a second state.

Abstract: A programmable and configurable datapath unit (DPU) includes a configuration of single-bit multi-function processing units (PUs). The DPU can perform any of a variety of functions depending on the control applied to each PU. Functionality can be increased by utilizing multiplexers to direct data into, out of, and through each DPU dependent on the selected function being performed. Datapath units can also be configured and interconnected to form larger datapath circuits, arrays, and systems so as to increase the data throughput of the datapath system. A configurable and programmable datapath array includes rows of datapath units which can be interconnected to provide DPU circuits having varying input operand widths and functions. A datapath system can be constructed with a plurality of arrays of DPUs to further increase system data throughput.

Abstract: An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2 bits. The two paths can operate in parallel, but since the two paths have different data widths, they can more effectively operate with the different data sizes.

Abstract: A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of operands of the instruction set architecture. The data typer and aligner is selectively configued to align and select one of more sets of data bits from one or more data buses as operands for functional blocks of the signal processor in response to fields of an instruction.

Abstract: An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x≧2n/2m is satisfied. When an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1 is a natural number and is variable) is satisfied.

Abstract: A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal. The transistor stacks comprise silicon-on-insulator (SOI) transistors.

Abstract: A multiplier for multiplying n bits and n/2 bits is disclosed, wherein a word multiplication is implemented by input of two words. The apparatus includes an encoder receiving the two words and pretreating one of the two words, a partial product generating unit outputting a partial product by multiplying the pretreated word and the unpretreated word from the encoder in accordance with a word control signal, a Wallace tree adder dividing the partial product into first and second output signals, and an adder receiving the first and second output signals and outputting word and byte multiplication output results in accordance with the word control signal.

Abstract: An integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circuit receives another portion of the operands to be summed, along with corresponding carry-in inputs. Multiplexers between the first and second adder circuits determine whether the carry-in inputs to the second adder circuit are the same the carry-in inputs to the first adder circuit or whether the carry-in inputs to the second adder circuit are independent.

Abstract: A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry multiplexer selects one of a plurality of possible carry inputs to the following sections. The data processing circuit may make the specification of the selection of the carry control multiplexers by: the opcode of the instruction; a combination of the opcode and an opcode modification field; an immediate field directly specifying carry control signals; or designation a carry control register which stores the carry control signals. The adder unit may be divided into sections of equal size or of unequal size.

Abstract: An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

Abstract: An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

Abstract: Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask signal based on an amount of shift and split mode information. An output selector replaces data shifted by the shifter with code extension data bit by bit based on the mask signal, and outputs data which are shifted and code-extended according to the split mode information and arithmetic/logical shift information. In a carry-select type adder/subtractor as another embodiment, if split parallel process is to be executed, both a pair of unit adders/subtractors execute an arithmetic operation to be carried out for the case where no carry is supplied from lower digits, and then a selector selects an arithmetic result, which is obtained when no carry is supplied from lower digits, regardless of the carry from the lower digits.

Abstract: Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask signal based on an amount of shift and split mode information. An output selector replaces data shifted by the shifter with code extension data bit by bit based on the mask signal, and outputs data which are shifted and code-extended according to the split mode information and arithmetic/logical shift information. In a carry-select type adder/subtractor as another embodiment, if split parallel process is to be executed, both a pair of unit adders/subtractors execute an arithmetic operation to be carried out for the case where no carry is supplied from lower digits, and then a selector selects an arithmetic result, which is obtained when no carry is supplied from lower digits, regardless of the carry from the lower digits.

Abstract: A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

Abstract: The process for performing operations with a variable arithmetic does not call for any shifting of the data in the different registers that come into play in the operation. The input registers can have empty parts which are completed by appropriate bit sequences to ensure a propagation of a possible outgoing carry over in order to recover that carry over from a result register.