Status Condition/flag Generation Or Use Patents (Class 708/525)
  • Patent number: 10235176
    Abstract: Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 19, 2019
    Assignees: The Charles Stark Draper Laboratory, Inc., The National Institute for Research in Data Processing and Automation
    Inventors: Andreā€² DeHon, Eli Boling, Catalin Hritcu
  • Patent number: 10168993
    Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
  • Patent number: 10133760
    Abstract: A hardware accelerator includes a bitmap processor that processes a bitmap structure for multiple list population. A population count processor processes population counts for data and aggregates the population counts. The bitmap data structure includes bitmap bit fields interleaved with aggregated population count fields.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gopi K. Attaluri, Ronald J. Barber, Vincent Kulandaisamy, Vijayshankar Raman, Richard S. Sidle
  • Patent number: 10133577
    Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Dennis R. Bradford, Jonathan C. Hall, Thomas D. Fletcher, Brian J. Hickmann, Dror Markovich, Amit Gradstein
  • Patent number: 10101967
    Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
  • Patent number: 10073635
    Abstract: Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. The method can include, responsive to determining the particular endianness format is a first endianness format, reordering bits of each byte of the plurality of bytes on a bytewise basis, storing the reordered plurality of bytes in an array of memory cells, and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array. The method can include, responsive to determining the particular endianness format is a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jeremiah J. Willcock, Kyle B. Wheeler, Timothy P. Finkbeiner
  • Patent number: 9996521
    Abstract: A method validates a formula within a spreadsheet. A formula type, of an identified formula from a spreadsheet, is identified. A database of known accurate formulas, whose type matches a formula type of the identified formula within the spreadsheet, is identified and located. A determination is made as to whether the identified formula from the spreadsheet matches a known accurate formula from the database. In response to the identified formula from the spreadsheet failing to match the known accurate formula from the database, a predefined action is initiated.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Cudak, Christopher J. Hardee, Adrian X. Rodriguez
  • Patent number: 9804998
    Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Sergeevich Rumyantsev, Dmitri Yurievich Pavlov, Alexander Nikolayevich Redkin, Daniil Valentinovich Demidov, Dmitry Anatolievich Gusev
  • Patent number: 9519459
    Abstract: A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: December 13, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Nam Sung Kim, Syed Gilani, Michael Schulte
  • Patent number: 9507565
    Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: November 29, 2016
    Assignee: ALTERA CORPORATION
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Hyun Yi
  • Patent number: 8838665
    Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction, and execution logic configured to receive the plurality of operands and the multiply operation. The execution logic includes a first logic path configured to perform the multiply operation on the plurality of operands and output a result, and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 16, 2014
    Assignee: Nvidia Corporation
    Inventor: Scott Pitkethly
  • Patent number: 8781110
    Abstract: A system for performing public key encryption is provided. The system supports mathematical operations for a plurality of public key encryption algorithms such as Rivert, Shamir, Aldeman (RSA) and Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The system supports both prime fields and different composite binary fields.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Erdinc Ozturk, Gilbert Wolrich, Wajdi K. Feghali
  • Publication number: 20140181165
    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca
  • Patent number: 8762444
    Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The execution logic includes a primary logic path configured to perform the arithmetic operation on such operands and a secondary parallel logic path configured to output metadata associated with the result of the arithmetic operation.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: June 24, 2014
    Assignee: NVIDIA Corporation
    Inventors: Peter Gentle, Scott Pitkethly
  • Patent number: 8694571
    Abstract: Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding logic then can provide the valid data values so that operations on the valid data values can be performed in accordance with instructions received from an associated program.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 8, 2014
    Assignee: BlackBerry Limited
    Inventors: John F. A. Dahms, David P. Yach
  • Patent number: 8667041
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael F Cowlishaw, Shawn D Lundvall, Ronald M Smith, Phil C Yeh
  • Patent number: 8560591
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh, Michael Frederic Cowlishaw
  • Patent number: 8539015
    Abstract: To perform a binary-coded decimal (BCD) calculation, a processor receives values on which the BCD calculation is to be performed. A carry resulting from the BCD calculation is stored in a flag register of the processor, and the carry stored in the flag register is used to compute a result of the BCD calculation.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: September 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Cyrille De Brebisson
  • Publication number: 20130013656
    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 10, 2013
    Inventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca
  • Patent number: 8305471
    Abstract: The present invention relates to improved imaging devices having high dynamic range and to monitoring and automatic control systems incorporating the improved imaging devices.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: November 6, 2012
    Assignee: Gentex Corporation
    Inventors: Jon H. Bechtel, Jeremy C. Andrus
  • Patent number: 8301681
    Abstract: A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: October 30, 2012
    Assignee: Altera Corporation
    Inventors: Kwan Yee Martin Lee, Martin Langhammer, Triet M. Nguyen, Yi-Wen Lin
  • Patent number: 8095586
    Abstract: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result res0 of precision greater than precision P1; rounding positive result res0 to precision P1 to the nearest away, producing positive result res1; and rounding the result res1 to precision P2 to the nearest away, where P2 is narrower than P1, producing result res2. The embodiments may also include correcting res2 for double rounding errors. The correcting may include determining that res1 is midway between two consecutive floating point numbers of precision P2, the larger being res2, determining that rounding res0 to produce res1 involved rounding up, and decrementing the significand of res2 to obtain the corrected result.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 10, 2012
    Assignee: Intel Corporation
    Inventor: Marius Cornea-Hasegan
  • Patent number: 8069199
    Abstract: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result res0 of precision greater than precision P1; rounding positive result res0 to precision P1 to the nearest even, producing positive result res1; and rounding the result res1 to precision P2 to the nearest even, where P2 is narrower than P1, producing result res2. The embodiments may also include correcting res2 for double rounding errors. The correcting may include determining that res1 is midway between two consecutive floating point numbers of precision P1, the larger (smaller) being res2, determining that rounding res0 to produce res1 involved rounding up (down), and decrementing (incrementing) the significand of res2 to obtain the corrected result res2?.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventor: Marius Cornea-Hasegan
  • Patent number: 8015230
    Abstract: In one embodiment, a state determiner comprises a plurality of logic circuits and a second logic circuit. Each logic circuit corresponds to a respective bit position of a result of an adder. A first logic circuit corresponds to a least significant bit of the result and is coupled to receive a least significant bit of each operand of the adder and a carry-in input to the adder. Each remaining logic circuit is coupled to receive a bit from the respective bit position of each operand and a less significant bit adjacent to the bit of each operand. Each logic circuit generates an output signal indicative of whether or not a specific result occurs in the respective bit position of the result. Coupled to receive the output signals second logic circuit is configured to generate a sum signal indicative, when asserted, that the specific result occurs.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: September 6, 2011
    Assignee: Apple Inc.
    Inventor: Honkai Tam
  • Patent number: 8005210
    Abstract: Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: August 23, 2011
    Assignee: Intel Corporation
    Inventors: Erdinc Ozturk, Vinodh Gopal, Gilbert Wolrich, Wajdi K. Feghali
  • Patent number: 7986779
    Abstract: Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: Erdinc Ozturk, Vinodh Gopal, Gilbert Wolrich, Wajdi K. Feghali
  • Patent number: 7978846
    Abstract: The computation time to perform scalar point multiplication in an Elliptic Curve Group is reduced by modifying the Barrett Reduction technique. Computations are performed using an N-bit scaled modulus based a modulus m having k-bits to provide a scaled result, with N being greater than k. The N-bit scaled result is reduced to a k-bit result using a pre-computed N-bit scaled reduction parameter in an optimal manner avoiding shifting/aligning operations for any arbitrary values of k, N.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: July 12, 2011
    Assignee: Intel Corporation
    Inventors: Erdinc Ozturk, Vinodh Gopal, Gilbert Wolrich, Wajdi K. Feghali
  • Patent number: 7953784
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh, Michael Frederic Cowlishaw
  • Publication number: 20100030834
    Abstract: To perform a binary-coded decimal (BCD) calculation, a processor receives values on which the BCD calculation is to be performed. A carry resulting from the BCD calculation is stored in a flag register of the processor, and the carry stored in the flag register is used to compute a result of the BCD calculation.
    Type: Application
    Filed: September 22, 2008
    Publication date: February 4, 2010
    Inventor: Cyrille de Brebisson
  • Patent number: 7606848
    Abstract: One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more detectors that are configured to receive a portion of the input vector. The detector is further configured to perform detections on this portion of the input vector in parallel with the logical operation. Methods described herein include identifying a portion of the input vector, wherein the portion of the input vector appears an output of the logic component, and analyzing the portion of the vector in parallel with a logical operation performed by the logic component.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventor: Itay Admon
  • Publication number: 20090172506
    Abstract: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient that is based on the switching signal, a second calculation unit performing an operation on an output of the first calculation unit in accordance with a second coefficient that is based on the switching signal, a selection unit selecting one of the output of the first calculation unit and an output of the second calculation unit based on the switching signal, and a third calculation unit selecting one or both of the input signal and the output of the first calculation unit based on the switching signal and performing a predetermined calculation on the selected signal.
    Type: Application
    Filed: December 24, 2008
    Publication date: July 2, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Noboru YONEOKA, Hirofumi Nagaoka
  • Publication number: 20090006687
    Abstract: Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.
    Type: Application
    Filed: June 25, 2008
    Publication date: January 1, 2009
    Applicant: Elpida Memory, Inc.
    Inventor: Tomoyuki Shibata
  • Patent number: 7444367
    Abstract: A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating point operands and provides an indication of one or more predetermined formats in which the plurality of floating point operands are represented. The result assembler receives the indication from the analysis circuit and assembles an accumulated result that represents a value and combines the encoded status flag information from at least two of the plurality of floating point operands.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: October 28, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Patent number: 7430576
    Abstract: A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the square root of the first floating point operand and a resulting status embedded within the resulting floating point operand.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 30, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Patent number: 7395297
    Abstract: A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure includes a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: July 1, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Patent number: 7069289
    Abstract: A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 27, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Patent number: 7062633
    Abstract: It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision means 109 whether or not the state flag satisfies a condition for performing the arithmetic. A control means 110 controls whether an ALU 100 should perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mana Hamada, Shunichi Kuromaru, Tomonori Yonezawa, Tsuyoshi Nakamura
  • Patent number: 7058678
    Abstract: An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating on a first lower portion of the first binary number and a second lower portion of the second binary number to produce a first result and a carry out signal; and a second ALU operating on a first upper portion of the first binary number and a second upper portion of the second binary number to produce a second result; wherein at least a portion of the pipelined circuit stalls in response to the carry out signal. Another embodiment includes memory comprising a plurality of words, each word comprising data bits and a flag bit indicating a predetermined number of the most significant data bits are all zero.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: June 6, 2006
    Assignee: International Business Machines Corporation
    Inventor: David Arnold Luick
  • Patent number: 7047272
    Abstract: An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder 470 connected to the partial production reduction tree. Unbiased rounding logic 476 is provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signal 477 which is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jean-Pierre Giacalone, Anne Lombardot, Francois Theodorou
  • Patent number: 7016928
    Abstract: A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: March 21, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Patent number: 7010562
    Abstract: An arithmetic circuit includes an arithmetic circuit performing an arithmetic operation of a predetermined bit width in accordance with an arithmetic instruction, a holding circuit storing status information about the arithmetic operation by the arithmetic circuit and a logic circuit having a function of a logic operation. The logic circuit receives the status information stored in the holding circuit and the status information about a present result of arithmetic operation. The arithmetic circuit further includes a selector for selecting either the status information about the present result of arithmetic operation or a signal outputted form the logic circuit in accordance with a control signal based on the arithmetic instruction. The selector supplies the selected signal to the holding circuit.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: March 7, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tomomi Miyano
  • Patent number: 7003543
    Abstract: The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing the ALU mathematical operation. The result may comprise a series of results, each result produced by an ALU mathematical operation instruction executed to perform the ALU mathematical operation. Indicating a status affected by the performance of the ALU mathematical operation instruction further includes determining whether the ALU mathematical operation instruction corresponds to an ALU mathematical operation instruction with carry as well as determining whether the result is a non-zero value. The status bit maintains a value of zero upon the production of a non-zero value until an ALU mathematical operation instruction without carry is determined.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: February 21, 2006
    Assignee: Microchip Technology Incorporated
    Inventor: John Elliott
  • Patent number: 6986023
    Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: January 10, 2006
    Assignee: Intel Corporation
    Inventors: Nigel C. Paver, William T. Maghielse, Wing K. Yu, Jianwei Liu, Anthony Jebson, Kailesh B. Bavaria, Rupal M. Parikh, Deli Deng, Mukesh Patel, Mark Fullerton, Murli Ganeshan, Stephen J. Strazdus
  • Patent number: 6970898
    Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 29, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Guy L. Steele, Jr.
  • Patent number: 6912560
    Abstract: An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at least one of the stages and is operative to generate an overflow flag for the adder substantially in parallel with the generation of the sum output signal and the primary carry-output signal of the adder. Advantageously, the invention substantially reduces the computational delay associated with generation of the overflow flag, relative to that of conventional adders, without requiring an increase in transistor count or circuit area.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 28, 2005
    Assignee: Agere Systems, Inc.
    Inventor: Alexander Goldovsky
  • Patent number: 6836147
    Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: December 28, 2004
    Assignee: NEC Corporation
    Inventor: Shogo Nakaya
  • Patent number: 6819971
    Abstract: A bit manipulation unit (BMU) scales and formats data and includes fast computation of the overflow flag. For fast computation the BMU's overflow flag is computed based on the input data and the shift amount. The overflow flag is calculated separately as either a LMVleft for an arithmetic shift left operation or LMVright for an arithmetic shift right operation. For an arithmetic shift left operation, LMVleft may be computed by first adding one plus the number of guard bits in the input data to the shift amount, and then detecting the number of redundant sign bits. For an arithmetic shift right operation, LMVright may be computed by checking the input redundant sign bits plus the right shift amount. By computing the overflow flag separately as LMVleft and LMVright for arithmetic left and right shifts, respectively, the overflow flag LMV is determined in parallel with the barrel shift operation and so does not depend on the result from the barrel shift operation.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: November 16, 2004
    Assignee: Agere Systems Inc.
    Inventors: Mazhar M. Alidina, Alexander Goldovsky
  • Patent number: 6742013
    Abstract: Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly such that it represents the result of the whole multi-word subtraction until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: May 25, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert Griesemer
  • Publication number: 20040078413
    Abstract: A computer device includes a computer processing circuit and a software development circuit. The computer processing circuit includes a first computing component and a first command control component, the first computing component performs calculations in accordance with a first control signal and the first control signal is generated by the first command control component based on a first program. The software development and support circuit includes a second computing component and a second command control component, the second computing component calculates in accordance with a second control signal and the second command control component generates the second control signal based on a second program. The software development and support circuit receives information of computing status of the computer processing circuit as numerical data, and the second computing component processes the numerical data responsive to the said second control signal.
    Type: Application
    Filed: January 22, 2003
    Publication date: April 22, 2004
    Inventors: Takeshi Yoshimoto, Toshiyuki Furusawa
  • Patent number: 6718459
    Abstract: A numerical arithmetic circuit 50 executes an arithmetic instruction according to an instruction read out of a program memory 10 and then stores the arithmetic result into a register group 40 via an input switcher 70. A mode register 20 is associated with the register group 40. A flag designating whether or not a predetermined logic operation is executed to the arithmetic result is set to the mode register 20. When the register group 40 stores the arithmetic result, the mode register 20 corresponding to the register being the register group 40 designated on the program is referred as a register which stores the arithmetic result. Thus, a predetermined arithmetic and logic operation to the arithmetic result is controlled.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: April 6, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Satoshi Chiba