Abstract: Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectable bias, a reduced precision signal, having minimized or eliminated rounding error, is generated. The selectable bias corresponds to a predetermined characteristic of one of bias, an error signal, the input datum, the reduced precision datum, and a combination thereof.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

Abstract: A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one (“1”) is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed operand is denormalized and providing characteristic bits. A rounding bit is generated based on the characteristic bits. The rounding bit is merged with the denormalized operand to generate the rounded result operand.

Abstract: A digital signal processor having an ALU and accumulating register small in bit number. The digital signal processor adds r-bit rounding bits to an N-bit data(wherein r<N) and adds g-bit guard bits to the high-order bits of the data using bit alignment units each being implemented with a wiring, when N bit data is processed. The data added by the guard bits and the rounding bits is operated by means of the accumulator. The operated data is selectively rounded by a rounding processor. Also, the selectively rounded data is selectively saturated by a saturation processor.

Abstract: An improved method and apparatus for saturation detection in floating point to integer conversions is described. A floating point number is tested for saturation conditions based on an integer field size. From testing the saturation conditions on the floating point number, the present invention predicts whether a floating point number can be converted into an integer value having the given integer field size, or whether the integer field would be saturated. In one embodiment, the saturation conditions are tested on the floating point number in parallel with a floating point to integer conversion.

Abstract: A multiplication method and a multiplication circuit, wherein a multiplicand is multiplied by a multiplier using a multiplication process, the result of the multiplication is added by an addition process to a rounding signal to be output from a rounding signal generation process, and the result of the addition, i.e., a multiplication result obtained after rounding, is stored in a register. By a barrel shifter, the multiplication result obtained after rounding stored in the register is shifted by a bit count indicated by a shift bit count signal. The shift bit count signal output from an instruction control process is input to the barrel shifter and a rounding signal generation process. The rounding signal generation process generates a rounding signal on the basis of the shift bit count signal indicating the bit count used to shift the multiplication result after rounding.

Abstract: A scaling multiplier circuit in accordance with the invention includes a multiplier circuit, a carry calculation circuit, a logic circuit, and an adder circuit. The multiplier circuit produces a 16-bit product of two 8-bit input numbers. The 16-bit product has bits m(15:0). The carry calculation circuit produces a first carryout bit from a sum of a first number consisting of bits m(6:0), a second number consisting of bits m(14:8), and a third number consisting of bit m(7). The logic circuit produces intermediate carryout bits from a sum of bit m(7m), m(15), the first carryout bit, and a constant bit having a value of "1". The adder circuit produces the actual scaled product by summing the intermediate carryout bits and a fourth number consisting of bits m(15:8).

Abstract: A method and apparatus for compressing fixed point signals without introducing a bias. Signals are compressed according to a dithered rounding approach wherein signal values are rounded up and rounded down with approximately equal probability, canceling the bias that would otherwise result from the rounding operation. Numerical properties of the input signal are exploited in order to determine whether the signal value should be rounded up or down. Signal compression may, therefore, be introduced at multiple points within a system without accumulating a signal bias and degrading downstream performance. Further, one bit signal compression may be achieved in a particularly efficient fashion with a minimal amount of hardware.

Abstract: A multiplier configured to obtain higher frequencies of exactly rounded results by adding an adjustment constant to intermediate products generated during iterative multiplication operations is disclosed. One such iterative multiplication operation is the Newton-Raphson iteration, which may be utilized by the multiplier to perform reciprocal calculations and reciprocal square root calculations. For each iteration, the results converge toward an infinitely precise result. To improve the frequency of the exactly rounded result, the results of the iterative calculations may be studied for a large number of differing input operands to determine the best suited value for the adjustment constant. The multiplier may also be configured to perform scalar and packed vector multiplication using the same hardware.

Abstract: A numerical processing method on a computer system in which an instruction having at least one operand and a type control is retrieved, and the operand is converted to a precision specified by the type control. The instruction is executed in the precision specified by the type control to obtain a result, and when the destination precision differs from the precision specified by the type control, the result is converted to the destination precision using a second instruction.

Abstract: A processor contains a storage area for a dynamic rounding mode control value, and a circuit coupled to the storage area configured to execute an instruction using a rounding mode. When the instruction is a first predetermined instruction, a first predetermined rounding mode is used during execution of the instruction. When the instruction is not the first predetermined instruction and the rounding mode specified by the instruction is not a dynamic override, the circuit executes the instruction using a rounding mode specified by the instruction. When the instruction is not the first predetermined instruction and the rounding mode specified by the instruction is the dynamic override, the circuit executes the instruction using a rounding mode specified by the dynamic rounding mode control value.

Abstract: An interface circuit performs a last step of an arithmetic operation and a round operation in parallel. The interface circuit includes a first adder circuit that receives as an input a true result of an arithmetic operation in an intermediate format. The first adder circuit outputs both the true result in a final format and a first representable number approximating the true result. A second adder circuit is connected in parallel to the first adder circuit. The second adder circuit receives the true result in the intermediate format and a 1 as inputs. The second adder circuit outputs a second representable number approximating the true result. The interface circuit also includes a selection circuit connected to the outputs of the first and second adder circuits. The selection circuit outputs either the first or second representable numbers as a rounded result of the arithmetic operation.

Abstract: A method and apparatus for performing rounding in a data processor (10). In one embodiment, two instructions are used to implement a procedure for rounding operands of finite but arbitrary precision. A first instruction "rndp" performs a preliminary rounding operation by analyzing bits which are less significant than the rounding point and updating the values of the round (RND) and sticky (STK) status bits (70, 71) in a defined manner. A second instruction "rnd" performs the rounding of the most significant portion of the operand, using the contents of the RND and STK status bits (70, 71) as determined by the one or more iterations of the "rndp" instruction. By appropriate use of these two instructions, and additional add-with-carry operations, an operand of any length may be rounded at an arbitrary point using a data processor (10) with fixed width registers (40) and a fixed width ALU (30).

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product.

Abstract: An arithmetic logic unit (30) for a digital signal processor (DSP) contains circuitry for preshifting (46, 48) and prerounding (54) the 2's-complement fractional input operands (32, 34) before they are used by a carry look-ahead adder (56). The preshifting (46, 48) provides for efficient divide-by-2 and divide-by-4 functionality and reduces early overflow. Concurrent preshifting (46, 48) and prerounding (54) improve the critical path timing in the carry look-ahead adder (56).

Abstract: In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed, the setting of the truncation indicator is inhibited under certain conditions to facilitate later handling of the result. Determinations are made as to whether the result and truncation fields of the result word are zero and as to whether the overflow field is non-zero. If the result and truncation fields are zero, the setting of the truncation indicator is inhibited notwithstanding a non-zero value in the overflow field. Break point position information is processed to obtain masks of bits having logic "1" values for testing the result and truncation fields and logic "0" values for testing the overflow field, the masks then being logically ANDed with the result word. If the result of the ANDing process is a logic "0", the truncation indicator is inhibited from being set.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of the floating point adder. The leading zero anticipator outputs a control signal to a shifter to shift the sum of the significand adder to eliminate the leading zeros. The number of leading zeros is also provided to an exponent circuit that reduces the magnitude of the exponent to reflect the shifted significand. The leading zero anticipator includes a pattern generator that outputs an intermediate pattern with a number of leading zeros approximately equal to the number of leading zeros in the sum. A counter circuit counts the number of leading zeros and provides one or more one-hot control signals to the shifter. In one embodiment, the significand shifter implements two stages of one-hot multiplexers to provide the desired shift.

Abstract: In the case that the bit width of a high-speed internal calculation of CPU or DSP is restricted and the high-speed internal calculation is performed as a fixed-point calculation, and the bit width of the input data of CPU or DSP is different from the bit width of the high-speed internal calculation, the input digital signal is truncated prior to the internal calculation. After the high-speed internal calculation has completed (at step S2-3), the result of the high-speed internal calculation is shifted in the direction reverse to that of the truncation by a predetermined bit width (at step S2-4). Thus, the gain of the output signal of the CPU or DSP is prevented from decreasing while performing the high-speed internal calculation.