All Four Basic Functions Patents (Class 708/604)
  • Patent number: 11206146
    Abstract: An equivalent circuit architecture and attendant methods for generating a physically unclonable function (PUF) response include a plurality of devices capable of generating a voltage output, a voltage source, and a microcontroller adapted to receive the voltage output from each device of the plurality of devices. The devices may be energy harvesting devices or sensors. The microcontroller is configured to determine an average peak voltage for predefined groups of the plurality of devices, to compare summation voltage values for the predefined groups, and from that information to output response values defining a 128-bit PUF response. The microcontroller determines a peak voltage of each device of the plurality of devices an equal number of times to generate the 128 bit PUF response value, this preventing biasing the response towards any individual device or group of devices.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: December 21, 2021
    Assignee: University of Kentucky Research Foundation
    Inventors: Himanshu Thapliyal, Carson Labrado
  • Patent number: 10764026
    Abstract: Methods and circuitry for relatively low-speed bus time stamping and triggering for use in acoustic object and gesture detection and recognition are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that includes a data line and a clock line. The master device generates and controls a clock signal on the clock line and sends a synchronization command over the data line to the slave devices. The master device receives timestamp and/or other information corresponding to events detected at each slave device, such as a detected acoustic wave reflected from an object. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can use the event times to derive positions and gestures associated with detected objects.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 1, 2020
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventor: Bradley Sharpe-Geisler
  • Patent number: 9268973
    Abstract: A sensor output correction circuit includes an analog-to-digital converter configured to receive an input voltage corresponding to a sensor output of a sensor and a reference voltage that are selectively input to the analog-to-digital converter; and an arithmetic unit configured to correct output data, which is output from the analog-to-digital converter when the input voltage is input to the analog-to-digital converter, based on an output value that is output from the analog-to-digital converter when the reference voltage is input to the analog-to-digital converter. The arithmetic unit includes a multiply adder and a non-restoring divider.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: February 23, 2016
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Konosuke Yamamoto, Yoichi Kimura
  • Patent number: 9032008
    Abstract: A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2?+?) where ? is a positive integer number and ? is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2?, respectively, a first unit to divide a dividend by 2?and calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Fuyuta Sato
  • Publication number: 20140207839
    Abstract: A computer system represents numbers as three-dimensional relations, which may be represented as collections of points in three-dimensional space. The three-dimensional representations may use values of +1 and ?1 as complements of each other to overcome limitations of binary representations which use values of 1 and 0 to represent numbers. The computer system may use such three-dimensional relations to perform arithmetic and to factorize numbers.
    Type: Application
    Filed: February 26, 2014
    Publication date: July 24, 2014
    Inventor: Sherwin Han
  • Publication number: 20140101214
    Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.
    Type: Application
    Filed: September 19, 2013
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: KLAUS M. KROENER, CHRISTOPHE J. LAYER, SILVIA M. MUELLER, KERSTIN SCHELM
  • Publication number: 20140019505
    Abstract: An apparatus for estimating a transfer function of at target object having divided systems is disclosed. The apparatus acquires an estimation equation to estimate the transfer function of the target object, and determines, for each arithmetic operation in the estimation equation, whether the arithmetic operation is an addition or a multiplication. For the multiplication, the apparatus performs the multiplication of frequency response characteristics in the frequency domain. For addition, the apparatus converts the frequency response characteristics into time response characteristics, performs the addition of the time response characteristics in the time domain, and reconverts a result of the addition into the frequency domain.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 16, 2014
    Inventors: Yasuhiko MUKAI, Yoshifumi MORITA, Hiroyuki UKAI, Makoto IWASAKI, Hiroyasu OTAKE, Ryo KANO
  • Publication number: 20130218939
    Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.
    Type: Application
    Filed: April 1, 2013
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: KABUSHIKI KAISHA TOSHIBA
  • Patent number: 8161092
    Abstract: System and method for processing symbols in a communication system are disclosed and may include in a processor that receives symbols to be coded for transmission over a wireless medium, grouping elements of an input matrix across a second dimension of the input matrix to form groups of matrix elements while multiplying the input matrix and an input vector. The input vector may include the symbols to be coded for transmission over the wireless medium. The method may also include pre-computing possible permutations of partial results for each of the groups of matrix elements, and assigning the partial results from each of the groups of matrix elements to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: April 17, 2012
    Assignee: Broadcom Corporation
    Inventor: Yung-Hsiang Lee
  • Publication number: 20110153708
    Abstract: A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2?+?) where ? is a positive integer number and ? is a positive integer number other than powers of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2?, respectively, a first unit to divide a dividend by 2? and calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 23, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Fuyuta SATO
  • Publication number: 20100185836
    Abstract: An arithmetic-program conversion apparatus includes: a program storage section storing an arithmetic program describing a circuit by a logical expression including a plurality of input and output variables, and operators; if the expression has three input variables or more, an intermediate-variable generation section generating an intermediate variable for converting the expression into a plurality of binomials including input and output variables; if the intermediate variable is generated, an expression conversion section converting the logical expression into a plurality of binomials including a binomial for obtaining the intermediate variable and a binomial obtaining the output variable from the intermediate variable; if a plurality of binomials are generated, an expression update section updating the stored original expression; a bit-width determination section determining bit widths of the output, input, and intermediate variables of the expression; and a bit-width storage section storing the bit widths
    Type: Application
    Filed: January 19, 2010
    Publication date: July 22, 2010
    Applicant: Sony Corporation
    Inventor: Shota Hasegawa
  • Publication number: 20080263115
    Abstract: An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the processes being defined for a first number of bits determined by the operand word length; a fetch and write unit comprising direct memory access circuitry for fetching a second number of bits of operand data by direct access from an external memory and for writing results to memory, the second number being set by a predetermined memory access width; the second number being smaller than said operand word length, and the direct memory access circuitry being configured to deliver said second number of bits directly to the processing location without aggregation prior to processing.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Applicant: Horizon Semiconductors Ltd.
    Inventors: Tomer Y. Morad, Ami Hazbany
  • Publication number: 20080046497
    Abstract: Systems and methods for a memory structure are described for increasing the throughput of double precision operations. Broadly, the present invention utilizes a novel memory system to process double precision data in a single memory access. In accordance with one embodiment, a method for increasing throughput of arithmetic operations on double precision data by reducing the number of memory accesses comprising: retrieving a double precision value from a memory, wherein the double precision value is comprised of a high word and a low word, wherein the double precision value is retrieved in a single memory access; selecting a word within the double precision value, wherein the portion selected is a single precision value; multiplying the word with a single precision operand to generate a single precision product; adding the product to a double precision operand to produce a double precision result; and forwarding the double precision result back to memory for storage.
    Type: Application
    Filed: August 17, 2007
    Publication date: February 21, 2008
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Yue-Peng Zheng, Ehud Langberg, Wenye Yang