Incrementation/decrementation Patents (Class 708/672)
  • Double incrementing, low overhead, adder
    Patent number: 6199090
    Abstract: A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: March 6, 2001
    Assignee: ATI International SRL
    Inventors: Sanjay Mansingh, Stephen Clark Purcell