Abstract: Method, program and system for code optimization. A sign assignment instruction with identically sized packed decimal format input and output operands is detected where the sign assignment instruction assigns a value of zero to a packed decimal data value input operand having a value of negative zero. If the input operand to the sign assignment instruction does not result from an add or subtract operation, or the value of the input operand is not greater than a value prior to that operation, the possibility that the value of the input operand of the sign assignment instruction is negative zero is checked when the input operand and the output operand have identical addresses. An instruction is generated and inserted for executing the sign assignment instruction only when there is the possibility that the operand value is negative zero.

Abstract: Method, program and system for code optimization. The method includes detecting a sign assignment instruction having an input operand and an output operand identical in size to each other. Analyzing and determining whether a value of the input operand results from an add or subtract operation and if the value is greater than the value prior to the operation. If so then removing the sign assignment instruction on the condition that the input operand and the output operand of the sign assignment instruction have their addresses identical to each other and replacing the sign assignment instruction with a copy instruction for copying the value of the input operand of the sign assignment instruction to a value of the output operand on the condition that the addresses of the input operand and the output operand of the sign assignment instruction are not identical and do not overlap each other.

Abstract: Certain embodiments of the invention may include systems, methods, and apparatus for detecting shifts in redundant sensor signals. According to an example embodiment of the invention, a method is provided for detecting and indicating a shift in redundant sensor signals. The method can include receiving a sensor channel closeness signal for two or more redundant sensors, receiving a spike confidence signal for at least one of the two or more redundant sensors, receiving a spike duration signal for the at least one of the two or more redundant sensors, determining a shift confidence based at least in part on the received sensor channel closeness signal, the received spike confidence signal, and the received spike duration signal, and outputting the shift confidence.

Abstract: An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value.

Abstract: Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit.

Abstract: A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.