Abstract: An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: An amount is divided into equal portions (n) in a manner which eliminates rounding errors or remainders and has repeatable results.

Abstract: Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal indicative of one or more energy parameters of an associated energy utility, including at least a peak demand period or an off-peak demand period. A generated serial number is obtained from an original serial number of the appliance or controller, which is configured for a signal to communicate to the appliance within a population and command the appliance to operate in an energy savings mode and a normal mode at various time periods. The generated serial number (GSN) is used to segregate a total population into segments to provide granularity in assigning DR activations and deactivations based upon the GSN.

Abstract: The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2n<N?2n+1; performing an initialization operation by initializing a constant a to the smallest integer greater than or equal to half of N; performing a first operation by subtracting, when C is greater than or equal to N·a (product of N and a), the value of C by the value of N·a; and performing a second operation by assigning the smallest integer greater than or equal to half of a to the value of a, wherein the value of C is output as the result of modulo operation after the first operation and the second operation are repeated n times. In the first operation, when C is less than N·a, the value of C is unchanged.

Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.

Abstract: Disclosed is a method for factoring integers by squaring computation time. The present invention uses binary numbers to process invert function of multiplication as factorization. Inverse method of integer factorization uses a diamond expansion form to arrange the digit positions of 1-numbers and 0-numbers subtracted from the product number P and its complement number No. The complement number N0 is the difference between the product number P and the square of the whole-1-number 1n2. The square of the whole-1-number 1n2 equals to the number of that first n-1 digits are 1s, followed by n 0s, and ended by 1.

Abstract: Disclosed are methods, apparatus, and computer-readable media for generating output computer code that adds a 64-bit integer to a smaller-length integer having a length of less than 64 bits. Input computer code includes a loop that includes adding a 64-bit integer and a smaller-length integer. Output code is generated that represents the input code in a format such as assembly language or machine code. The output code includes instructions to convert the smaller-length integer to a 64-bit integer, such that the conversion is not performed during each loop execution. The smaller-length integer is converted by subtracting an offset from the 64-bit integer, adding the offset to the smaller-length integer, and zero-extending the smaller-length integer. The offset is determined based on the length of the smaller-length integer. The output code preserves the integer semantics of the smaller-length integer as required by the input code.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point additions and/or decimal fixed-point additions may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding addition results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits of a predetermined digit unit in plurality of memory areas; calculation-instruction memory section which stores calculation instruction having the number of calculation digits and type of calculation set therein; and decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation resul

Abstract: A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and aligns significands associated with the floating-point numbers such that exponents associated with the floating-point numbers have equal values. The decimal-floating-point adder further includes a binary adder that adds the aligned significands. The floating-point adder includes a correction unit and an output conversion unit to produce a final resultant decimal floating-point number. The decimal floating-point adder may be pipelined so that complete resultant decimal floating-point numbers may be output each clock cycle.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: A method of labelling an article, including a) choosing a first character string comprising an identification number chosen to represent an article or a given class of articles, the character string comprising two or more characters, b) expressing each character in said character string as a binary number having seven or more binary digits, c) storing a sequence of binary numbers corresponding to said character string in a data store, and d) attaching the data store to, or incorporating the data store in, an article. The sequence of binary numbers is preferably generated by multiplication of the identification number by an integer, followed by conversion of the resultant number into a base 84 number. The data store preferably comprises anisotropic magnetic particles having a permanent non-random orientation in predetermined spaced regions.