Abstract: A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

Abstract: This specification describes technologies relating to detecting anomalous user accounts. A computer implemented method is disclosed which evaluates an unknown status user account. The method described compares features associated with a plurality of known anomalous user accounts stored in a database to features present in the unknown account. A correlation value corresponding to the probability of a specific feature occurring in a particular anomalous user account is calculated and a dependence value corresponding to the degree of dependence between the given feature and at least one other feature is also calculated. A subset of features in the unknown account is generated comprising those features that possess a correlation value less than a threshold value and a dependence value below a maximum correlation value. A risk score for the unknown account is calculated by selecting those features from the subset that maximizes the correlation value.

Abstract: A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors.

Abstract: A method and system for binary to binary coded decimal (BCD) conversion. The conversion includes: obtaining a binary input vector; generating, by a binary/BCD hardware converter, a plurality of BCD vectors based on the binary input vector; and calculating a BCD output vector based on the plurality of BCD vectors.

Abstract: Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.

Abstract: An overall processing time to rasterize, at the first device, the electronic document to be rendered is computed. Also, a rendering time to render, at the first device, the electronic document to be rendered is computed. When the overall processing time to rasterize at the first device is greater than the rendering time to render at the first device, the electronic document to be rendered is parsed into a first document and sub-documents. A productivity capacity of each node is determined, the productivity capacity being a measured of the processing power of the node and the communication cost of exchanging information between the first device and the node. A sub-document is rasterized at a node when a productivity capacity of the node reduces the processing time to rasterize the electronic document to be rendered to be less than the computed overall processing time.

Abstract: Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.

Abstract: The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of 4-bits each, computes an intermediate sum vector and carry vector without considering the input carry bit, and also computes propagation and generate functions for each 4-bit group. The second stage is a carry look ahead circuit which computes all carries from the input carry, and the propagate and generate functions of the 4-bit groups from the first stage. The third stage adjusts the intermediate sum vector with pre-correction factors which depend upon the input carry and the carries generated from the second stage and the carry vectors from the first stage.

Abstract: The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of 4-bits each, computes an intermediate sum vector and carry vector without considering the input carry bit, and also computes propagation and generate functions for each 4-bit group. The second stage is a carry look ahead circuit which computes all carries from the input carry, and the propagate and generate functions of the 4-bit groups from the first stage. The third stage adjusts the intermediate sum vector with pre-correction factors which depend upon the input carry and the carries generated from the second stage and the carry vectors from the first stage.