Abstract: According to the present disclosure, a passband filter is provided. The passband filter comprises a first connection, a second connection, and a third connection. One or more resonators of a first type are provided connected in series between the first connection and the second connection; and one or more resonators of a second type are provided connected from between the first connection and the second connection to the third connection. A radio-frequency front end module and wireless mobile device are also provided.

Abstract: A system and method for multi-band digital pre-distortion (DPD) for a non-linear system. The system includes a DPD circuitry configured to perform multi-band DPD on a multi-band input signal to compensate for a non-linearity of a non-linear system. The multi-band input signal includes input signals of multiple frequency bands and the DPD circuitry is configured to perform DPD on an input signal of each frequency band per frequency band. The DPD circuitry is configured to perform the DPD using a combination of a look-up table (LUT) that evaluates a non-linear function and computation of terms of a non-linear polynomial of one or more variables representing the input signals of multiple frequency bands. Both the non-linear function and the non-linear polynomial are in a reduced dimension lower than a dimension of the multi-band input signal.

Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g.

Abstract: A noise suppressor includes a first differential-mode transmission module, a second differential-mode transmission module and a common-mode absorption module. The first and second differential-mode transmission modules are configured to receive a differential signal at one of the first and second differential-mode transmission modules, and output the differential signal at the other of the same. The common-mode absorption module is electrically connected to a reference node, and is configured to absorb common-mode noise of the differential signal from at least one of the first differential-mode transmission module or the second differential-mode transmission module.

Abstract: A general design method for phasor estimation algorithms on different applications is described based on a complex finite impulse response (FIR) band-pass filter. To facilitate the design of the complex band-pass filter for different requirements and reduce the trial and error process, a design framework based on the error mathematical models is described. Using an absolute value inequality theorem, the general error models between the filter gain and the error limitations of all the valuables measured by phasor measurement units (PMUs) are established separately. The filter design criteria obtained by the error models can determine the passband and stopband gain range of complex band-pass filters.

Abstract: A receiving circuit and method for increasing bandwidth are provided. The receiving circuit includes a linear equalizer circuit and a variable gain amplifier. The linear equalizer circuit includes a first negative impedance converter, to generate a first capacitance. The variable gain amplifier is coupled to the linear equalizer circuit. The variable gain amplifier includes a first-stage gain circuit and a feedback circuit. The first-stage gain circuit is coupled to the feedback circuit, and the feedback circuit generates a zero-point at the output end of the first-stage gain circuit.

Abstract: Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Abstract: A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low pass filter is presented. The filter utilizes history capacitor arrays incorporating banks of capacitors. A linear interpolation technique is used in the IIR filter with second order antialiasing filtering, whose transfer function is sinc(x)2 per stage. It also uses a gm cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7th-order charge-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of the filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

Abstract: A multi-input analog-to-digital converter (ADC), i.e., a single ADC, can receive multiple analog input signals and generate multiple digital outputs. To combine multiple analog input signals into a single multi-input ADC, the multi-input ADC would typically include multiple track and hold (T/H) circuits and an adder, which can consume a significant amount of power and incur large cost overhead. An improved approach is to combine multiple inputs through a unique T/H circuit in the front-end of the ADC. The multiple analog input signals can be aggregated using code sequences, without requiring a significant amount of external circuits.

Abstract: To reduce distortion of output analog signals generated at a current-output DA converter. A DA converter that outputs a differential analog signal corresponding to an input digital signal is provided, including: a current output unit outputting a current corresponding to the digital signal to each of first and second wires; a converting unit outputting, as positive-side and negative-side analog signals, voltage signals based on currents flowing through the first and second wires, respectively; a first noise reducing unit having: a first switch switched to be or not to be electrically connected with the first wire; and a first buffer provided between the first switch and a reference potential; and a second noise reducing unit having: a second switch switched to be or not to be electrically connected with the second wire; and a second buffer provided between the second switch and the reference potential.

Abstract: A neural network unit convolves an H×W×C input with F R×S×C filters to generate F Q×P outputs. N processing units (PU) each have a register receiving a respective word of an N-word row of a second memory and multiplexed-register selectively receiving a respective word of an N-word row of a first memory or word rotated from an adjacent PU multiplexed-register. H first memory rows hold input blocks of B words each of channels of respective 2-dimensional input row slices. R×S×C second memory rows hold filter blocks of B words each holding P copies of a filter weight. B is the smallest factor of N greater than W. The PU blocks multiply-accumulate input blocks and filter blocks in column-channel-row order; they read a row of input blocks and rotate it around the N PUs while performing multiply-accumulate operations so each PU block receives each input block before reading another row.

Abstract: A frequency response optimization system includes a battery configured to store and discharge electric power, a power inverter configured to control an amount of the electric power stored or discharged from the battery, and a frequency response controller. The frequency response controller includes receiving a regulation signal from an incentive provider, determining statistics of the regulation signal, using the statistics of the regulation signal to generate a frequency response midpoint, and using the frequency response midpoint to determine optimal battery power setpoints for the power inverter. The power inverter is configured to use the optimal battery power setpoints to control the amount of the electric power stored or discharged from the battery.

Abstract: A frequency response controller includes a high level controller configured to receive a regulation signal from an incentive provider, determine statistics of the regulation signal, and use the statistics of the regulation signal to generate a frequency response midpoint. The controller further includes a low level controller configured to use the frequency response midpoint to determine optimal battery power setpoints and use the optimal battery power setpoints to control an amount of electric power stored or discharged from a battery during a frequency response period.

Abstract: A neural network unit convolves a H×W×C input with F R×S×C filters to generate F Q×P outputs. N processing units (PU) each have a register receiving a memory word and a multiplexed-register selectively receiving a memory word or word rotated from an adjacent PU multiplexed-register. The N PUs are logically partitioned as G blocks each of B PUs. The PUs convolve in a column-channel-row order. For each filter column: the N registers read a memory row, each PU multiplies the register and the multiplexed-register to generate a product to accumulate, and the multiplexed-registers are rotated by one; the multiplexed-registers are rotated to align the input blocks with the adjacent PU block. This is performed for each channel. For each filter row, N multiplexed-registers read a memory row for the multiply-accumulations, F column-channel-row-sums are generated and written to the memory, then all steps are performed for each output row.

Abstract: Reflectionless low-pass, high-pass, band-pass, band-stop, all-pass, all-stop, and multi-band filters, as well as a method for designing such filters is disclosed, along with a method of enhancing the performance of such filters through the use of unmatched sub-networks to realize an optimal frequency response, such as the Chebyshev equal-ripple response. These filters preferably function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. The unmatched sub-networks preferably offer additional degrees of freedom by which element values can be assigned to realize improved cutoff sharpness, stop-band rejection, or other measures of performance. The elements of the filter may be physical passive elements, or synthesized with active circuits, potentially realizing even negative element-values for improved performance.

Abstract: According to one aspect of the invention, there is provided a method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising: during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output.

Abstract: A time-domain equalizer includes a delay circuit, a weighting circuit, a controller and a summation circuit. The delay circuit receives an equalized signal and accordingly generates M delayed signals for an equalized signal. The weighting circuit applies an mth weighting of M weightings to an mth delayed signal of the M delayed signals to generate an mth weighted signal. The summation circuit sums up the M weighted signals, according to which the equalized signal is updated. The controller iteratively updates the M weightings according to a vector {right arrow over (e)}n,p=[en,p,1 . . . en,p,M], where the symbol en,p,j is defined as en,p,j=?k(z[k]*z[k?Dp,j]*), the symbol n is an iteration index, k is a sample index, z[k] is a kth sample of the equalized signal, j is an integer index between 1 and M, and Dp,j represents a time delay amount corresponding to a jth delayed signal of the M delayed signals.

Abstract: A discrete time filter, DTF, is described that comprises a summing node; N parallel branches, each branch having a set of input unit sampling capacitances where each unit sampling capacitance is independently selectively coupleable to the summing node; and an output capacitance connected to the summing node. The output capacitance has a value equal to a sum of the sampling capacitances that are to be selectively connected to the summing node; and the discrete time filter further comprises an inductance connected between the summing node and the output capacitance.

Abstract: A method may include determining that values of a plurality of samples of a digital audio signal that are stored in an input buffer exceed a clipping threshold value. The method may further include identifying the plurality of samples that exceed the clipping threshold value as potentially clipped samples of the digital audio signal. In addition, the method may include generating, based on identification of the potentially clipped samples, attenuated samples by uniformly applying a fixed attenuation factor to the potentially clipped samples and to every sample of the digital audio signal included in the input buffer that follows the potentially clipped samples. Further, the method may include generating a plurality of modified attenuated samples by applying interpolation to the attenuated samples that correspond to the potentially clipped samples. The method may also include outputting the attenuated samples and the modified attenuated samples as a modified digital audio signal.

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal.

Abstract: Spectrometers including integrated capacitive detectors are described. An integrated capacitive detector integrates ion current from the collector (220) into a changing voltage. The detector includes a collector configured to receive ions in the spectrometer, a dielectric (228), and a plate (232) arranged in an overlapping configuration with collector on an opposite side of the dielectric. The detector also includes an amplifier (226).

Abstract: The optimal low power complex filter, as a second order complex filter, is based on current amplifiers (CAs) and is utilized to implement a 4th order current-mode filter that can be used for intermediate frequency (IF) applications, such as, for example, low-IF Bluetooth receivers. Fabricated in a standard 0.18 ?m CMOS technology, experimental results show that the present design offers improved characteristics over the existing solutions in terms of power consumption and spurious-free dynamic range (SFDR). The 4th order filter exhibits in-band SFDR of 65.8 dB while consuming only 1 mW.

Abstract: The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

Abstract: The present invention relates to providing high-speed bidirectional communication while maintaining compatibility. When an HDMI® source 71 performs bidirectional IP communication with an HDMI® sink 72 using a CEC line 84 and a signal line 141, a switching control unit 121 controls a switch 133 so that, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a converting unit 131 and, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a receiver 82. When bidirectional communication is performed using only the CEC line 84, the switching control unit 121 controls the switch 133 so that the CEC signal output from the HDMI® source 71 or the receiver 82 is selected.

Abstract: A switched mode assisted linear regulator includes a linear amplifier (LA) and a buck converter configured as a current source. In example embodiments, the buck converter circuit includes a power switch M1 with an M1 body diode (tub), and includes buck turn-off circuitry configured to avoid negative inductor current by controlled switching of the tub to the higher of VIN and a second voltage. For DC-coupled configurations, boost functionality is provided by an LA boost supply, and the tub is switched to the boost supply. For AC-coupled configurations, boost functionality can be provided without boosting the LA supply rail by constraining signal peak-to-peak amplitude to be less than the LA supply voltage (maintaining a DC-average voltage on the AC-coupling capacitor), and the tub is switched to the higher of VIN and VOUT. The buck turn-off circuitry can include zero crossing detection to control M1 tub switches.

Abstract: A digital infinite impulse response filter has a plurality of cascaded filter elements, with each filter element defining a pole of the filter and wherein the poles lie inside a unit circle. The filter elements are configured such that the p of the last filter element is a real number. In one embodiment the poles are arranged as complex conjugate pairs. In another embodiment the real part of the output of each filter element is extracted before being passed to the next filter element. This architecture offers improved idle tone with reduced complexity.

Abstract: A spurious frequency attenuation servo is provided. The spurious frequency attenuation servo includes a first function generator that generates a first signal at a first frequency and at a spurious frequency; a second function generator that generates a second signal in-phase with the first signal and at the spurious frequency; a third function generator that generates a third signal ninety degrees out-of-phase with the first signal and at the spurious frequency; in-phase and quadrature-phase mixers to input a feedback signal and the second and third signals, respectively; in-phase and quadrature-phase error accumulators; an in-phase and quadrature-phase multiplier to multiply an output from the in-phase and quadrature-phase error accumulators with the second and third signals, respectively; and a summing node to sum the first signal with output from the in-phase and quadrature-phase multipliers to form an output signal that is fed back to the in-phase mixer and the quadrature-phase mixer.

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.

Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein.

Abstract: The present invention is an improved linearizer that implements more complex transfer functions to provide the necessary linearization performance with a reasonable amount of signal processing resources. Particularly, the linearizer operates on an analog-to-digital converter and comprises a distortion compensator and one or more factored Volterra compensators, which may include a second-order factored Volterra compensator, a third-order factored Volterra compensator, and additional higher-order factored Volterra compensators. Inclusion of factored Volterra distortion compensators improves linearization processing performance while significantly reducing the computational complexity compared to a traditional Volterra-based compensator.

Abstract: A discrete-time analog filter including multiple storage cells each coupled to common input and output ports and each including at least one of capacitor and at least one switch. Each cell periodically samples an input signal and contributes to an output signal. At least two cells sample the input signal at different frequencies. The cells may be grouped together into one or more filter taps, where each filter tap may have a specified timing delay. Timing signals of a given tap may be non-overlapping phases of a given frequency. Cells may have a fixed or programmable capacitance associated with a corresponding weighting coefficient, and different taps may have different weighting coefficients. Taps may be coupled to implement a negative weighting coefficient. Programmable gain may be implemented with switches or by tap output coupling including sub-filter summing arrangements. Self-timed cells based on a master clock are disclosed.

Abstract: A system for estimating clock frequency offset and sampling clock offset in a communication system is provided. A receiver is configured to receive a communication signal having been transmitted from a transmitter via a communication channel. The receiver has a signal processor, wherein the signal processor is configured to generate an estimate of a carrier frequency offset and an estimate of a sampling clock offset from the received communication signal by: extracting a vector of pilot symbols from the received signal; performing equalization on the pilot symbols; performing clock frequency offset and sampling clock offset compensation on the pilot symbols; generating the estimate of a carrier frequency offset by estimating a common phase rotation using a first Taylor series approximation; and generating the estimate of the sampling clock offset by estimating phase differences between pairs of pilot symbols using a second Taylor series approximation.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: A system is provided to perform non-recursive signal processing using a sampled data technique and a parallel network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals to obtain analog-valued samples. These samples are collected into data blocks that are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using the parallel network to produce a processed analog output signal. Each individual processing path of the parallel network processes a specific data block of the set of data blocks. The number of parallel processing paths is the same as one plus the degree of the polynomial representing the desired or overall input/output equation characterizing the non-recursive signal processing.

Abstract: Provided is an apparatus and method for analyzing identification (ID) signals by converting radio frequency (RF) signals which are transmitted with an ID signal added thereto by a transmitting part, e.g., a plurality of transmitters or repeaters, into signals of a desired band; creating ID signals that are identical to the ID signals added to the RF signals; calculating correlation values between the converted signals and the created ID signals based on partial correlation; and extracting channel profile of multi-path signals caused by a channel between the transmitting part and the ID signal analyzing apparatus from the correlation value. The technology of the present research is applied to broadcasting and communication.

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: A system including a processor for adjusting the dynamic range of an image including a plurality of pixels. The processor segments the pixels into blocks, and computes statistical values for each block based on intensity values of the pixels. The processor also adjusts the dynamic range of the image by controlling the intensity values of the pixels based on the statistical values.

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.

Abstract: A FIR filter component for a voltage mode driver includes a first node, a second node, and a first switching component comprising a first transistor having a first drain/source, a gate, and a second drain/source, and also a second transistor having a first drain/source, a gate, and a second drain/source. The FIR filter component also includes a first tunable resistor coupled between the first node and a first potential, and a second tunable resistor coupled between the second node and a second potential, wherein the FIR filter component is configured to generate a first output signal at the first output node.

Abstract: A down conversion filter with a plurality of sampling capacitor, wherein at least one sampling capacitor is discharged in sampling phases or charge-summing phases of the other sampling capacitors.

Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal.

Abstract: A broad-band active delay line includes a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell includes a feedback loop and a feedforward path to achieve a high bandwidth.

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.

Abstract: A cost function generator circuit includes memory terms each receiving one or more input signals, and each providing inphase and quadrature output current signals. The inphase and quadrature output currents of the memory terms are summed to provide combined inphase and quadrature output currents, respectively. Transimpedance amplifiers are provided to transform the combined inphase and quadrature output currents into an inphase output voltage and a quadrature output voltage.