Abstract: According to one aspect of an embodiment a learning apparatus includes a first acquiring unit that acquires first output information that is output by an output layer when predetermined input information is input to a model that includes an input layer, a plurality of intermediate layers, and the output layer. The learning apparatus includes a second acquiring unit that acquires intermediate output information that is based on pieces of intermediate information that are output by the plurality of intermediate layers when the input information is input to the model. The learning apparatus includes a learning unit that learns the model based on the first output information and the intermediate output information.

Abstract: Deep neural networks (DNNs) have become very popular in many areas, especially classification and prediction. However, as the number of neurons in the DNN increases to solve more complex problems, the DNN becomes limited by the latency and power consumption of existing hardware. A scalable, ultra-low latency photonic tensor processor can compute DNN layer outputs in a single shot. The processor includes free-space optics that perform passive optical copying and distribution of an input vector and integrated optoelectronics that implement passive weighting and the nonlinearity. An example of this processor classified the MNIST handwritten digit dataset (with an accuracy of 94%, which is close to the 96% ground truth accuracy). The processor can be scaled to perform near-exascale computing before hitting its fundamental throughput limit, which is set by the maximum optical bandwidth before significant loss of classification accuracy (determined experimentally).

Abstract: The purpose of the present invention is to provide an efficient and versatile neural network circuit while significantly reducing the size and cost of the circuit. The neural network circuit comprises: memory cells 1 which are provided in the same number as that of pieces of input data I, and each of which performs a multiplication function by which each piece of input data I consisting of one bit is multiplied by a weighting coefficient W; and a majority determination circuit 2 for performing an addition/application function by which the multiplication results of the memory cells 1 are added up, an activation function is applied to the addition result, and a piece of one-bit output data is outputted.

Abstract: A device configured to implement an artificial intelligence deep neural network includes a first matrix and a second matrix. The first matrix resistive processing unit (“RPU”) array receives a first input vector along the rows of the first matrix RPU. A second matrix RPU array receives a second input vector along the rows of the second matrix RPU. A reference matrix RPU array receives an inverse of the first input vector along the rows of the reference matrix RPU and an inverse of the second input vector along the rows of the reference matrix RPU. A plurality of analog to digital converters are coupled to respective outputs of a plurality of summing junctions that receive respective column outputs of the first matrix RPU array, the second matrix RPU array, and the reference RPU array and provides a digital value of the output of the plurality of summing junctions.

Abstract: A video content matching system includes a computing platform having a hardware processor and a memory storing a software code. When executed, the software code obtains a reference digital profile of a reference video segment, obtains a target digital profile of target video content, and compares the reference and target digital profiles to detect a candidate video segment of the target video content for matching to the reference video segment. The software code also frame aligns reference video frames of the reference video segment with corresponding candidate video frames of the candidate video segment to provide frame aligned video frame pairs, pixel aligns the frame aligned video frame pairs to produce frame and pixel aligned video frame pairs, and identifies, using the frame and pixel aligned video frame pairs, the candidate video segment as a matching video segment or a non-matching video segment for the reference video segment.

Abstract: Input unit to which a voltage is applied, current output unit that outputs a high level current or a low level current in response to the voltage applied to input unit, and stochastic circuit unit that, in response to the voltage applied to input unit, changes a probability that the high level current or the low level current is output from current output unit, in accordance with a sigmoid function used in a mathematical model of a neural activity are included.

Abstract: A computer based on a spiking neural network, includes at least one maximum pooling layer. In response to an input spike received by a neuron of the maximum pooling layer, the device is configured so as to receive the address of the activated synapse. The device comprises an address comparator configured so as to compare the address of the activated synapse with a set of reference addresses. Each reference address is associated with a hardness value and with a pooling neuron. The device activates a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of the set.

Abstract: The vehicle radar apparatus may include a transmitting array antenna configured to radiate radar signals for forward detection, N receiving array antennas configured to receive the radar signals reflected from a target after being radiated from the transmitting array antenna, and a control unit configured to estimate an azimuth of the target by using non-offset receiving array antennas among the N receiving array antennas and estimate an elevation of the target by using a phase difference between an offset receiving array antenna and the non-offset receiving array antenna among the N receiving array antennas and the azimuth of the target.

Abstract: Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p1, p2, . . . , pk} and a second set of values {s1, s2, . . . , sk} that represent a LUT value of s1·2p1+s2·2p2+ . . . +sk·2pk where each value si?{+1,?1} where k?2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p1, p2, . . . , pk} and {s1, s2, . . . , sk} to provide an output sample.

Abstract: A computer implemented method includes updating weight values associated with a plurality of analog synapses in a cross-bar array that implements an artificial neural network by sending a pulse sequence to the analog synapses. Each analog synapse includes a conductance unit, wherein a weight value of the analog synapse is based on a conductance value of the conductance unit. The pulse sequence changes the conductance value. The method further includes comparing the weight values of the analog synapses with target weight values associated with the analog synapses and selecting a set of analog synapses based on the comparison. The method further includes updating the weight values of the selected analog synapses by sending a set of electric pulses of varying durations.

Abstract: Examples described herein relate to apparatuses and methods for a computer simulation platform to solve a computer model, including splitting complex vectors generated for the computer model into real components and imaginary components by generating a first matrix corresponding to real components and a second matric corresponding to imaginary components, generating an appended matrix by appending the first matrix to the second matrix, generating a set of real, orthogonal vectors by running the appended matrix through a residual vector logic, and performing a real arithmetic-based computer simulation solution using the set of real, orthogonal vectors.

Abstract: In an aspect, the present invention provides an optical encryption terminal for generating and distributing a cryptographic key signal in a cryptography key distribution system having at least two optical encryption terminals. The optical encryption terminal comprises an electronic processing unit and the optical encryption terminal is configured to selectively receive optical input signals generated by a source of electromagnetic radiation and optical input signals generated by a further optical encryption terminal, and to selectively output first optical output signals to a detection element and second optical output signals to the further optical encryption terminal, wherein the first optical output signals are based on the optical input signals generated by the further optical encryption terminal and transformed in accordance with an optical encryption pattern provided at the optical encryption terminal.

Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron, a row line extending from the pre-synaptic neuron in a row direction, a post-synaptic neuron, a column line extending from the post-synaptic neuron in a column direction, and a synapse at an intersection region between the row line and the column line. The synapse may include a switching device and a memristor electrically connected with each other in series. The post-synaptic neuron may include a summation circuit, a variable resistor, and a comparator.

Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core comprises a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also comprises a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also comprises an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also comprises a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.

Abstract: A weak binary classifier configured to receive an input signal for classification and generate a classification output is disclosed. The weak binary classifier includes a plurality of weighting amplifier stages, each weighting amplifier stage being configured to receive the input signal for classification and a weighting input derived from a classifier model and generate a weighted input signal, the plurality of weighting amplifier stages being configured to generate a plurality of positive weighted input signals coupled to a positive summing node and a plurality of negative weighted input signals coupled to a negative summing node. The weak binary classifier also includes a comparator having a non-inverting input coupled to the positive summing node and an inverting input coupled to the negative summing node and being configured to generate a weak classification output based on the plurality of weighted input signals.

Abstract: An integrated optical module is provided. The optical module comprises multi optically-coupled channels, and enables the use thereof in an Artificial Neural Network (ANN). According to some embodiments the integrated optical module comprises a multi-core optical fiber, wherein the cores are optically coupled.

Abstract: A neuron device may include an input unit, a synapse unit, and an output unit. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals and may generate an output signal based on the weighted sum.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for augmenting neural networks to generate additional outputs. One of the systems includes a neural network and a sequence processing subsystem, wherein the sequence processing subsystem is configured to perform operations comprising, for each of the system inputs in a sequence of system inputs: receiving the system input; generating an initial neural network input from the system input; causing the neural network to process the initial neural network input to generate an initial neural network output for the system input; and determining, from a first portion of the initial neural network output for the system input, whether or not to cause the neural network to generate one or more additional neural network outputs for the system input.

Abstract: Techniques for designing application or algorithm specific quantum computing circuits for particular applications or algorithms are presented. A design component can comprise an extractor component that can extract qubit pairs determined to satisfy a defined threshold potential of having to use a direct connection between each other in a quantum circuit design based on analysis of an application or algorithm; and a design management component (DMC) that can determine a circuit design of the quantum circuit to use for the application or algorithm based on analysis of characteristics associated with the qubit pairs. DMC can sort the qubit pairs by weighting schemes and the characteristics, comprising the number of affecting downstream qubits, the number of two-qubit gate operations between qubit pairs, and/or whether a qubit pair affects a measurement. Based on the sorting, DMC selects highest ranking qubit pairs to assign a direct connection.

Abstract: A method for data mining on compressed data vectors by a certain metric being expressible as a function of the Euclidean distance is suggested. In a first step, for each compressed data vector, positions and values of such coefficients having the largest energy in the compressed data vector are stored. In a second step, for each compressed data vector, the coefficients having not the largest energy in the compressed data vector are discarded. In a third step, for each compressed data vector, a compression error is determined in dependence on the discarded coefficients in the compressed data vector. In a fourth step, at least one of an upper and a lower bound for the certain metric is retrieved in dependence on the stored positions and the stored values of the coefficients having the largest energy and the determined compression errors.

Abstract: In an embodiment, a quantum circuit (circuit) includes a first qubit and a second qubit. In an embodiment, a quantum circuit includes a tunable microwave resonator, wherein a first applied magnetic flux is configured to tune the microwave resonator to a first frequency, the first frequency configured to activate an interaction between the first qubit and the second qubit, and wherein a second applied magnetic flux is configured to tune the microwave resonator to a second frequency, the second frequency configured to minimize an interaction between the first qubit and the second qubit.

Abstract: In a method for determining positions {pi}i=1, . . . , N of transducers {Ai}i=1, . . . , N of an apparatus, the transducers are assumed to be configured for receiving wave signals from and/or transmitting wave signals to one or more regions {Rm}m=1, . . . , M of interest in an n-dimensional space, with n=2 or 3. An n-dimensional spatial filter function {circumflex over (?)}e(r) is determined, which matches projections {Pm}m=1, . . . , M of the one or more regions {Rm}m=1, . . . , M of interest onto an n?1-dimensional sphere centered on the apparatus. Then, a density function ƒb(p) is obtained, based on a Fourier transform ?(p) of the determined spatial filter function {circumflex over (?)}e(r). Finally, a position pi is determined, within said n-dimensional space, for each of N transducers, based on the obtained density function ƒb(p) and a prescribed number N of the transducers. The invention is further directed to related devices, apparatuses and systems, as well as computer program products.

Abstract: In a method for determining positions {pi}i=1, . . . , N of transducers {Ai}i=1, . . . , N of an apparatus, the transducers are assumed to be configured for receiving wave signals from and/or transmitting wave signals to one or more regions {Rm}m=1, . . . , M of interest in an n-dimensional space, with n=2 or 3. An n-dimensional spatial filter function {circumflex over (?)}e(r) is determined, which matches projections {Pm}m=1, . . . , M of the one or more regions {Rm}m=1 . . . , M of interest onto an n?1-dimensional sphere centered on the apparatus. Then, a density function ƒb(p) is obtained, based on a Fourier transform ?(p) of the determined spatial filter function {circumflex over (?)}e(r). Finally, a position pi is determined, within said n-dimensional space, for each of N transducers, based on the obtained density function ƒb(p) and a prescribed number N of the transducers. The invention is further directed to related devices, apparatuses and systems, as well as computer program products.

Abstract: A biological sample measuring device in which a deposited biological sample is introduced into a capillary, a biological sample measuring sensor in which a reagent and the biological sample provided is mounted, and the biological sample is measured. The biological sample measuring device comprises a mounting portion, a voltage application section, and a detection component. The biological sample measuring sensor is mounted to the mounting portion. The voltage application section applies a measurement voltage to a plurality of electrodes disposed along the capillary. The detection component eliminates the effect of seepage of the biological sample by pass-around at the end of the capillary, or the effect whereby the plasma component seeps into the reagent, and detects the degree to which the biological sample is introduced into the capillary, based on the output result for the voltage applied by the voltage application section to the electrodes.

Abstract: A technique relates to providing a superconducting quantum device. A fixed frequency transmon qubit is provided. A tunable frequency transmon qubit is provided. The fixed frequency transmon qubit is coupled to the tunable frequency transmon qubit to form a single qubit.

Abstract: A method of additive manufacturing of a three-dimensional object is disclosed. The method comprises sequentially forming a plurality of layers each patterned according to the shape of a cross section of the object. In some embodiments, the formation of at least one of the layers comprises performing a raster scan to dispense at least a first building material composition, and a vector scan to dispense at least a second building material composition. The vector scan is optionally along a path selected to form at least one structure selected from the group consisting of (i) an elongated structure, (ii) a boundary structure at least partially surrounding an area filled with the first building material, and (iii) an inter-layer connecting structure.

Abstract: The present invention discloses a digital to analog conversion module, a data drive circuit and a liquid crystal display, wherein the digital to analog conversion module can comprise 2N?1 sub circuits and 2N?1?1 first divider resistors, and each sub circuit comprises a second divider resistor, a first switch circuit and a second switch circuit, wherein the first switch circuit and the second switch circuit are respectively coupled to two ends of the second divider resistor; the first switch circuit comprises N first switch units coupled in series, and the second switch circuit comprises a second switch unit and at least one first switch unit coupled in series; according to a preset order, a control end of the second switch unit is coupled to a connection node of a N?1th and a Nth first switch units; an output end of the second switch unit is coupled to the first switch unit.

Abstract: In one embodiment, a method of generating write data generates write data for a multi charged particle beam writing apparatus. The method includes dividing a polygonal figure included in design data into a plurality of figure segments including trapezoids each having a pair of parallel opposite sides extending in a first direction, the trapezoids being connected in a second direction orthogonal to the first direction such that adjacent trapezoids share the side extending in the first direction as a common side, and generates the write data including position information of a common vertex of a first trapezoid and a second trapezoid next to the first trapezoid expressed by a displacement in the first and second directions from a position of a common vertex of the second trapezoid and a third trapezoid next to the second trapezoid.

Abstract: An apparatus includes a first array including sensors; a second array including sensors that are not collinear with the sensors of the first array except for a sensor that defines the origin of a spatial phase; and a signal processing unit that generates covariance matrices including a first covariance matrix and a second covariance matrix based on reflected waves received by the first and second arrays from targets, estimates first angles of the targets based on the first covariance matrix, reproduces an angle matrix based on the estimated first angles, performs triangular decomposition on the product of a generalized inverse matrix of the angle matrix and the second covariance matrix to obtain a matrix, constructs a similarity transformation problem from submatrices of the obtained matrix, and estimates second angles of the targets based on the estimated first angles and solutions of the similarity transformation problem.

Abstract: A logarithmic conversion circuit comprises: an operation amplifier; an input resistor connected at a preceding stage of an inverting input terminal, of the operation amplifier, to which a current signal is inputted; and a logarithmic conversion device and a current feedback device connected in series between the inverting input terminal and an output terminal of the operation amplifier, and an inverse-logarithmic conversion circuit comprises: a current/voltage conversion circuit which, after the current signal having passed through the current feedback device is inputted, converts the inputted current signal to a voltage value corresponding thereto; and a subtraction circuit outputting the difference between an output voltage of the current/voltage conversion circuit and a predetermined reference voltage, a circuit constant of the subtraction circuit being set such that the difference output of the subtraction circuit has a linearity proportional to the current signal.

Abstract: A global image adjustment, such as dynamic range adjustment is established based on image characteristics. The image adjustment is based more heavily on pixel values in image areas identified as being important by one or more saliency mapping algorithms. In one application to dynamic range adjustment, a saliency map is applied to create a weighed histogram and a transformation is determined from the weighted histogram. Artifacts typical of local adjustment schemes may be avoided.

Abstract: Provided are, among other things, systems, apparatuses methods and techniques for performing multi-bit quantization. One such apparatus includes an input signal line; a first comparator having a first input coupled to the input signal line, a second input coupled to a first reference signal, and an output; a rectifier having an input coupled to the input signal line and also having an output; and a second comparator having a first input coupled to the output of the rectifier, a second input coupled to a second reference signal, and an output, with the first comparator and the second comparator being clocked so as to produce sequences of quantized samples at substantially the same times.

Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

Abstract: The present invention describes systems and methods to provide programmable analog classifiers. An exemplary embodiment of the present invention provides an analog classifier circuit comprising a bump circuit enabled to store a template vector, wherein the template vector can model a probability distribution with exponential behavior. Furthermore, the bump circuit is enabled to generate an output corresponding to a comparison between an input vector received by the bump circuit and the template vector stored by the bump circuit. Additionally, the analog classifier circuit includes a variable gain amplifier in communication with the bump circuit, and the variable gain amplifier can be adjusted to modify the variance of the template vector.

Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.

Abstract: A method is provided for processing received data symbols in an orthogonal frequency division multiplexing (OFDM) transmission scheme, and an OFDM baseband receiver which performs this method, in order to support frequency selective noise estimation, especially in interference limited environments, and to offer improved estimation performance and reduced computational complexity.

Abstract: The present invention relates to an apparatus and method for the encryption and decryption of optically transmitted data, and more particularly to the encryption and decryption of optical data transmitted and received using only optical components. Because only optical components are used, the encryption and decryption is independent of the data rate of the optical signal. The apparatus may include an encryption device that operates by receiving and combining both an unencrypted optical signal as well as a delayed optical signal that is based on the unencrypted optical signal. An optical delay may be configured in a number of different ways and may be used for delaying the unencrypted optical signal. The apparatus may further include a decryption device that receives and combines an encrypted optical signal as well as a delayed optical signal that is based on the encrypted optical signal.

Abstract: An arithmetic circuit includes: an input terminal for receiving an input signal; plural capacitors; and an amplifier circuit including an amplifying input terminal and an output terminal and configured to amplify a signal input from the amplifying input terminal and output it as an output signal from the output terminal. A first switch circuit becomes conductive based on a first control signal and connects the plural capacitors in parallel between the input terminal and a first voltage terminal for supplying a first voltage. A second switch circuit becomes conductive based on a second control signal and connects a first capacitor of the plural capacitors between the amplifying input terminal and a second voltage terminal for supplying a second voltage to form a first current path and a second capacitor of the plural capacitors between the amplifying input terminal and the output terminal to form a second current path.

Abstract: The invention reduces unnecessary electromagnetic radiation noise associated with a step pulse of an output signal. A random number control register is a register for controlling start, standby, stop, timing or the like of output of random number data from a random number generation circuit. Random number data outputted by the random number generation circuit is stored in a rise/fall time variable data register. The data stored in the rise/fall time variable data register is replaced by random number data sequentially generated by the random number generation circuit. An output circuit is a circuit for outputting a signal from an internal circuit of a microcomputer to an external device, and the rise/fall times of the output signal from the output circuit are variably controlled in response to the random number data stored in the rise/fall time variable data register.

Abstract: Methods, systems and apparatus for quasi-adiabatic quantum computation include initializing a quantum processor to a ground state of an initial Hamiltonian and evolving the quantum processor from the initial Hamiltonian to a final Hamiltonian via an evolution Hamiltonian, wherein anti-crossings of the evolution Hamiltonian are passed non-adiabatically.

Abstract: Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number.

Abstract: Schedulability determination method of determining whether real-time scheduling of tasks is possible using processors, includes calculating Lk and ?i=1 . . . NMi*Uk, i, (1?k, i?N; k, i: integer) where Lk corresponds to task-k, Mi represents number of the one or more processors simultaneously used by task-i, Uk, i corresponds to task-k and task-i, and N represents number of tasks, and determining that real-time scheduling of tasks is possible using processors, if tasks all satisfy conditions, ?i=1 . . .

Abstract: A method and apparatus processes signals in a set of analog circuit components of an analog circuit white enforcing a set of explicit constraints corresponding to a set of implicit constraints to reduce errors in output signals.

Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current.

Abstract: A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.

Abstract: Various components of the present invention are collectively designated as Adaptive Real-Time Embodiments for Multivariate Investigation of Signals (ARTEMIS). It is a method, processes, and apparatus for measurement and analysis of variables of different type and origin. In this invention, different features of a variable can be quantified either locally as individual events, or on an arbitrary spatio-temporal scale as scalar fields in properly chosen threshold space. The method proposed herein overcomes limitations of the prior art by directly processing the data in real-time in the analog domain, identifying the events of interest so that continuous digitization and digital processing is not required, performing direct, noise-resistant measurements of salient signal characteristics, and outputting a signal proportional to these characteristics that can be digitized without the need for high-speed front-end sampling. The application areas of ARTEMIS are numerous, e.g.

Abstract: A quantum processing apparatus includes a qubit, a superconducting bus, and a controllable coupling mechanism that controllably couples the superconducting bus to the qubit. The controllable coupling mechanism is characterized by a first state in which the superconducting bus and the qubit are capacitively coupled, thereby permitting a coupling operation to be performed between a quantum device, coupled to the superconducting bus, and the qubit. The controllable coupling mechanism is also characterized by a second state in which the superconducting bus and the qubit are capacitively uncoupled such that the qubit and the quantum device are not coupled to each other.

Abstract: A method for performing a coupling operation between a quantum device and a qubit is provided. The quantum device is coupled to a superconducting bus. The method includes placing a controllable coupling mechanism into a coupled state, thereby coupling the quantum device and the qubit to each other. The quantum device or the qubit is then tuned for a first period of time. Then the controllable coupling mechanism is placed into an uncoupled state, thereby decoupling the quantum device and the qubit from each other.

Abstract: An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.