Particular Function Performed Patents (Class 708/801)
  • Patent number: 10241069
    Abstract: A biological sample measuring device in which a deposited biological sample is introduced into a capillary, a biological sample measuring sensor in which a reagent and the biological sample provided is mounted, and the biological sample is measured. The biological sample measuring device comprises a mounting portion, a voltage application section, and a detection component. The biological sample measuring sensor is mounted to the mounting portion. The voltage application section applies a measurement voltage to a plurality of electrodes disposed along the capillary. The detection component eliminates the effect of seepage of the biological sample by pass-around at the end of the capillary, or the effect whereby the plasma component seeps into the reagent, and detects the degree to which the biological sample is introduced into the capillary, based on the output result for the voltage applied by the voltage application section to the electrodes.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 26, 2019
    Assignee: PHC Holdings Corporation
    Inventors: Eriko Yoshioka, Teppei Shinno, Shouko Hironaka
  • Patent number: 10176432
    Abstract: A technique relates to providing a superconducting quantum device. A fixed frequency transmon qubit is provided. A tunable frequency transmon qubit is provided. The fixed frequency transmon qubit is coupled to the tunable frequency transmon qubit to form a single qubit.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Jay Gambetta, Jared B. Hertzberg, Easwar Magesan
  • Patent number: 10016937
    Abstract: A method of additive manufacturing of a three-dimensional object is disclosed. The method comprises sequentially forming a plurality of layers each patterned according to the shape of a cross section of the object. In some embodiments, the formation of at least one of the layers comprises performing a raster scan to dispense at least a first building material composition, and a vector scan to dispense at least a second building material composition. The vector scan is optionally along a path selected to form at least one structure selected from the group consisting of (i) an elongated structure, (ii) a boundary structure at least partially surrounding an area filled with the first building material, and (iii) an inter-layer connecting structure.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 10, 2018
    Assignee: Stratasys Ltd.
    Inventor: Eduardo Napadensky
  • Patent number: 9978331
    Abstract: The present invention discloses a digital to analog conversion module, a data drive circuit and a liquid crystal display, wherein the digital to analog conversion module can comprise 2N?1 sub circuits and 2N?1?1 first divider resistors, and each sub circuit comprises a second divider resistor, a first switch circuit and a second switch circuit, wherein the first switch circuit and the second switch circuit are respectively coupled to two ends of the second divider resistor; the first switch circuit comprises N first switch units coupled in series, and the second switch circuit comprises a second switch unit and at least one first switch unit coupled in series; according to a preset order, a control end of the second switch unit is coupled to a connection node of a N?1th and a Nth first switch units; an output end of the second switch unit is coupled to the first switch unit.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 22, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Dongsheng Guo, Mingliang Wang
  • Patent number: 9558315
    Abstract: In one embodiment, a method of generating write data generates write data for a multi charged particle beam writing apparatus. The method includes dividing a polygonal figure included in design data into a plurality of figure segments including trapezoids each having a pair of parallel opposite sides extending in a first direction, the trapezoids being connected in a second direction orthogonal to the first direction such that adjacent trapezoids share the side extending in the first direction as a common side, and generates the write data including position information of a common vertex of a first trapezoid and a second trapezoid next to the first trapezoid expressed by a displacement in the first and second directions from a position of a common vertex of the second trapezoid and a third trapezoid next to the second trapezoid.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: January 31, 2017
    Assignee: NuFlare Technology, Inc.
    Inventors: Kenichi Yasui, Shigehiro Hara
  • Patent number: 9507018
    Abstract: An apparatus includes a first array including sensors; a second array including sensors that are not collinear with the sensors of the first array except for a sensor that defines the origin of a spatial phase; and a signal processing unit that generates covariance matrices including a first covariance matrix and a second covariance matrix based on reflected waves received by the first and second arrays from targets, estimates first angles of the targets based on the first covariance matrix, reproduces an angle matrix based on the estimated first angles, performs triangular decomposition on the product of a generalized inverse matrix of the angle matrix and the second covariance matrix to obtain a matrix, constructs a similarity transformation problem from submatrices of the obtained matrix, and estimates second angles of the targets based on the estimated first angles and solutions of the similarity transformation problem.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Kazuo Shirakawa
  • Patent number: 8972474
    Abstract: A logarithmic conversion circuit comprises: an operation amplifier; an input resistor connected at a preceding stage of an inverting input terminal, of the operation amplifier, to which a current signal is inputted; and a logarithmic conversion device and a current feedback device connected in series between the inverting input terminal and an output terminal of the operation amplifier, and an inverse-logarithmic conversion circuit comprises: a current/voltage conversion circuit which, after the current signal having passed through the current feedback device is inputted, converts the inputted current signal to a voltage value corresponding thereto; and a subtraction circuit outputting the difference between an output voltage of the current/voltage conversion circuit and a predetermined reference voltage, a circuit constant of the subtraction circuit being set such that the difference output of the subtraction circuit has a linearity proportional to the current signal.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 3, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Toshimitsu Nakai
  • Patent number: 8907971
    Abstract: A global image adjustment, such as dynamic range adjustment is established based on image characteristics. The image adjustment is based more heavily on pixel values in image areas identified as being important by one or more saliency mapping algorithms. In one application to dynamic range adjustment, a saliency map is applied to create a weighed histogram and a transformation is determined from the weighted histogram. Artifacts typical of local adjustment schemes may be avoided.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: December 9, 2014
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Anders Ballestad, Gerwin Damberg
  • Patent number: 8819101
    Abstract: Provided are, among other things, systems, apparatuses methods and techniques for performing multi-bit quantization. One such apparatus includes an input signal line; a first comparator having a first input coupled to the input signal line, a second input coupled to a first reference signal, and an output; a rectifier having an input coupled to the input signal line and also having an output; and a second comparator having a first input coupled to the output of the rectifier, a second input coupled to a second reference signal, and an output, with the first comparator and the second comparator being clocked so as to produce sequences of quantized samples at substantially the same times.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 26, 2014
    Assignee: Syntropy Systems, LLC
    Inventor: Christopher Pagnanelli
  • Patent number: 8799346
    Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: David Reynolds, Benjamin Vigoda
  • Patent number: 8688763
    Abstract: The present invention describes systems and methods to provide programmable analog classifiers. An exemplary embodiment of the present invention provides an analog classifier circuit comprising a bump circuit enabled to store a template vector, wherein the template vector can model a probability distribution with exponential behavior. Furthermore, the bump circuit is enabled to generate an output corresponding to a comparison between an input vector received by the bump circuit and the template vector stored by the bump circuit. Additionally, the analog classifier circuit includes a variable gain amplifier in communication with the bump circuit, and the variable gain amplifier can be adjusted to modify the variance of the template vector.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 1, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Sheng-Yu Peng, Paul E. Halser
  • Patent number: 8649508
    Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 11, 2014
    Assignee: Tata Consultancy Services Ltd.
    Inventor: Natarajan Vijayarangan
  • Patent number: 8605841
    Abstract: A method is provided for processing received data symbols in an orthogonal frequency division multiplexing (OFDM) transmission scheme, and an OFDM baseband receiver which performs this method, in order to support frequency selective noise estimation, especially in interference limited environments, and to offer improved estimation performance and reduced computational complexity.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 10, 2013
    Assignee: Intel Mobile Communications Technology Dresden GmbH
    Inventor: Andreas Bury
  • Patent number: 8428259
    Abstract: The present invention relates to an apparatus and method for the encryption and decryption of optically transmitted data, and more particularly to the encryption and decryption of optical data transmitted and received using only optical components. Because only optical components are used, the encryption and decryption is independent of the data rate of the optical signal. The apparatus may include an encryption device that operates by receiving and combining both an unencrypted optical signal as well as a delayed optical signal that is based on the unencrypted optical signal. An optical delay may be configured in a number of different ways and may be used for delaying the unencrypted optical signal. The apparatus may further include a decryption device that receives and combines an encrypted optical signal as well as a delayed optical signal that is based on the encrypted optical signal.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: April 23, 2013
    Assignee: General Dynamics Advanced Information Systems
    Inventor: James P. Waters
  • Publication number: 20120303689
    Abstract: An arithmetic circuit includes: an input terminal for receiving an input signal; plural capacitors; and an amplifier circuit including an amplifying input terminal and an output terminal and configured to amplify a signal input from the amplifying input terminal and output it as an output signal from the output terminal. A first switch circuit becomes conductive based on a first control signal and connects the plural capacitors in parallel between the input terminal and a first voltage terminal for supplying a first voltage. A second switch circuit becomes conductive based on a second control signal and connects a first capacitor of the plural capacitors between the amplifying input terminal and a second voltage terminal for supplying a second voltage to form a first current path and a second capacitor of the plural capacitors between the amplifying input terminal and the output terminal to form a second current path.
    Type: Application
    Filed: March 21, 2012
    Publication date: November 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanori FURUTA, Hirotomo ISHII
  • Patent number: 8316069
    Abstract: The invention reduces unnecessary electromagnetic radiation noise associated with a step pulse of an output signal. A random number control register is a register for controlling start, standby, stop, timing or the like of output of random number data from a random number generation circuit. Random number data outputted by the random number generation circuit is stored in a rise/fall time variable data register. The data stored in the rise/fall time variable data register is replaced by random number data sequentially generated by the random number generation circuit. An output circuit is a circuit for outputting a signal from an internal circuit of a microcomputer to an external device, and the rise/fall times of the output signal from the output circuit are variably controlled in response to the random number data stored in the rise/fall time variable data register.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: November 20, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Hideo Kondo
  • Patent number: 7899852
    Abstract: Methods, systems and apparatus for quasi-adiabatic quantum computation include initializing a quantum processor to a ground state of an initial Hamiltonian and evolving the quantum processor from the initial Hamiltonian to a final Hamiltonian via an evolution Hamiltonian, wherein anti-crossings of the evolution Hamiltonian are passed non-adiabatically.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: March 1, 2011
    Assignee: D-Wave Systems Inc.
    Inventor: Mohammad H. S. Amin
  • Patent number: 7844656
    Abstract: Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: November 30, 2010
    Assignee: D-Wave Systems Inc.
    Inventors: William G. Macready, Johnny Jone Wai Kuan
  • Patent number: 7797703
    Abstract: Schedulability determination method of determining whether real-time scheduling of tasks is possible using processors, includes calculating Lk and ?i=1 . . . NMi*Uk, i, (1?k, i?N; k, i: integer) where Lk corresponds to task-k, Mi represents number of the one or more processors simultaneously used by task-i, Uk, i corresponds to task-k and task-i, and N represents number of tasks, and determining that real-time scheduling of tasks is possible using processors, if tasks all satisfy conditions, ?i=1 . . .
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: September 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Torii, Seiji Maeda
  • Patent number: 7788312
    Abstract: A method and apparatus processes signals in a set of analog circuit components of an analog circuit white enforcing a set of explicit constraints corresponding to a set of implicit constraints to reduce errors in output signals.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 31, 2010
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventor: Benjamin Butterfly William Vigoda
  • Patent number: 7769798
    Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: August 3, 2010
    Inventors: Amir Banihashemi, Saied Hemati
  • Patent number: 7631030
    Abstract: A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: December 8, 2009
    Assignee: Sony Corporation
    Inventor: Masayuki Katakura
  • Patent number: 7617270
    Abstract: Various components of the present invention are collectively designated as Adaptive Real-Time Embodiments for Multivariate Investigation of Signals (ARTEMIS). It is a method, processes, and apparatus for measurement and analysis of variables of different type and origin. In this invention, different features of a variable can be quantified either locally as individual events, or on an arbitrary spatio-temporal scale as scalar fields in properly chosen threshold space. The method proposed herein overcomes limitations of the prior art by directly processing the data in real-time in the analog domain, identifying the events of interest so that continuous digitization and digital processing is not required, performing direct, noise-resistant measurements of salient signal characteristics, and outputting a signal proportional to these characteristics that can be digitized without the need for high-speed front-end sampling. The application areas of ARTEMIS are numerous, e.g.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: November 10, 2009
    Inventor: Alexei V. Nikitin
  • Patent number: 7613765
    Abstract: A quantum processing apparatus includes a qubit, a superconducting bus, and a controllable coupling mechanism that controllably couples the superconducting bus to the qubit. The controllable coupling mechanism is characterized by a first state in which the superconducting bus and the qubit are capacitively coupled, thereby permitting a coupling operation to be performed between a quantum device, coupled to the superconducting bus, and the qubit. The controllable coupling mechanism is also characterized by a second state in which the superconducting bus and the qubit are capacitively uncoupled such that the qubit and the quantum device are not coupled to each other.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: November 3, 2009
    Assignee: D-Wave Systems, Inc.
    Inventors: Jeremy P. Hilton, Yutian Ling
  • Patent number: 7613764
    Abstract: A method for performing a coupling operation between a quantum device and a qubit is provided. The quantum device is coupled to a superconducting bus. The method includes placing a controllable coupling mechanism into a coupled state, thereby coupling the quantum device and the qubit to each other. The quantum device or the qubit is then tuned for a first period of time. Then the controllable coupling mechanism is placed into an uncoupled state, thereby decoupling the quantum device and the qubit from each other.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: November 3, 2009
    Assignee: D-Wave Systems Inc.
    Inventors: Jeremy P. Hilton, Yutian Ling
  • Patent number: 7610326
    Abstract: An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: October 27, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keisuke Korekado, Osamu Nomura, Atsushi Iwata, Takashi Morie
  • Publication number: 20090259709
    Abstract: Various components of the present invention are collectively designated as Adaptive Real-Time Embodiments for Multivariate Investigation of Signals (ARTEMIS). It is a method, processes, and apparatus for measurement and analysis of variables of different type and origin. In this invention, different features of a variable can be quantified either locally as individual events, or on an arbitrary spatio-temporal scale as scalar fields in properly chosen threshold space. The method proposed herein overcomes limitations of the prior art by directly processing the data in real-time in the analog domain, identifying the events of interest so that continuous digitization and digital processing is not required, performing direct, noise-resistant measurements of salient signal characteristics, and outputting a signal proportional to these characteristics that can be digitized without the need for high-speed front-end sampling. The application areas of ARTEMIS are numerous, e.g.
    Type: Application
    Filed: August 7, 2006
    Publication date: October 15, 2009
    Inventor: Alexei V. Nikitin
  • Patent number: 7584238
    Abstract: An analog circuit system for generating output signals whose curve shape, at least sectionally, corresponds or is approximate to an elliptic function. Standard analog components such as adders, integrators, multipliers and differential amplifiers can be interconnected in order to simulate elliptic time functions from the standpoint of circuit engineering.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: September 1, 2009
    Assignee: Deutsche Telekom AG
    Inventor: Klaus Huber
  • Publication number: 20090198759
    Abstract: The present invention provides a set of analog circuit modules and procedures for assembling them into circuits that represent fundamental expressions and operations in mathematics, and more specifically to circuits for performing computations on problems formulated as constraints in Set Theory. In this invention, physical analogues of mathematical sets are realized by the current flowing through electronic circuit devices, or by the voltage across such devices. A circuit assembled from set analogue devices appropriately connected together can generate analogues of the basic operations in Set Theory, such as intersection, union, complement, difference, subset, etc. Using these basic circuit modules, the analogues of arbitrarily complex expressions and operations can be obtained by combination. A complete circuit that is the analogue of Set Theory expressions defining the problem specification can be assembled by requiring the circuit and the Set Theory expressions to have the same topology.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 6, 2009
    Inventor: Robert William Schmieder
  • Patent number: 7546332
    Abstract: Apparatus and methods for implementation of mathematical functions apparatus providing both speed and accuracy. Disclosed are specific circuits and methods of operation thereof that may be used for the purpose of implementing an exponential function, a squaring function, and a cubic function, using the same basic circuit. By applying a desired weighting function on a current source, an output current provides a value that corresponds exactly to the desired mathematical functions at discrete points, and closely tracks values in between the discrete points. The precision is defined by the selection of a voltage reference for the circuit. Various embodiments are disclosed, as well as embodiments implementing other exemplary functions.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: June 9, 2009
    Assignee: Theta Microelectronics, Inc.
    Inventor: Spyridon Vlassis
  • Patent number: 7523154
    Abstract: A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: April 21, 2009
    Assignee: Panasonic Corporation
    Inventors: Hirokuni Fujiyama, Shiro Dosho, Hiroyuki Nakahira, Akira Yamamoto, Hiroki Mouri
  • Patent number: 7493353
    Abstract: A stochastic processor of the present invention includes a fluctuation generator configured to output an analog quantity having a fluctuation, a fluctuation difference calculation means configured to output fluctuation difference data with an output of the fluctuation generator added to analog difference between two data, a thresholding unit configured to perform thresholding on an output of the fluctuation difference calculation means to thereby generate a pulse, and a pulse detection means configured to detect the pulse output from the thresholding unit.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: February 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Michihito Ueda, Kiyoyuki Morita
  • Patent number: 7464131
    Abstract: A logical calculation circuit capable of storing data, and performing logical calculations with high reliability and high speeds are provided. The residual polarized state s? of a load ferroelectric capacitor Cs? is actively changed so that the residual polarized state s? of a load ferroelectric capacitor Cs? is opposite to the residual polarized state s of a storage ferroelectric capacitor Cs. In the case a reference potential is made c=0 in the calculation operation, even if the second data to be calculated x=1 is given to the storage ferroelectric capacitor Cs in the residual polarized state s (the first data to be calculated)=0, the ferroelectric capacitor Cs does not reverse in polarity. Even with combinations other than s=0 and x=1, the ferroelectric capacitor Cs does not reverse in polarity.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: December 9, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Michitaka Kameyama, Takahiro Hanyu, Hiromitsu Kimura, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
  • Patent number: 7461111
    Abstract: A method of uniforming physical random numbers while concurrently maintaining a random number generating rate and ensuring security. The method sequentially inputs a plurality of physical random numbers to a shift register to hold them there, and shifts them every time a reference pulse signal rises. Physical random numbers held in the shift register are randomly selected and output by a selector based on part of them. Accordingly, physical random numbers input to the shift register are uniformed and then output even thought they have a deviation, thereby eliminating the chance of not outputting random numbers or letting others recognize the deviation of random numbers.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: December 2, 2008
    Assignee: FDK Corporation
    Inventors: Hiroyasu Yamamoto, Ananda Vithanage, Takakuni Shimizu, Kaoru Fujita, Hatsumi Nakano, Takaaki Shiga, Ryuji Soga, Masayoshi Katono, Toshiyuki Watanabe, Misako Koibuchi
  • Patent number: 7451174
    Abstract: An analog electronic circuit is proposed that e.g. computes the symbol likelihoods for PAM or QAM signal constellations. The circuit has at least one set of M transistors connected to a common current source. A multiplier/adder generates the voltages to be applied to the transistors from a value y and a set of M expected values in such a way that the currents through the transistors correspond to the likelihood that the value y corresponds to the expected values. The circuit can be used for signal demodulation and various other applications.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: November 11, 2008
    Assignee: Anadec GmbH
    Inventors: Hans-Andrea Loeliger, Matthias Urs Frey, Patrick Peter Merkli
  • Publication number: 20080172438
    Abstract: A figure data verification apparatus includes an operation part configured to input design data and writing data converted from the design data and perform an exclusive OR operation between data of a figure included in the design data and data of a figure included in the writing data, a sorting part configured to sort figures produced as a result of the exclusive OR operation to at least one arbitrary-angle figure having at least one angle not being an integral multiple of 45 degrees and to at least one non-arbitrary-angle figure all angles of which are integral multiples of 45 degrees, a first removal part configured to remove a figure of a size smaller than a first allowable error value from the arbitrary-angle figure, and a second removal part configured to remove a figure of a size smaller than a second allowable error value from the non-arbitrary-angle figure.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 17, 2008
    Applicant: NuFlare Technology, Inc.
    Inventors: Jun KASAHARA, Shigehiro HARA, Shinji SAKAMOTO
  • Patent number: 7401108
    Abstract: A random noise signal generator circuit comprising a random noise source that produces a random noise signal, an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal, a feedback loop having a DC offset correction circuit, and a summer. The DC offset correction circuit processes a fed back portion of the amplified random noise signal to produce a DC offset correction signal. The summer sums the random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal. The summer is electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry. The amplification circuitry amplifies the summed signal to produce a random noise output signal.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: July 15, 2008
    Assignee: Avago Technologies General IP Pte Ltd
    Inventor: Robert H. Miller, Jr.
  • Patent number: 7302456
    Abstract: A stochastic processor and a stochastic computer comprises a fluctuation generator configured to generate and output analog quantity having fluctuation comprised of chaos of tent mapping, a mixer configured to output a fluctuation superposed signal with the analog quantity output from the fluctuation generator superposed on an input signal represented by analog quantity and a thresholding unit configured to perform thresholding on the fluctuation superposed signal output from the mixer to generate and output a pulse.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: November 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Michihito Ueda, Katsuya Nozawa, Toyonori Munakata
  • Patent number: 7218741
    Abstract: An adaptive differential microphone array method comprises receiving a signal, estimating a measured signal spectral covariance matrix of the signal, and estimating a direction of arrival of the signal based on the measured signal spectral covariance matrix of the signal. The method further comprises determining a fractional delay, and applying a differential microphone array filter to the signal based on the direction of arrival and the fractional delay.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: May 15, 2007
    Assignee: Siemens Medical Solutions USA, Inc
    Inventors: Radu Victor Balan, Justinian Rosca, Liang Hong, Volkmar Hamacher, Eghart Fischer
  • Patent number: 7092980
    Abstract: A programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. Configuration registers define the type of function to be performed, the way in which the analog blocks are to be coupled, the inputs and outputs of the analog blocks, and the characteristics of the analog elements. The configuration registers can be dynamically programmed. Thus, the device can be used to realize a large number of different analog functions and applications.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: August 15, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Monte Mar, Warren Snyder
  • Patent number: 7020281
    Abstract: A method for determining a result of a group operation performed an integral number of times on a selected element of the group, the method comprises the steps of representing the integral number as a binary vector; initializing an intermediate element to the group identity element; selecting successive bits, beginning with a left most bit, of the vector. For each of the selected bits; performing the group operation on the intermediate element to derive a new intermediate element; replacing the intermediate element with the new intermediate element; performing the group operation on the intermediate element and an element, selected from the group consisting of: the group element if the selected bit is a one; and an inverse element of the group element if the selected bit is a zero; replacing the intermediate element with the new intermediate element.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: March 28, 2006
    Assignee: Certicom Corp.
    Inventors: Ashok Vadekar, Robert J. Lambert
  • Patent number: 7007060
    Abstract: A method and circuit is presented for generating a random bit stream based on thermal noise of a Complementary Metal Oxide Semiconductor (CMOS) device. A circuit implementing the invention preferably includes at least a pair of identically implemented thermal noise generators whose outputs feed a differential amplifier. The differential amplifier measures and amplifies the difference between the noise signals. A sampling circuit compares the difference with a threshold value that is selected to track with process/voltage/temperature variations of the noise generator circuits to output a binary bit having a bit value determined according to the polarity of the noise difference signal relative to the threshold value. The sampling circuit may be clocked to generate a random bit stream.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: February 28, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Robert H Miller, Jr.
  • Patent number: 6970900
    Abstract: An optical system utilizing phosphors to perform mathematical operations without the direct or necessary use of an electronic component or electrical power source is disclosed. The luminenscent and quenching properties of phosphors are combined with at least one first-order relaxation subsystem such that when the optical system achieves equilibrium, it will have performed certain mathematical operations. The precise mathematical operation to be performed is determined by controlling the materials utilized, light inputs, and certain variables within the optical system.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: November 29, 2005
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: John L. Johnson
  • Patent number: 6941336
    Abstract: A programmable analog system architecture and method thereof are described. The analog system architecture and method introduce a single chip solution that contains a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The architecture includes an array of analog blocks, including continuous time blocks and different types of switched capacitor blocks. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. The architecture thereby facilitates the design of customized chips at less time and expense.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: September 6, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventor: Monte Mar
  • Patent number: 6910126
    Abstract: A method of programming a programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. Configuration registers define the type of function to be performed, the way in which the analog blocks are to be coupled, the inputs and outputs of the analog blocks, and the characteristics of the analog elements. The configuration registers can be dynamically programmed. Thus, the device can be used to realize a large number of different analog functions and applications.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: June 21, 2005
    Assignee: Cypress Microsystems, Inc.
    Inventors: Monte Mar, Warren Snyder
  • Patent number: 6898616
    Abstract: An arbitrary function generating circuit incorporating an analog multiplier, amplifier, and frequency multiplier to construct a nonlinear analog circuit equivalent to a generalized Lotka-Volterra equation for performing high-speed calculations.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: May 24, 2005
    Assignee: National Agriculture and Bio-oriented Research Organization
    Inventor: Masayuki Hirafuji
  • Patent number: 6857003
    Abstract: A method of generating random numbers comprises: generating a first noise and passing the first noise through a first high pass filter which removes a periodic component contained in the first noise to produce a first noise signal having 1/f characteristic; generating a second noise and passing the second noise through a second high pass filter which removes a periodic component contained in the second noise to produce a second noise signal having 1/f characteristic; supplying the first and second noise signals to a differential circuit to derive a different signal between the first noise signal and said second noise signal; and generating, from the different signal, random numbers which do not have a periodicity due to 1/f characteristics of the first and second noise signals.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: February 15, 2005
    Assignee: Niigata University
    Inventor: Yoshiaki Saito
  • Publication number: 20040267864
    Abstract: A level detection circuit is provided with an arithmetic unit which multiplies an input signal Vin by a value, an integration circuit which integrates the result of computation by the arithmetic unit, and a comparison unit which compares the result of integration by the integration circuit and the input signal Vin and detects a signal level change of the input value Vin.
    Type: Application
    Filed: April 1, 2004
    Publication date: December 30, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoru Kojima
  • Publication number: 20040260743
    Abstract: A method of activating at least one electrical igniter incorporated in each of a plurality of gas generators provided in an air bag system is provided. The method includes: connecting an electronic control unit to a power source and an impact detecting sensor; providing a bus line having a plurality of loop wires passing through the electronic control unit to supply and transmit current and required information; connecting each of the at least one electrical igniter to the electronic control unit through the bus line branched from predetermined portions of the bus line; providing each of the at least one electrical igniter with a heat generating portion, a priming ignited by the heat generating portion, a capacitor, and an integrated circuit recorded with information to exhibit required functions; and supplying a current for igniting the priming to the at least one igniter through the capacitor.
    Type: Application
    Filed: July 9, 2004
    Publication date: December 23, 2004
    Applicant: Daicel Chemical Industries, Ltd.
    Inventors: Mitsuyasu Okamoto, Shingo Oda
  • Patent number: 6810407
    Abstract: An optical device for performing at least one Boolean logic operation. The optical device has at least a first and second input signal and at least one output signal. The optical device includes at least one interferometer for receiving the at least a first and second input signals. The device also has at least one optical amplifier for creating a phase difference between the first and second inputs to generate the output signal to perform at least one Boolean logic operation.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: October 26, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: James J Jaques, Herman Melvin Presby