Abstract: Examples described herein relate to a data aggregation system for enabling query operations on restricted data that originates from multiple independent sources.

Abstract: An information process device according to an embodiment includes a thermal head that prints on paper at positions along a width direction based on a reference position. The sensor is at a sensor position in the width direction and detects marks on paper being conveyed by a conveyance unit. The controller controls the conveyance unit to convey a confirmation sheet and then detects a position of a mark on the confirmation sheet with the sensor. The detected position corresponds to the sensor position. The controller next controls the conveyance unit and the thermal head to print a line on a sheet corresponding to the sensor position. The controller is configured to receive a corrected sensor position based on a measured distance of the printed line to an edge of the sheet and update the print reference position accordingly.

Abstract: The present disclosure describes a computer using a combination of analogue and digital components/elements used in a cohesive manner. Depending on the signals and data the computer manipulates, the analog processing elements and digital processing elements can be used separately, independently or in combination to optimize the computational results and the performance of the computer.

Abstract: Examples of the present disclosure describe systems and methods of managing user tasks using isolated collections of data. In aspects, input may be received by a task management application/service. The task management application/service may analyze the input to determine isolated collection of resources identifying tasks associated with one or more user accounts. The task management application/service may aggregate and analyze the tasks to determine associations between the tasks, to classify tasks and/or to prioritize tasks. The task management application/service may use the analyzed data to provide notifications, prompt user action and/or provide query results. In aspects, the task management application/service may also provide an interface comprising a single master view of tasks aggregated from disparate data stores and/or user accounts associated with a user.

Abstract: Efficiency improvements for electronic task managers and an improved user experience are realized when more relevant and fewer irrelevant tasks are presented to users and users are given greater control in manipulating those task items. By heuristically determining times, locations, and semantics associated with task relevance and integrating the management of tasks into more applications, the functionality of the systems providing for electronic task management is improved, as computer resources are spent with greater utility to the users and the user experience is improved for the users.

Abstract: Examples described herein relate to a data aggregation system for enabling query operations on restricted data that originates from multiple independent sources.

Abstract: A request is received from a user of one of the one or more business applications for a business object. A single user interface is generating for displaying the data associated with the requested business object. A link between the requested business object and all of the data associated with the business object stored in the one or more data repositories is created. A subset of all of the data associated with the business object in the single user interface is displayed, the displaying being based on a role associated with the user making the request for the business object, the role being used by the at least one programmable processor for determining the subset of all of the data associated with the business object for displaying in the single user interface.

Abstract: Examples described herein relate to a data aggregation system for enabling query operations on restricted data that originates from multiple independent sources.

Abstract: Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.

Abstract: Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.

Abstract: In accordance with aspects of the present principles, an over-approximation of reachable states of a hybrid system may be determined by utilizing template polyhedra. Policy iteration may be utilized to obtain an over-approximation of reachable states in the form of a relaxed invariant based upon template polyhedra expressions. The relaxed invariant may be used to construct a flowpipe to refine the over-approximation and thereby determine the reachable states of the hybrid system.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: A method of transforming an analog electrical signal into a wavelet transform. The analog electrical signal is input into a transmission line system as a transmission line input signal. A wavelet transform lifting is performed on the transmission line input signal to provide at least a first sum signal and a first difference signal of the transmission line input signal. The sum signal is designated as a first wavelet transform approximation signal and the difference signal is designated as a first wavelet transform detail signal.

Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current.

Abstract: One embodiment of the present method, program, and apparatus for natural language generation enables a language generation system to generate a grammatically correct natural language sentence by retrieving and adapting one or more stored sentences having semantic features similar to semantic features of a system-generated semantic representation. The retrieval of stored sentences is guided at least in part by the ease with which the stored sentences may be adapted to produce a grammatically correct sentence, enabling rapid generation of accurate output.

Abstract: A processor, a circuit and a method for processing images in an analog parallel processor network. A processor comprises a plurality of circuits, a bias transistor and an output transistor. A circuit comprises a first transistor and a second transistor, which receive respective supply voltages and operate as current sources, providing an output voltage. A circuit further comprises a coefficient coupling, which receives the output voltage provided by the first transistor and the second transistor, providing a switching function for a circuit output current. A transistor in a coefficient coupling determines a mode of operation based on the output voltage, provided by the first transistor and the second transistor, and an input current. The circuit provides an output current of the circuit for further processing.

Abstract: For sequentially input data string, the outliner and the change point are detected through calculation of the outlier score and the change point score by combining a time-series model learning device to learn the generation mechanism of the read data series as the time-series statistic model, a score calculator to calculate the outlier score of each data based on the time-series model parameter and the input data, a moving average calculator to calculate the moving average of the outlier score, a time-series model learning device to learn the generation mechanism of the moving average series as the time-series statistic model and the above score calculator that further calculates the outlier score of the moving average based on the moving average of the outlier score and outputs the result as the change point score of the original data.

Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.

Abstract: A method of programming a programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. Configuration registers define the type of function to be performed, the way in which the analog blocks are to be coupled, the inputs and outputs of the analog blocks, and the characteristics of the analog elements. The configuration registers can be dynamically programmed. Thus, the device can be used to realize a large number of different analog functions and applications.

Abstract: An arbitrary function generating circuit incorporating an analog multiplier, amplifier, and frequency multiplier to construct a nonlinear analog circuit equivalent to a generalized Lotka-Volterra equation for performing high-speed calculations.

Abstract: A computer-based system includes task computing enabling users to define tasks by combining available functionality and to execute such tasks. The computer-based system of includes available functionality which originates in devices, computing applications and electronic services available through local and remote procedure calls including Web Services, UPnP, CORBA, RMI, RPC, DCE, DCOM or comprises previously defined tasks. All available functionality is abstracted to the user as a service and each service is expressed in a service description language, and the services have a semantic description associated with them.

Abstract: A circuit comprising a digital processor, analogue processing means, a digital to analogue converter for converting digital values output from the digital processor into analogue values which are processed by the analogue processing means, and an analogue to digital converter for converting resulting analogue values into digital values for input to the digital processor, wherein the analogue processing means comprises one or more analogue processors, and the circuit is dynamically reconfigurable under the control of the digital processor, such that analogue values are processed according to a first function by the analogue processing means, and following reconfiguration, analogue values are processed according to a second function by the analogue processing means.

Abstract: A sub-flux quantum generator includes an N-turn ring having a plurality of connected turns about a common aperture. The width of each respective turn in the N-turn ring exceeds the London penetration depth of a superconducting material used to make the respective turn. The generator includes a switching device configured to introduce a reversible localized break in the superconductivity of at least one turn in the N-turn ring. The generator includes a magnetism device configured to generate a magnetic field within the aperture of the N-turn ring. A method for biasing a superconducting structure that encompasses all or a portion of an N-turn ring. While a supercurrent is flowing through the N-turn ring, a quantized magnetic flux is introduced into the aperture of the N-turn ring using a reversible localized break in a turn in the ring. The quantized magnetic flux is trapped in the ring by removal of the localized break. The trapped flux biases the superconducting structure.

Abstract: A processor, a circuit and a method for processing images in an analog parallel processor network. A processor comprises a plurality of circuits, a bias transistor and an output transistor. A circuit comprises a first transistor and a second transistor, which receive respective supply voltages and operate as current sources, providing an output voltage. A circuit further comprises a coefficient coupling, which receives the output voltage provided by the first transistor and the second transistor, providing a switching function for a circuit output current. A transistor in a coefficient coupling determines a mode of operation based on the output voltage, provided by the first transistor and the second transistor, and an input current. The circuit provides an output current of the circuit for further processing.