Abstract: According to some embodiments, the present disclosure may relate to a method of neural network analysis that includes receiving a first electronic message, storing it in a storage device, and decoding it to output a first data structure. The first electronic message may reference a first dictionary entry correlating the first electronic message to the first data structure including more bits than the first message. The method may also include providing the first data structure to a processing element to perform a data structure analysis on the first data structure yielding a second data structure including more bits than the first electronic message. The method may also include matching the second data structure to a second dictionary entry correlating the second data structure to a second electronic message that includes fewer bits than the second data structure, and transmitting the second electronic message instead of the second data structure.

Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction.

Abstract: A communications device includes pre-processing circuitry for processing a received wideband complex signal including an undesired narrowband interference component therein, and for determining a frequency of the undesired narrowband interference component. A filter is downstream from the pre-processing circuitry and operable to generate a received wideband complex signal with at least one frequency notch therein to suppress the undesired narrowband interference component. The filter includes a finite impulse response (FIR) filter with L taps to generate N output values, with L>N. A Fast Fourier Transform (FFT) block is downstream from the FIR filter and has a length N so that filter transition regions occur between frequency bins of the FFT block. A notching block is downstream from the FFT block to generate the frequency notch. An Inverse Fast Fourier Transform (IFFT) block is downstream from the notching block and has the length N.

Abstract: A hadamard gate includes two strongly cross-coupled limit cycle oscillators. Each limit cycle oscillator includes an amplifier, a summing node, an integrator, a hysteresis quantizer, a self-feedback 1-bit DAC (Digital-to-Analog Converter) and a cross-feedback 1 bit DAC. Each oscillator output drives its own self-feedback DAC and the cross-feedback DAC of the other oscillator.

Abstract: A method of transforming an analog electrical signal into a wavelet transform. The analog electrical signal is input into a transmission line system as a transmission line input signal. A wavelet transform lifting is performed on the transmission line input signal to provide at least a first sum signal and a first difference signal of the transmission line input signal. The sum signal is designated as a first wavelet transform approximation signal and the difference signal is designated as a first wavelet transform detail signal.

Abstract: A method and system is described for optimizing a digital filter defined by coefficients that are multiplied by input data and accumulated to generate output data. A factorization set of candidate factors is compiled based on the coefficients. For each of the candidate factors, an optimized solution is generated. To generate the optimized solution, the candidate factor is applied to the coefficients and a working set of terms is compiled. Terms in the working set are converted to power-of-two representations and grouped with other terms that have a common partial sum, or multiple of the partial sum, within their respective power-of-two representations. A reduction set is compiled from the grouped terms and an order of application is selected based on optimization objectives. The reduction set is then applied to the working set of terms to generate the optimized solution, which is ranked and stored based on the optimization objectives.

Abstract: A plurality of first measured values (xi) are obtained by respectively measuring a plurality of measuring objects in a plurality of first measuring systems and a plurality of second measured values (yi) are obtained by respectively measuring the plurality of measuring objects in a plurality of second measuring systems, and a combination of a first measured value and a second measured value corresponding to each other is obtained as a sample point (Pi). A transformation function representing a relationship between a first reconstituted system derived from the plurality of first measuring systems and a second reconstituted system derived from the plurality of second measuring system is obtained statistically processing a plurality of sample points of the plurality of measuring objects. Subsequently, a transformed value (?i) is obtained by transforming a second measured value (yi) with the transformation function.

Abstract: Method and apparatus for generating an Nth order Boolean derivative from r bit-array Qth order partial derivatives combined using fusion. Exemplary applications include multimedia, e.g., signal, image and video, processing systems; security systems; edge detection, compression, filtering, multimedia data, e.g., signal, image, video, interpolation and resizing systems; biometrics and recognition systems; networking and communication systems; static hazard free circuit design, simplifying gates in circuits; circuit testing, fault detection, and analysis systems.

Abstract: This invention provides a universal interface system that is capable of launching software applications across operating system platforms. For example, the universal interface system allows a computer using a Microsoft Windows operating system to launch and execute software applications that were written for a UNIX operating system environment. Conversely, the universal interface system allows software applications written for a Linux operating system environment to be launched and operating in a Sun Solaris operating system environment. The universal interface system may interface between the BIOS and the operating system or operate on top of the operating system.

Abstract: A system for efficient implementation of transforms. The implementation by flows of particles, and summation by a conservation low offers savings. In particular for an electronic implementation, a current mode implementation is described, by which replicators, sign changers are implemented by current mirrors and summation is performed in a node by Kirchoff″s law. The transform implementation is efficient for on-chip compression avoiding the need to convert to digital all signals from a sensing array. It is also an efficient implementation for direct control of an emitting array, such as a display which can be directly controlled with outputs from a transform block performing decompression.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: The present invention includes a data compression system which implements transformation and quantization functions using analog devites. The system includes a transformation module with analog devices (22), a quantization module with analog devices (24) and an entropy coding module (26). A data decompression system which implements inverse transformation and inverse quantization functions using analog devices is also shown.

Abstract: A digital signal processing apparatus comprises a sensor, a multi-valued binary level signal generator, a wavelet transform section, and a post processor. The signal generator receives analog signals output from the sensor and converts them to multi-valued binary level signals. The wavelet transform section has fundamental elements and threshold devices. The fundamental elements are provided at the nodes of a tree structure. Each threshold device is designed to receive at least two multi-valued signals and to output one binary signal, it receives the coefficients of the scaling functions output from the fundamental elements provided at the same level of the tree structure, for extracting the feature of the analog signal. The output signals of the wavelet transform section, i.e., the results of the wavelet transform, are input to the post processor. The apparatus can therefore perform signal processing including wavelet transform, at high speed without using large-scale hardware.