Using Transmitter And Receiver Patents (Class 710/106)
  • Patent number: 11880611
    Abstract: A data process device includes a data input unit and a processor. The processor includes a division unit, a first storage unit and a second storage unit which have a plurality of storage areas, a write unit, a calculation unit, and a control unit. The division unit divides a data series input by the data input unit to generate a plurality of divided data. The write unit writes the divided data to the first storage unit according to writing order to the storage areas in the first storage unit. The calculation unit performs calculation processing on the divided data written to the first storage unit, and writes calculated data obtained by the calculation processing to the second storage unit according to writing order to the storage areas in the second storage unit. The control unit controls processing of the write unit and processing of the calculation unit, which are divided into different processing lines, to be executed in parallel by pipeline processing.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: January 23, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takahiro Suzuki, Sang-Yuep Kim, Junichi Kani
  • Patent number: 11809348
    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: November 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary Franklin Chard, Tpinn Ronnie Koh, Harshil Atulkumar Shah
  • Patent number: 11786245
    Abstract: A surgical system is usable in a surgical procedure. The surgical system includes a surgical hub; a powered surgical instrument; and a communication module configured to: receive first data regarding a first surgical activity of the surgical procedure; receive second data regarding a second surgical activity of the surgical procedure; select transmission rates for transmission of the first data and the second data between the powered surgical instrument and the surgical hub based on at least one characteristic of at least one of the first surgical activity and the second surgical activity; and transmit the first data and the second data between the powered surgical instrument and the surgical hub at the selected transmission rates.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 17, 2023
    Assignee: CILAG GMBH INTERNATIONAL
    Inventor: Frederick E. Shelton, IV
  • Patent number: 11792361
    Abstract: A redriver system adapted for coupling to a first device and to a second device includes first and second transmitter drivers and a snoop circuit. The first transmitter driver has a first enable input. The second transmitter driver has a second enable input. The snoop circuit is coupled to the first and second enable inputs. The snoop circuit is configured to determine whether the first device and the second device are to operate according to a first protocol. Responsive to the snoop circuit determining that the first and second devices are to operate according to the first protocol, the snoop circuit enables the first transmitter driver and disables the second transmitter driver. Responsive to the snoop circuit determining that the first and second devices are not to operate according to the first protocol, the snoop circuit disables the first transmitter driver and enables the second transmitter driver.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 17, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Michael Campbell, Mustafa Ulvi Erdogan, Douglas Edward Wente, Sridhar Ramaswamy
  • Patent number: 11714574
    Abstract: Various embodiments described herein provide for using analysis of a sequence of commands (issued by a host system) to manage a memory command component, such as a read engine or a write engine of a memory system.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Arun Kumar Reddy Thokala, Ameer Bhargav Kilari, Rajan Rishi, Badal Nilawar
  • Patent number: 11687744
    Abstract: This disclosure relates to systems with multiple NFC front ends and at least one shared controller. One disclosed system includes a first discrete device having a first near field communication (NFC) controller, a second discrete device having a second NFC controller, a communicative connection between the first discrete device and the second discrete device, and a system controller located on the first discrete device. The system controller is communicatively connected to the first NFC controller. The system controller is connected to the second NFC controller via the communicative connection. In specific approaches, the second discrete device can include a display which is also controlled by the system controller, and the system controller is NCI compliant and application aware. In specific approaches, the system controller can control the second NFC controller based on the content concurrently being provided to the display.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: June 27, 2023
    Assignee: CLOVER NETWORK LLC.
    Inventors: Ketan Patwardhan, Narayanan Gopalakrishnan
  • Patent number: 11650827
    Abstract: An embodiment is able to simplify the design and manufacturing process by unifying the step of writing boot loaders to the integrated circuits.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 16, 2023
    Assignee: SILICON WORKS CO., LTD.
    Inventor: Gyu Chul Lee
  • Patent number: 11651799
    Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyoung Park, Jaewoo Park, Younghoon Son, Youngdon Choi, Junghwan Choi
  • Patent number: 11625345
    Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 11, 2023
    Assignee: SILICON MOTION INC.
    Inventor: Chao-Kuei Hsieh
  • Patent number: 11615046
    Abstract: The present application relates to a bus communication signal conversion method and device, a medium, and a numerical control machine tool control equipment. The bus communication signal conversion method comprises: acquiring an interface type of a bus interface of a first equipment end; receiving an output signal sent by a communication interface of a second equipment end; extracting a working parameter value of the second equipment end from the output signal; and sending the working parameter value of the second equipment end to the bus interface of the first equipment end according to a communication protocol corresponding to the interface type. The use of the present method can achieve signal conversion between different types of interfaces, thereby ensuring effectiveness of communication.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 28, 2023
    Assignees: HAN'S LASER TECHNOLOGY INDUSTRY GROUP CO., LTD., SHENZHEN HAN'S SMART CONTROLTECHNOLOGY CO., LTD.
    Inventors: Yuxin Feng, Yan Chen, Yunfeng Gao
  • Patent number: 11494126
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Julian Vlaiko, Idan Alrod, Tien-Chien Kuo, Nimrod Hermesh, Eran Sharon
  • Patent number: 11403241
    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11394589
    Abstract: Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Nobuyuki Umeda, Casto Salobrena Garcia, Rethin Raj, Andreas Schneider
  • Patent number: 11385824
    Abstract: An apparatus in one embodiment stores a first version of an operating system data structure comprising a first identifier of a logical storage device associated with a first access protocol, and in conjunction with migration of the logical storage device from utilization of the first access protocol to utilization of a second access protocol, temporarily continues to present information from the first version of the operating system data structure in response to one or more requests relating to the logical storage device, obtains a second identifier of the logical storage device associated with the second access protocol, stores a second version of the operating system data structure comprising the second identifier of the logical storage device associated with the second access protocol, and switches from presenting information from the first version of the operating system data structure to presenting information from the second version of the operating system data structure.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 12, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Amit Pundalik Anchi, Vinay G. Rao, Sanjib Mallick, Arieh Don
  • Patent number: 11381432
    Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright, Dean D. Gans
  • Patent number: 11345467
    Abstract: A data transmission method and a sending end device are provided. The method is applied to short-range wireless communication based on a high carrier frequency. During the process of a sending end device sending data to be transmitted to a receiving end device, the method includes: after short-range wireless communication interrupted between the sending end device and the receiving end device is restored, the sending end device querying recorded transmission information, wherein the transmission information is used to indicate a data block, transmission of which is not completed, in the data to be transmitted; and the sending end device sending, to the receiving end device, the data block, transmission of which is not completed, in the data to be transmitted.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: May 31, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Shangbo Lin, Shiming Wan, Jialiang Zhang
  • Patent number: 11334134
    Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 17, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Naveen Kumar Narala, Richard Dominic Wietfeldt, Christopher Kong Yee Chun
  • Patent number: 11323548
    Abstract: Method and system for lossless and stateless compression scheme is used with a fixed-length data such as frames. Frames having a payload of M bits length are mapped into a payload of N bits length, where N<M. The N bits payload of each received frame is extracted, and mapped using a memory, PLD, or a processor, to reconstruct the uncompressed M bits payload, and to form the original frame. The reconstruction may use a set of N coefficients that are each multiplied by the corresponding received payload bit, and summarized modulo-2 to obtain the original pre-compressed M payload bits. The method and system may be used with a vehicle bus, such as Controller Area Network (CAN). The compressed frames may use the same or different protocol than the uncompressed ones, and may further carry an additional code such as metadata, error detection or correction code, or authentication related code.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 3, 2022
    Assignee: ARILOU INFORMATION SECURITY TECHNOLOGIES LTD.
    Inventors: Avraham Entelis, Gil Litichever, Moshe Karl, Ziv Levi
  • Patent number: 11309995
    Abstract: Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 19, 2022
    Assignee: CREDO TECHNOLOGY GROUP LIMITED
    Inventors: Junqing Sun, Haoli Qian
  • Patent number: 11301160
    Abstract: A system and method are presented for a replication protocol in a real-time statistical engine. A real-time statistical engine monitors external data sources and uses received data to derive on-demand statistics. The engine may be comprised of a plurality of instances. In an embodiment with two instances of the engine, the instances are labeled as a primary instance and a backup instance. In case of primary instance failure, client servers of the engine are able to connect to the backup instance and obtain the same statistics with minimal data loss. The communication system between the primary instance and the backup instance may be used to exchange information about requested statistics, to clean unused statistics and to unconditionally delete statistics for which computation has become impossible.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 12, 2022
    Inventor: Vitaly Y. Barinov
  • Patent number: 11302279
    Abstract: A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: April 12, 2022
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Shun-Hsun Yang, Tse-Hung Wu
  • Patent number: 11232048
    Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 25, 2022
    Assignee: SILICON MOTION INC.
    Inventor: Chao-Kuei Hsieh
  • Patent number: 11138112
    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Doddaballapur N. Jayasimha, Samantika S. Sury, Christopher J. Hughes, Jonas Svennebring, Yen-Cheng Liu, Stephen R. Van Doren, David A. Koufaty
  • Patent number: 11100036
    Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: August 24, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Andrew Brown, David Heinrich
  • Patent number: 11073862
    Abstract: A synchronization circuit and a cascaded synchronization circuit for converting an asynchronous signal into at least one synchronous signal are provided. The synchronization circuit includes a signal control circuit, a flip-flop circuit, a clock enable circuit and a clock control circuit. The flip-flop circuit is coupled to the signal control circuit, the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit, and the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit. The signal control circuit and the clock control circuit can guarantee hold time and setup time is sufficient to allow the flip-flop circuit to output the synchronous signal without glitch regardless of the asynchronous signal.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 27, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Jen-Shou Hsu
  • Patent number: 11036660
    Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: George Chong Hean Ooi, Lai Guan Tang, Chee Hak Teh
  • Patent number: 11030903
    Abstract: A system includes a processor and a memory. The memory stores instructions executable by the processor to specify a driving pattern including a vehicle speed and position in a lane to encode a message determined based on vehicle sensor data, and to actuate a vehicle actuator based on the encoded message.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 8, 2021
    Assignee: Ford Global Technologies, LLC
    Inventors: Erik J. Christen, Mahmoud Abdelhamid, Pallav Sohoni
  • Patent number: 10976930
    Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto
  • Patent number: 10938577
    Abstract: This specification describes techniques for handling a blockchain service. A service request sent by a client is received by a first application of a first consensus node of a blockchain network, where the first consensus node includes the first application, a second application, and a database. To-be-sent service data is determined based on the service request. The to-be-sent service data is stored in the database by the first application. A determination is made as to whether a predetermined condition is satisfied. If it is determined that the predetermined condition is satisfied, the to-be-sent service data is retrieved from the database by the first application or the second application. The to-be-sent service data is transmitted to a second consensus node of the blockchain network.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Qiang Tang
  • Patent number: 10924305
    Abstract: Disclosed herein are devices and methods to facilitate compensating for intra-pair skew in a high-definition multimedia interface (HDMI) system. One or more skew training pattern may be transmitted on a signal line including a differential pair. Acknowledgment of receiving the skew training pattern may be received on a display data channel (DDC) associated with HDMI system. The skew training pattern may be used to ascertain and compensate for intra-pair skew.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Aruna Kumar, Anoop Karunan, Ganesh Balamurugan, Prakash Radhakrishnan
  • Patent number: 10917100
    Abstract: Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry, comprising a pair of latch input transistors which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry; and gain-stage circuitry, comprising a pair of cross-coupled gain-stage output transistors connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 9, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Suhas Rattan
  • Patent number: 10909452
    Abstract: A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up the block.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Patent number: 10869111
    Abstract: In some embodiments, a transceiver is configured to wirelessly transfer data between a host computing device and a plurality of peripheral devices over a communication path using a communication data construct sent by the transceiver comprising a plurality of packet structures forming a communication protocol for communicating peripheral device data (HID or audio data) between the host device and the plurality of peripheral devices. Each of the packet structures of the plurality of packet structures can include a single destination address configured to identify which of the plurality of peripheral devices will receive peripheral device data from the host computing device in the present packet structure and which of the plurality of computer peripheral devices will not receive peripheral device data from the host computing device in a present packet structure; and a data field configured to contain peripheral operational data for each of the plurality of peripheral devices.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Logitech Europe S.A.
    Inventors: Philippe Chazot, Jiri Holzbecher
  • Patent number: 10856129
    Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An operating method of a first electronic device in a communication system is provided.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Suk Ko, Ohyun Jo
  • Patent number: 10740266
    Abstract: This disclosure describes systems, methods, and devices related to sensor data pipelining. A device may identify a first request of one or more requests received from a wireless universal serial bus (USB) host, wherein the first request is to collect data from a USB sensor. The device cause to send the first request to the USB sensor. The device identify a first response from the USB sensor, wherein the first response comprises data collected by the USB sensor based on the first request. The device determine that no additional requests are received from the wireless USB host. The device cause to send a second autonomous request to the USB sensor to collect data. The device identify a second response received from the USB sensor, wherein the second response is associated with the autonomous second request. The device cause to buffer or send the second response to the wireless USB host based on a second request being received from the wireless USB host.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 11, 2020
    Assignee: Intel IP Corporation
    Inventors: Elad Levy, Michael Glik, Miron Maevsky, Bahareh Sadeghi, Rafal Wielicki, Avishai Ziv
  • Patent number: 10686283
    Abstract: A semiconductor device for determining whether a foreign substance (e.g., water) is present and a method of operating the same are provided. The semiconductor device includes a receptacle including a plurality of pins according to a USB type-C receptacle interface; a first current source providing first current to a CC1 signal pin or a CC2 signal pin among the plurality of pins in a first operation mode; a second current source providing second current to the CC1 signal pin or the CC2 signal pin in a second operation mode; a third current source providing third current to at least two pins of other pins excluding the CC1 signal pin and the CC2 signal pin; and a power delivery integrated circuit (PDIC) controlling the first current source, the second current source and the third current source and detecting the voltage level of a signal outputted to the plurality of pins.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je Kook Kim
  • Patent number: 10664426
    Abstract: Disclosed is an electronic device including a first communication circuit that perform communication by using a first communication protocol, and a processor electrically connected to the first communication circuit, wherein the processor activates the first communication circuit based on a predetermined mutual operation, sets an operating mode of the electronic device based on at least part of the activation of the first communication circuit, and operates a universal serial bus (USB) host controller through a switching circuit based on the set operating mode.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Woo Kwang Lee, Kyoung Hoon Kim, Bo Ram Namgoong
  • Patent number: 10664371
    Abstract: A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 26, 2020
    Assignee: Mixel Inc.
    Inventor: Ashraf K. Takla
  • Patent number: 10664424
    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gary Franklin Chard, Tpinn Ronnie Koh, Harshil Atulkumar Shah
  • Patent number: 10664419
    Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 26, 2020
    Assignee: Arm Limited
    Inventors: Alejandro Rico Carro, Pavel Shamis, Stephan Diestelhorst
  • Patent number: 10651952
    Abstract: In an example embodiment, a communication system provides a clock extension peripheral interface (CXPI) communication bus that is coupled to a master node and a plurality of slave nodes. The master node is configured to transmit a reference clock signal on the CXPI communication bus. Each slave node of the plurality of slave nodes is configured to receive the reference clock signal from the CXPI communication bus and to transmit and receive data to and from the CXPI communication bus based on the reference clock signal.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 12, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kazuhiro Tomita, Masuo Inui
  • Patent number: 10642946
    Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Ankireddy Nalamalpu, Md Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
  • Patent number: 10574553
    Abstract: Methods and systems are provided for evaluating a CAN that includes a CAN bus and a plurality of modules configured to communicate over the CAN bus. A voltage sensor may be provided in electrical communication with the CAN bus. A number (N) of pairs of voltages may be read. Each pair may include a CAN high (CAN-H) value and a CAN low (CAN-L) value. The N pair of voltages may be processed through a comparison of the CAN-H values and the CAN-L values. Whether a fault signature is present in the CAN-H and CAN-L values may be determined from the processing.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: February 25, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Xinyu Du, Shengbing Jiang, Qi Zhang, Aaron B. Bloom
  • Patent number: 10564868
    Abstract: A method and apparatus for selecting power states in storage devices for computers including providing monitoring storage device parameters and comparing those parameters to endurance thresholds to increase reliability of the storage device.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Itshak Afriat, Judah Gamliel Hahn, Karin Inbar
  • Patent number: 10567706
    Abstract: An interface module 61 relays control signal communication between a main CPU 621 and a light source control CPU 651 and between the main CPU 621 and a camera head CPU 242. The interface module 61 includes an FPGA 610 having CPU I/Fs 611 to 613 that correspond to communication schemes of CPUs 621, 651, and 242, respectively, and first and second storage units 615 (617) and 616 (618). The FPGA 610 relays a control signal between the main CPU 621 and the light source control CPU 651 and between the main CPU 621 and the camera head CPU 242, while temporarily storing the control signal in the first and the second storage units 615 (617) and 616 (618). Moreover, a first communication timing and second and third communication timings are set at timings shifted from one another.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 18, 2020
    Assignee: SONY OLYMPUS MEDICAL SOLUTIONS INC.
    Inventors: Aki Mizukami, Yoshihiro Koizumi, Masashige Kimura
  • Patent number: 10545903
    Abstract: In accordance with an embodiment, a method includes receiving a transmission signal; converting the received transmission signal into a corresponding bus signal by driving an output stage of a transmitter having a plurality of switches, where a switching behavior of the plurality of switches of the output stage is dependent on a parameter set; converting the bus signal into a corresponding reception signal, wherein an edge of the reception signal is delayed by a loop delay relative to a corresponding edge in the transmission signal; determining a measurement value for the loop delay; and altering the parameter set in order to adapt the loop delay.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: January 28, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Dieter Metzner, Magnus-Maria Hell
  • Patent number: 10459028
    Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 29, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10440198
    Abstract: An image processing apparatus is capable of communicating with a mobile terminal by short range radio communication, and includes an image reader that reads an image of a document, a generator that generates image data based on the image read by the image reader, and a notifying controller that notifies a user to bring the mobile terminal close to a communicable area in accordance with completion of reading the image by the image reader. In addition, a transmitter transmits the image data generated by the generator to the mobile terminal by the short range radio communication in accordance with being able to communicate with the mobile terminal by short range radio communication.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 8, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yuya Hasegawa
  • Patent number: 10405405
    Abstract: The present invention proposes to use a power negotiation connection (e.g. the VBUS channel) of a power delivery interface for transmitting or receiving control commands or, respectively, status information to/from a lighting device. The power negotiation connection can be used as a communication channel that is fully independent of the data connection. It uses, for example, different protocols and different wires than the data connection. Control commands, such as dim level or color, can be encoded in a vendor defined message of a related power negotiation protocol.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: September 3, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Matthias Wendt, Marcel Beij
  • Patent number: 10361793
    Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 23, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kazuhiro Tomita, Masuo Inui