Abstract: An electronic device is provided. The electronic device includes a battery, a connector including one or more signal terminals, a power regulator for adjusting a first voltage from the battery to a second voltage, at least one processor operably connected to the one or more signal terminals and the power regulator, and a memory. The memory can store instructions, that during the execution thereof, allow the at least one processor to sense the connection to an external electronic device through the connector, acquire identification information about the external electronic device after outputting the second voltage through the connector onto the external electronic device connected through the connector, and output, on the basis of the identification information of the external electronic device, the first voltage onto the external electronic device through the connector by using a bypass route.

Abstract: A Universal Serial Bus (USB) audio device kit includes a USB peripheral audio device and a passive USB-to-analog audio adapter. The USB peripheral audio device includes a USB interface configured to communicatively interface the USB audio peripheral device with a USB host device. The passive USB-to-analog audio adapter is configured to electrically interface the USB peripheral audio device with analog audio equipment via the USB interface.

Abstract: A device includes a serial interface, such as Universal Serial Bus (USB) interface, having two operating modes. The first operating mode has a higher data transfer rate than the second operating mode, but also causes greater interference affecting use of a wireless network. To prevent loss of connectivity from the wireless network, when a detected signal strength associated with the wireless network is less than a threshold value, the interface is switched from the first operating mode to the second operating mode to reduce interference to use of the wireless network. During times when detected signal strength for the wireless network is high, the interface is switched to the first operating mode to allow for higher data transfer rates.

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

Abstract: A transceiver device, communication control device, and method for a user station of a serial bus system. The transceiver device includes a first terminal for receiving a transmission signal from a communication control device, a transmission module for transmitting the transmission signal onto a bus, a reception module for receiving the signal from the bus, the reception module configured to generate a digital reception signal from the signal received from the bus, a second terminal for sending the digital reception signal to the communication control device and for receiving an operating mode changeover signal from the communication control device, and a changeover feedback block for outputting feedback regarding a changeover of the operating mode that has taken place based on the operating mode changeover signal. The changeover feedback block is configured to output the feedback to the communication control device via the second terminal and in the digital reception signal.

Abstract: A surgical stapling device includes an adapter assembly and a reload assembly. The adapter assembly includes an elongate body and a channel member coupled to the elongate body. The reload assembly includes an anvil and a cartridge assembly that includes a cartridge body and a channel extension. A proximal portion of the cartridge body is received within the channel member to secure the reload assembly to the adapter assembly. The channel extension is received about a distal portion of the cartridge body and is engaged with the channel member to support the cartridge body.

Abstract: A data process device includes a data input unit and a processor. The processor includes a division unit, a first storage unit and a second storage unit which have a plurality of storage areas, a write unit, a calculation unit, and a control unit. The division unit divides a data series input by the data input unit to generate a plurality of divided data. The write unit writes the divided data to the first storage unit according to writing order to the storage areas in the first storage unit. The calculation unit performs calculation processing on the divided data written to the first storage unit, and writes calculated data obtained by the calculation processing to the second storage unit according to writing order to the storage areas in the second storage unit. The control unit controls processing of the write unit and processing of the calculation unit, which are divided into different processing lines, to be executed in parallel by pipeline processing.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A surgical system is usable in a surgical procedure. The surgical system includes a surgical hub; a powered surgical instrument; and a communication module configured to: receive first data regarding a first surgical activity of the surgical procedure; receive second data regarding a second surgical activity of the surgical procedure; select transmission rates for transmission of the first data and the second data between the powered surgical instrument and the surgical hub based on at least one characteristic of at least one of the first surgical activity and the second surgical activity; and transmit the first data and the second data between the powered surgical instrument and the surgical hub at the selected transmission rates.

Abstract: A redriver system adapted for coupling to a first device and to a second device includes first and second transmitter drivers and a snoop circuit. The first transmitter driver has a first enable input. The second transmitter driver has a second enable input. The snoop circuit is coupled to the first and second enable inputs. The snoop circuit is configured to determine whether the first device and the second device are to operate according to a first protocol. Responsive to the snoop circuit determining that the first and second devices are to operate according to the first protocol, the snoop circuit enables the first transmitter driver and disables the second transmitter driver. Responsive to the snoop circuit determining that the first and second devices are not to operate according to the first protocol, the snoop circuit disables the first transmitter driver and enables the second transmitter driver.

Abstract: Various embodiments described herein provide for using analysis of a sequence of commands (issued by a host system) to manage a memory command component, such as a read engine or a write engine of a memory system.

Abstract: This disclosure relates to systems with multiple NFC front ends and at least one shared controller. One disclosed system includes a first discrete device having a first near field communication (NFC) controller, a second discrete device having a second NFC controller, a communicative connection between the first discrete device and the second discrete device, and a system controller located on the first discrete device. The system controller is communicatively connected to the first NFC controller. The system controller is connected to the second NFC controller via the communicative connection. In specific approaches, the second discrete device can include a display which is also controlled by the system controller, and the system controller is NCI compliant and application aware. In specific approaches, the system controller can control the second NFC controller based on the content concurrently being provided to the display.

Abstract: An embodiment is able to simplify the design and manufacturing process by unifying the step of writing boot loaders to the integrated circuits.

Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.

Abstract: The present application relates to a bus communication signal conversion method and device, a medium, and a numerical control machine tool control equipment. The bus communication signal conversion method comprises: acquiring an interface type of a bus interface of a first equipment end; receiving an output signal sent by a communication interface of a second equipment end; extracting a working parameter value of the second equipment end from the output signal; and sending the working parameter value of the second equipment end to the bus interface of the first equipment end according to a communication protocol corresponding to the interface type. The use of the present method can achieve signal conversion between different types of interfaces, thereby ensuring effectiveness of communication.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Abstract: Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.

Abstract: An apparatus in one embodiment stores a first version of an operating system data structure comprising a first identifier of a logical storage device associated with a first access protocol, and in conjunction with migration of the logical storage device from utilization of the first access protocol to utilization of a second access protocol, temporarily continues to present information from the first version of the operating system data structure in response to one or more requests relating to the logical storage device, obtains a second identifier of the logical storage device associated with the second access protocol, stores a second version of the operating system data structure comprising the second identifier of the logical storage device associated with the second access protocol, and switches from presenting information from the first version of the operating system data structure to presenting information from the second version of the operating system data structure.

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Abstract: A data transmission method and a sending end device are provided. The method is applied to short-range wireless communication based on a high carrier frequency. During the process of a sending end device sending data to be transmitted to a receiving end device, the method includes: after short-range wireless communication interrupted between the sending end device and the receiving end device is restored, the sending end device querying recorded transmission information, wherein the transmission information is used to indicate a data block, transmission of which is not completed, in the data to be transmitted; and the sending end device sending, to the receiving end device, the data block, transmission of which is not completed, in the data to be transmitted.

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

Abstract: Method and system for lossless and stateless compression scheme is used with a fixed-length data such as frames. Frames having a payload of M bits length are mapped into a payload of N bits length, where N<M. The N bits payload of each received frame is extracted, and mapped using a memory, PLD, or a processor, to reconstruct the uncompressed M bits payload, and to form the original frame. The reconstruction may use a set of N coefficients that are each multiplied by the corresponding received payload bit, and summarized modulo-2 to obtain the original pre-compressed M payload bits. The method and system may be used with a vehicle bus, such as Controller Area Network (CAN). The compressed frames may use the same or different protocol than the uncompressed ones, and may further carry an additional code such as metadata, error detection or correction code, or authentication related code.

Abstract: Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.

Abstract: A system and method are presented for a replication protocol in a real-time statistical engine. A real-time statistical engine monitors external data sources and uses received data to derive on-demand statistics. The engine may be comprised of a plurality of instances. In an embodiment with two instances of the engine, the instances are labeled as a primary instance and a backup instance. In case of primary instance failure, client servers of the engine are able to connect to the backup instance and obtain the same statistics with minimal data loss. The communication system between the primary instance and the backup instance may be used to exchange information about requested statistics, to clean unused statistics and to unconditionally delete statistics for which computation has become impossible.

Abstract: A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.

Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.

Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: A synchronization circuit and a cascaded synchronization circuit for converting an asynchronous signal into at least one synchronous signal are provided. The synchronization circuit includes a signal control circuit, a flip-flop circuit, a clock enable circuit and a clock control circuit. The flip-flop circuit is coupled to the signal control circuit, the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit, and the clock enable circuit is coupled to the signal control circuit and the flip-flop circuit. The signal control circuit and the clock control circuit can guarantee hold time and setup time is sufficient to allow the flip-flop circuit to output the synchronous signal without glitch regardless of the asynchronous signal.

Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.

Abstract: A system includes a processor and a memory. The memory stores instructions executable by the processor to specify a driving pattern including a vehicle speed and position in a lane to encode a message determined based on vehicle sensor data, and to actuate a vehicle actuator based on the encoded message.

Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

Abstract: This specification describes techniques for handling a blockchain service. A service request sent by a client is received by a first application of a first consensus node of a blockchain network, where the first consensus node includes the first application, a second application, and a database. To-be-sent service data is determined based on the service request. The to-be-sent service data is stored in the database by the first application. A determination is made as to whether a predetermined condition is satisfied. If it is determined that the predetermined condition is satisfied, the to-be-sent service data is retrieved from the database by the first application or the second application. The to-be-sent service data is transmitted to a second consensus node of the blockchain network.

Abstract: Disclosed herein are devices and methods to facilitate compensating for intra-pair skew in a high-definition multimedia interface (HDMI) system. One or more skew training pattern may be transmitted on a signal line including a differential pair. Acknowledgment of receiving the skew training pattern may be received on a display data channel (DDC) associated with HDMI system. The skew training pattern may be used to ascertain and compensate for intra-pair skew.

Abstract: Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry, comprising a pair of latch input transistors which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry; and gain-stage circuitry, comprising a pair of cross-coupled gain-stage output transistors connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.

Abstract: A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up the block.

Abstract: In some embodiments, a transceiver is configured to wirelessly transfer data between a host computing device and a plurality of peripheral devices over a communication path using a communication data construct sent by the transceiver comprising a plurality of packet structures forming a communication protocol for communicating peripheral device data (HID or audio data) between the host device and the plurality of peripheral devices. Each of the packet structures of the plurality of packet structures can include a single destination address configured to identify which of the plurality of peripheral devices will receive peripheral device data from the host computing device in the present packet structure and which of the plurality of computer peripheral devices will not receive peripheral device data from the host computing device in a present packet structure; and a data field configured to contain peripheral operational data for each of the plurality of peripheral devices.

Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An operating method of a first electronic device in a communication system is provided.

Abstract: This disclosure describes systems, methods, and devices related to sensor data pipelining. A device may identify a first request of one or more requests received from a wireless universal serial bus (USB) host, wherein the first request is to collect data from a USB sensor. The device cause to send the first request to the USB sensor. The device identify a first response from the USB sensor, wherein the first response comprises data collected by the USB sensor based on the first request. The device determine that no additional requests are received from the wireless USB host. The device cause to send a second autonomous request to the USB sensor to collect data. The device identify a second response received from the USB sensor, wherein the second response is associated with the autonomous second request. The device cause to buffer or send the second response to the wireless USB host based on a second request being received from the wireless USB host.

Abstract: A semiconductor device for determining whether a foreign substance (e.g., water) is present and a method of operating the same are provided. The semiconductor device includes a receptacle including a plurality of pins according to a USB type-C receptacle interface; a first current source providing first current to a CC1 signal pin or a CC2 signal pin among the plurality of pins in a first operation mode; a second current source providing second current to the CC1 signal pin or the CC2 signal pin in a second operation mode; a third current source providing third current to at least two pins of other pins excluding the CC1 signal pin and the CC2 signal pin; and a power delivery integrated circuit (PDIC) controlling the first current source, the second current source and the third current source and detecting the voltage level of a signal outputted to the plurality of pins.

Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.

Abstract: Disclosed is an electronic device including a first communication circuit that perform communication by using a first communication protocol, and a processor electrically connected to the first communication circuit, wherein the processor activates the first communication circuit based on a predetermined mutual operation, sets an operating mode of the electronic device based on at least part of the activation of the first communication circuit, and operates a universal serial bus (USB) host controller through a switching circuit based on the set operating mode.

Abstract: A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

Abstract: In an example embodiment, a communication system provides a clock extension peripheral interface (CXPI) communication bus that is coupled to a master node and a plurality of slave nodes. The master node is configured to transmit a reference clock signal on the CXPI communication bus. Each slave node of the plurality of slave nodes is configured to receive the reference clock signal from the CXPI communication bus and to transmit and receive data to and from the CXPI communication bus based on the reference clock signal.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: Methods and systems are provided for evaluating a CAN that includes a CAN bus and a plurality of modules configured to communicate over the CAN bus. A voltage sensor may be provided in electrical communication with the CAN bus. A number (N) of pairs of voltages may be read. Each pair may include a CAN high (CAN-H) value and a CAN low (CAN-L) value. The N pair of voltages may be processed through a comparison of the CAN-H values and the CAN-L values. Whether a fault signature is present in the CAN-H and CAN-L values may be determined from the processing.

Abstract: A method and apparatus for selecting power states in storage devices for computers including providing monitoring storage device parameters and comparing those parameters to endurance thresholds to increase reliability of the storage device.