Abstract: An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Abstract: The present invention provides a system for detecting an amount of R-32 refrigerant in an air temperature controller using an R-32 refrigerant, and a method of installing a configuration of R-32 sensors in the air temperature controller using an R-32 refrigerant. The system includes an R-32 control board, a first R-32 sensor, and a second R-32 sensor. The first R-32 sensor and the second R-32 sensor are coupled in series and electrically coupled to the R-32 control board. Each of the first R-32 sensor and the second R-32 sensor include sensing components configured to detect the amount of R-32 refrigerant.

Abstract: The present invention provides a system for detecting an amount of R-454b refrigerant in an air temperature controller using an R-454b refrigerant, and a method of installing a configuration of R-454b sensors in the air temperature controller using an R-454b refrigerant. The system includes an R-454b control board, a first R-454b sensor, and a second R-454b sensor. The first R-454b sensor and the second R-454b sensor are coupled in series and electrically coupled to the R-454b control board. Each of the first R-454b sensor and the second R-454b sensor include sensing components configured to detect the amount of R-454b refrigerant.

Abstract: Methods, systems, and devices for a read counter for quality of service design are described. First commands may be assigned to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level. The memory die may include a second queue associated with a second priority level different from the first priority level, the second queue comprising one or more second commands assigned. Based at least in part on a counter associated with the first queue and the first and second priority levels, it may be determined that a threshold number of the first commands of the first queue have issued without a command from the one or more second commands having issued. A command from the second commands may issue before issuing a next command of the first commands based at least in part on the counter.

Abstract: A serial transmission controller for processing data transmissions between a memory and an external device is provided. The serial transmission controller includes a microcontroller, a scheduling unit, a transmission unit, and an interception control unit. The microcontroller obtains pipe data from the memory. The microcontroller reads a transfer request block from the memory according to the pipe data. The scheduling unit generates a transmission request according to the pipe data and the transfer request block. The transmission unit transmits a packet of the transfer request block according to the transmission request, and correspondingly generates a transmission response. When the interception control unit receives the transmission response, and the data length that has not been transmitted in the transfer request block is greater than 0, the interception control unit notifies the transmission unit to continue to transmit a next packet of the transfer request block.

Abstract: An information handling system may include at least one central processing unit (CPU); and a plurality of special-purpose processing units. The information handling system may be configured to: receive information regarding cooling characteristics of the plurality of special-purpose processing units; and assign identification (ID) numbers to each of the plurality of special-purpose processing units in an order that is determined based at least in part on the cooling characteristics.

Abstract: An electronic device may use information about the location of nearby devices to make sharing with those devices more intuitive for a user. When two devices are pointed towards one another, each device may automatically present the option to share information with the other device. When a user wishes to share information with one or more devices in a group of users, an array of icons representing the nearby users may be positioned on the display according to the locations of the nearby users so that the sharing user can easily select which user he or she wishes to share with. A sharing user may broadcast a signal and nearby users may elect to receive the signal by pointing their devices towards the sharing user. A user of two devices may share information between the two devices and may use one device to manipulate the information on the other device.

Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

Abstract: A power Converter having power semiconductor components is disclosed herein, wherein a DC-link capacitor has a capacitance of less than 3 ?F and is not designed as a separate electrical device of the power converter, and wherein the clock frequency is greater than 1 MHz. A vehicle, (e.g., an aircraft), including a power Converter of this kind is also described.

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Abstract: A driverless traffic management vehicle has a control system having a controller interfacing steering and drive interfaces for control of respective steering and drive subsystems of the vehicle. The vehicle also has an impact attenuator and actuator therefor for configuring the attenuator in deployed and stowed configurations. The control system comprises at least one driverless mode controller operably controlling the steering and drive interfaces for controlling the vehicle in at least one of follow mode, remote-control and autonomous driverless mode of operation. To control traffic, the vehicle may be driven to a roadside location and set in the at least one driverless mode of operation to control the steering and drive interfaces accordingly.

Abstract: The disclosed technology provides solutions for improving the operational efficiency and safety of autonomous vehicles (AVs). In some implementations, the disclosed technology encompasses methods for performing vehicle clustering or platooning, for example, that can include steps for computing navigation routes for each of a plurality of autonomous vehicles (AVs), identifying a route overlap for a first AV and a second AV selected from among the plurality of AVs, and transmitting a clustering instruction to the first AV and the second AV based on the route overlap, wherein the clustering instruction is configured to cause the first AV and the second AV to initiate a clustering configuration. Systems and machine-readable media are also provided.

Abstract: A method for configuring a POS-System, which uses multiple peripheral devices to complete a transaction, and uses a device server to which all peripheral devices are registered and logically connectable a POS-System, includes the steps of: before starting a transaction on the POS-System, requesting the peripheral devices from the device server to dedicate the devices to the POS-System; once the request is granted, starting the transaction and informing the device server about the start of the transaction for blocking access to the peripheral devices for another POS-System; and when a request for a peripheral device from another POS-System is received from the devices server, checking if a transaction is pending for the peripheral device from the POS system and if the transaction is pending the request is automatically declined and if no transaction is pending the device is reassigned to the other POS-System.

Abstract: An electronic device comprises a bridge configured to transfer data bus transactions from a transaction source domain having a first bus width to a transaction target domain having a second bus width less than the first bus width. The bridge comprises a first interface configured to receive a transaction from the transaction source domain, where the transaction has a first transaction burst length. A converter logic is configured such that when a transaction is received via the first interface, the converter logic splits the transaction into a plurality of second transactions each having a respective second transaction burst length, wherein the plurality of second transactions have the second bus width. A second interface is configured to send the plurality of second transactions to the transaction target domain.

Abstract: A vehicle management device including request information reception means for receiving request information for platooning multiple vehicles; implementation feasibility assessment means for assessing an implementation feasibility of a platoon based on the request information; and implementation permission means for permitting implementation of the platoon based on a result of assessing of the implementation feasibility.

Abstract: A method of identifying a path for forwarding a packet by a packet forwarding element. The method receives a packet that includes a plurality of fields that identify a particular packet flow. The method computes a plurality of hash values from the plurality of fields that identify the particular packet flow. Each hash value computed using a different hash algorithm. Based on the plurality of hash values, the method identifies a plurality of paths configured to forward the packets of the particular flow. The method identifies the status of each of the plurality of paths. Each path status identifies whether or not the corresponding path is operational. The method selects an operational path in the plurality of paths to forward the packet based on a priority scheme using said plurality of identified status bits.

Abstract: A system and method are provided for facilitating efficient management of data structures stored in remote memory. During operation, the system receives a request to allocate memory for a first part in a data structure stored in a remote memory associated with a compute node in a network. The system pre-allocates a buffer in the remote memory for a plurality of parts in the data structure and stores a first local descriptor associated with the buffer in a local worker table stored in a volatile memory of the compute node. The first local descriptor facilitates servicing future access requests to the first and other parts in the data structure. The system stores a first global descriptor for the buffer in a shared global table stored in the remote memory and generates a first reference corresponding to the first part, thereby facilitating faster traversals of the data structure.

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

Abstract: An integrated circuit can be used to regulate data flow in a computing system. The integrated circuit can receive input data via a first interface associated with a first type of bus protocol and provide output data via a second interface associated with a second type of bus protocol. Size of the input data and the output data may vary based on the corresponding protocols. The integrated circuit can receive, via the first interface, an input data size for a write transaction to store the input data in a data storage unit. The integrated circuit can also receive a requested data size, via the second interface, to provide the output data for a read transaction. The integrated circuit can also generate an actual size of the output data based on the requested data size, the input data size, and size of the stored input data.

Abstract: An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Abstract: A management server executes interval adjustment processing to adjust a service frequency of a ride-sharing vehicle group. In the interval adjustment processing, it is judged whether or not a vehicle pair composed of two vehicles in a relationship of a preceding vehicle and a following vehicle includes a stopping vehicle that stops in a pick-up and drop-off point as a following vehicle. Further, it is judged whether or not the vehicle pair corresponds to a separated pair. If it is judged that vehicle pair includes the stopping vehicle as the following vehicle and the said vehicle pair corresponds to the separated pair, selection processing to select an overtaking vehicle is executed. The overtaking vehicle is a ride-sharing vehicle that overtakes with the stopping vehicle to cut into between the separated pair. An overtake instruction is transmitted to the overtaking vehicle selected by the selection processing.

Abstract: A method for operating a data bus subscriber of a local bus, particularly of a ring bus, the method including the steps of: receiving a first data packet over the local bus, wherein the first data packet has an address of the data bus subscriber to which it is directed and at least one instructions list, having a set of instructions for processing process data, receiving a second data packet over the local bus, wherein the second data packet has process data; and executing instructions of the at least one instructions list for processing the received process data. A corresponding data bus subscriber and a local bus master is also provided.

Abstract: An embodiment electronic system comprises a first device, a second device and a clock generator circuit. The clock generator circuit is configured to provide a clock signal having a selectable frequency. The first device comprises a first processing circuit having coupled therewith a first Ethernet interface, and the second electronic device comprises a second processing circuit having coupled therewith a second Ethernet interface. At least one of the first device and the second device is configured to determine a frequency of the clock signal as a function of an operating parameter of the first device and/or of the second device and/or as a function of a parameter of the frames exchanged between the first device and the second device, and to act on the clock generator circuit to operate the clock generator circuit at the frequency.

Abstract: One embodiment is directed to a master unit for a distributed antenna system (DAS). The master unit comprises one or more donor cards and one or more transport cards, and at least one passive backplane. Each passive backplane comprises a plurality of backplane connectors. Each backplane connector is configured to connect a respective donor card or transport card to the passive backplane. Each backplane connector is connected to each of the other connectors via one or more respective passive bi-directional backplane channels. The master unit is configured so that all active processing of streams of digital samples transported via the DAS is performed by the donor cards and transport cards and not the passive backplane.

Abstract: A circuit structure with automatic PCIe lane configuration adjustment and a method thereof are disclosed. The circuit structure includes a plurality of PCIe riser cards and a motherboard. The PCIe riser cards are of at least two lane sizes each associated with a PCIe size identifier. The motherboard includes a plurality of PCIe ports, a CPLD module, a storage unit, a BMC module and a BIOS unit. The PCIe ports are electrically connected to the respective PCIe riser cards via a plurality of PCIe cables. The CPLD module is electrically connected to the PCIe ports so as to be able to read the PCIe size identifiers thereof and determine current configuration information from a comparison between the PCIe size identifiers and present signals.

Abstract: An information handling system, including two or more single-slot M.2 modules; a dual-slot discrete graphics processing unit (dGPU) module; a printed circuit board, including: a plurality of M.2 connectors aligned on a same edge of the printed circuit board such that: a first single-slot M.2 module of the two or more single-slot M.2 modules is coupled to a first M.2 connector of the plurality of M.2 connectors; a second single-slot M.2 module of the two or more single-slot M.2 modules is coupled to a second M.2 connector of the plurality of M.2 connectors; and the dual-slot dGPU module is coupled to a third and a fourth M.2 connector of the plurality of M.2 connectors.

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

Abstract: This disclosure provides systems and methods for routing and topology management of computer networks with steerable beam antennas. A network controller can generate an input graph for a first time period. The input graph can have a plurality of vertices each representing a respective moving node and a plurality of edges each representing a possible link between a pair of moving nodes. The input graph also can include corresponding location information for each of the moving nodes during the first time period. A solver module can receive information corresponding to the input graph, a maximum degree for each vertex in the input graph, and a set of provisioned network flows. The solver module can determine a subgraph representing a network topology based on the input graph, the maximum degree for each vertex in the input graph, and the set of provisioned network flows, such that a number of edges associated with each vertex in the subgraph does not exceed the maximum degree for each vertex.

Abstract: A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.).

Abstract: An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Abstract: An information handling system may include a plurality of communication destinations, a communication source, a single-source/multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a communication destination respective to such branch, and a logic device communicatively coupled to the communication source and the single-source/multi-destination cable and configured to communicate to each of the plurality of branches both analog source identifying information and digital source identifying information regarding the communication source.

Abstract: Embodiments for providing a timely indication that a wireless transaction has been completed, using a command-based timer solution, are provided. These embodiments include receiving a first command, associated with the wireless transaction, from a reader; initiating, using an applet, a first command-based timer when the first command is received; issuing, using the applet, an activity timeout signal when the first command-based timer expires before a second command is received from the reader; and providing an indication that the wireless transaction has been completed in response to the activity timeout signal. In some embodiments, the command-based timer solution may also include canceling, using the applet, the first command-based timer when the second command is received before the first command-based timer expires; initiating a second command-based timer when the second command is received; and issuing the activity timeout signal when that the second command-based timer expires.

Abstract: A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.

Abstract: A method for improving the performance of applications executed within asynchronous processor architectures. In an embodiment, a method for improving execution time of compiled synchronized source code on an asynchronous processor architecture includes receiving, by a processing system, synchronized source code comprising synchronization instructions to synchronize execution of the synchronized source code on different pipelines of the asynchronous processor architecture. The method also includes analyzing, by the processing system, the synchronized source code to determine whether the synchronized source code includes a broken code condition.

Abstract: A system and method is provided for qualitative analysis of baseband building automation networks. The system may include a processor configured to carry out a plurality of tests on a serial communication network that includes at least one field device that carries out building automation communications on the network. A first test may include: transmitting a series of queries for devices on the network, in which the queries are transmitted at incrementally lower transmission signal levels until message loss is detected; and determining a first lower signal level at which transmissions of queries occur without message loss on the network. In addition, the processor may be configured to determine and output on a display device at least one classification of the relative quality of the network with respect to at least one predetermined scale of relative network quality based at least in part on the first lower signal level.

Abstract: An example embodiment may involve a software application executable on a computing device of a computational instance of a remote network management platform associated with a managed network. The managed network may contain an enterprise resource planning (ERP) system comprised of computing devices of the managed network on which ERP software is executable. The managed network may be granted a number of authorizations to access the ERP system and capabilities thereof. The ERP system may store user-related data for individual users of the managed network who access the ERP system. The software application may communicate with one or more of the ERP clients to access the user-related data, use a set of compliance criteria to identify, within the user-related data, a set of users, and store in memory an indication identifying the set of users as a potential source of non-compliance with the number of authorizations.

Abstract: Described is a baseboard management controller (BMC). The BMC comprises a BMC flash storage storing firmware and an access permission table. The access permission table defines an access control policy for access requests to peripherals communicatively coupled to the BMC. The BMC further comprises an access control chip comprising one or more processors and a write-once memory. The write-once memory stores a copy of the access permission table. The access control chip is configured to manage access to the peripherals using the access permission table.

Abstract: Disclosed is a content wallet device to which a storage device storing a content is connected including a communication unit for communication between the content wallet device and a user terminal device; an encryption unit generating encryption data including a user ID and a password for authentication between the content wallet device and the user terminal device; a switch unit controlling an electrical connection between the storage device and the communication unit; and a reset unit initializing the generated password when the electrical connection between the storage device and the communication unit is released by the switch unit.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for transmitting, as part of a polling loop, a value added services (VAS) command that includes capability data corresponding to a payment terminal. For example, the payment terminal can transmit a VAS command that advertises the payment terminal's capabilities as part of a polling loop. The payment terminal can listen for a response to the VAS command and, after receiving a response, the payment terminal may initiate a VAS protocol. The VAS command can also specify a mode in which the payment terminal is operating, such as a payment-only mode, a VAS mode, a payment-plus-VAS mode, etc.

Abstract: An audio synchronization processing method is provided. The method includes the following steps: receiving an input request signal; in response to receiving the input request signal, starting performing a counting operation according to a basic clock signal; outputting an output request signal according to a sampling-clock signal; in response to outputting the output request signal, stopping performing the counting operation to obtain a counting value; determining whether synchronization has been achieved based on the counting value; and in response to determining that the synchronization has not been reached, adjusting a frequency of the sampling-clock signal according to the counting value.

Abstract: Embodiments are generally directed to techniques for operating a wind turbine of a wind power plant. An associated method comprises determining, using one or more sensors of the wind turbine, a first power production level of the wind turbine; determining, during an unconstrained operation of the wind turbine, one or more available power correction factors using the first power production level; determining, using one or more wind power parameters applied to a predefined model for estimating an available power of the wind turbine, an estimated available power value; adjusting the estimated available power value using the one or more available power correction factors to produce the available power value; and controlling, using the available power value, the wind turbine to produce a second power production level.

Abstract: A method for providing a datum in a receive buffer memory. The method includes storing the datum to be provided in the receive buffer memory, and retrieving an old datum from the receive buffer memory, if the receive buffer memory overflows as a result of storing the datum to be provided.

Abstract: An apparatus according to one aspect of the present invention determines whether or not platoon vehicles can pass through an intersection, and includes: a calculation unit that calculates a first distance, a second distance, and a third distance described below; and a determination unit that determines whether or not the platoon vehicles can pass through the intersection, based on a result of comparison of the first distance with the second and third distances. First distance: a distance from a stop line of the intersection to a position of a leading vehicle at the present time. Second distance: a distance obtained by subtracting a platoon length from a distance of traveling for a remaining green interval at a vehicle speed at the present time. Third distance: a distance required for the leading vehicle to safely stop before the stop line of the intersection, with the vehicle speed at the present time.

Abstract: This patent provides a deadlock-free adaptive routing apparatus, method and computer storage medium for packets in two-dimensional mesh network based on the overlapping virtual network partitioning scheme, including: according to the offset between the source node and the destination node of the packet along the x-dimension or y-dimension, then use the x dimension and the y dimension to partition the two-dimensional mesh network into virtual networks; corresponding to each of the partitioned virtual networks, corresponding packet classes are respectively set, then merge virtual networks; based on the class the packet, inject the packet into the corresponding merged virtual network to route. This routing method balances utilization of the channels and improves efficiency of the data transmission.

Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

Abstract: A message processing system that provides a processing flow, the message processing system comprising an input message consumer configured to consume input messages from an input message queue, where the input messages comprise priority information. The message processing system includes a command producer configured to produce commands for a next step in the processing flow. Each command produced may include a target time determined using priority information extracted from an input message to which that command corresponds. The message processing system comprises a queue for commands. The message processing system further comprises a command consumer configured to select commands that have expired target times from the command queue for processing and consume the selected commands from the command queue.