Intrasystem Connection (e.g., Bus And Bus Transaction Processing) Patents (Class 710/100)
  • Patent number: 10725939
    Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 28, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Atish Ghosh, Mark Gordon, Ken Nagai, Larisa Troyegubova
  • Patent number: 10701748
    Abstract: A communication device may include a wireless interface configured to repeat operating sequentially in a plurality of states including a first state and a second state. The communication device may acquire first information from the wireless interface in a case where the wireless interface operating in the first state sends the first polling signal to a first external device and receives a response signal to the first polling signal from the first external device, and supply a specific signal to the wireless interface in a case where the first information is acquired from the wireless interface, the specific signal being for causing the wireless interface to use, as a duration time period of the second state, a specific time period instead of the second predetermined time period, the specific time period being longer than the second predetermined time period.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Shun Takeuchi
  • Patent number: 10693468
    Abstract: A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 23, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: H. Pooya Forghani-zadeh, George Vincent Konnail, Christopher Adam Opoczynski
  • Patent number: 10661912
    Abstract: Systems, methods, and devices for assigning addresses to a plurality of functional modules carried by a movable object are provided. In one aspect, a method can comprise: (a) transmitting an activation signal from a control module to a functional module of the plurality of functional modules via a first communication interface, thereby activating the functional module for addressing, wherein the plurality of functional modules are each configured to control a component of the movable object; (b) transmitting an addressing signal comprising an address from the control module to each functional module of the plurality of functional modules via a second communication interface different from the first communication interface, thereby causing the address to be assigned to the activated functional module of step (a); and (c) repeating steps (a) and (b) for each functional module, thereby assigning an address to each functional module.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 26, 2020
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Kaihong Lin, Wenlong Xiao, Xiaojian Wan
  • Patent number: 10657092
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Timothy J. Callahan, Hem Doshi, Hooi Kar Loo, Suketu U. Bhatt
  • Patent number: 10649936
    Abstract: An access control apparatus includes a memory, and a processor coupled to the memory and configured to, in response to an access request to a storage device, output an access command through a first path to a first controller among a plurality of controllers that control the storage device, the access command being a command to access the storage device, when no response to the access command to the first controller is received before a predetermined time passes after the output of the access command, control a second controller different from the first controller among the plurality of controllers through a second path coupled to the second controller such that the second controller stops processing executed by the first controller according to the access command, and output the access command through the second path after receiving a response to the control on the second controller.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kyuu Kobashi
  • Patent number: 10642668
    Abstract: A message processing system that provides a processing flow, the message processing system comprising an input message consumer configured to consume input messages from an input message queue, where the input messages comprise priority information. The message processing system includes a command producer configured to produce commands for a next step in the processing flow. Each command produced may include a target time determined using priority information extracted from an input message to which that command corresponds. The message processing system comprises a queue for commands. The message processing system further comprises a command consumer configured to select commands that have expired target times from the command queue for processing and consume the selected commands from the command queue.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 5, 2020
    Assignee: Open Text GXS ULC
    Inventors: Garrett Christopher Young, Timothy Austin Geldart
  • Patent number: 10629284
    Abstract: A semiconductor device preventing reduction of reliability due to the impact of heat after shipment is provided. A semiconductor device of the disclosure includes a built-in self-test circuit 110 and a resistive random-access memory. The built-in self-test circuit 110 includes a reforming information setting part 230 for performing reforming of the resistive random-access memory. When the operation of a forming execution part 220 or a test execution part 210 is performed, a flag is set to “1” for the reforming information setting part 230. Moreover, when a power supply mounted on a circuit board by IR reflow is turned on, the built-in self-test control part 200 references the flag of the reforming information setting part 230, and if the flag is “1”, then the forming execution part 220 executes the reforming of the resistive random-access memory.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 21, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Masaru Yano
  • Patent number: 10620966
    Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Tina C. Zhong, Russell J. Wunderlich, Chih-Cheh Chen, Malay Trivedi
  • Patent number: 10586077
    Abstract: Radio-assisted tamper protection in a HSM electronic device. Radio signals received from one or more network elements on a network are used for determining values of a set of network parameters that identify the electronic device in a predefined state. A tamper detection state signal may be generated responsive to the detected tampering state. The electronic device may be inhibited from operation in response to the tamper detection state signal.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Silvio Dragone, Mircea Gusat
  • Patent number: 10579391
    Abstract: Translation of boot code read request commands from an on-board processor of a system on a chip (SoC) from a bus protocol (e.g., advanced high-performance bus (AHB) protocol) into a sequence of commands understandable by a serial interface of the SoC to read boot code from an off-board (e.g., flash or other non-volatile) memory device. The serial interface of the memory device may include a relatively low pin count (e.g., 5 pins) and boot code of the memory device may be modified after tape-out of the SoC free of necessitating a subsequent tape-out of the SoC.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: March 3, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Erik Schlanger, Eric Devolder, Ashraf Ahmed
  • Patent number: 10572397
    Abstract: An example method to hide a presence of a storage device is provided herein. The method masks the presence of the storage device using a microcontroller that controls a presence bit. The method unmasks the presence of the storage device using the array controller to instruct the microcontroller to change the value of the presence bit after installation is complete.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 25, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Michael S. Bunker, Michael White
  • Patent number: 10565146
    Abstract: An interconnect, and method of handling supplementary data in an interconnect, are provided. The interconnect has routing circuitry providing a plurality of paths, and routing control circuitry to use the plurality of paths to establish routes through the interconnect between source devices and destination devices coupled to the interconnect, to enable system data to be routed through the interconnect between the source devices and the destination devices. The system data relates to functional operation of a system comprising the interconnect, the source devices and the destination devices. At least a subset of the paths are redundant paths whose use by the routing control circuitry provides the system data with resilience to faults when routing the system data through the interconnect.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Arm Limited
    Inventors: Andrew Brian Thomas Hopkins, Sean James Salisbury
  • Patent number: 10552357
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Patent number: 10542571
    Abstract: A wireless communication apparatus including: a specified output device, and a processor coupled to the specified output device and configured to: establish a wireless connection between the wireless communication apparatus and another wireless communication apparatus, and control the specified output device to output an output pattern that is substantially shared with the other wireless communication apparatus so that a corresponding output pattern of the output pattern is output by another specified output device of the other wireless communication apparatus.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hiroyasu Sugano, Eiichi Takahashi, Junichi Yura, Akira Shiba
  • Patent number: 10542125
    Abstract: A method for configuring a computing device to use a communication protocol is provided. The method is performed by a computing device that includes a host processor coupled to a bus processor and to memory. The method includes receiving, by the host processor, a human-readable configuration file that includes parameters for communication using the communication protocol. The method additionally includes generating, by the host processor, at least one data structure based on the parameters in the human-readable configuration file. Additionally, the method includes providing, to the bus processor, memory location associated with the at least one data structure for use in communicating using the communication protocol.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 21, 2020
    Assignee: THE BOEING COMPANY
    Inventors: Ignacio M. Soriano, Ryan T. Greene, Matthew David Burch
  • Patent number: 10536306
    Abstract: Switch units control ON and OFF of communication between a master device and slave devices. Signal levels of communication lines between switch units and slave devices are maintained at a predetermined level. A switch unit in a first stage is turned on and off by a first switch control signal. A switch unit in a second stage is turned on and off by a switch control signal generated based on a level of a communication line in the first stage and the first switch control signal. A switch unit in each of subsequent stages is turned on and off by a switch control signal generated based on a level of a communication line in a preceding stage and a switch control signal in a second preceding stage. A portion of ground short circuit is identified based on states of communication between the master device and the slave devices.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: January 14, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Takuya Kemmochi, Junichi Shimoda, Kazushi Takei, Tomohide Kondoh, Tetsuya Hara
  • Patent number: 10515234
    Abstract: A method for securing a KVM Matrix system by inserting a plurality of input security isolators, each of the input security isolators is placed between a host computer and matrix host adapter of the KVM matrix system to enforce security data flow policy that is applicable for the corresponding host computer. Additionally, a security filter is placed between peripheral devices and a matrix console adapter to enforce security data flow policy that is applicable for the corresponding peripheral devices.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 24, 2019
    Assignee: HIGH SEC LABS LTD.
    Inventor: Aviv Soffer
  • Patent number: 10516625
    Abstract: Examples described herein relate to a network entity on a ring network. In an example, a method includes receiving a first packet by a first network entity via a ring network. It is determined from the first packet that the ring network has a plurality of management entities each claiming a respective network entity. Based on the ring network having the plurality of management entities each claiming the respective network entity, the first network entity is transitioned from an unclaimed state to a dummyclaim state, and the first network entity is isolated from a portion of the ring network.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 24, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Christopher Murray
  • Patent number: 10503671
    Abstract: The present teaching, which includes methods, systems and computer-readable media, relates to controlling access to a shared resource including, for example, a memory unit. The disclosed techniques may include receiving a configuration parameter relating to a relationship between read and write requests that are initiated by concurrent processes and stored in read and write queues, respectively, for accessing the shared resource. The techniques may further include determining, based on the configuration parameter, whether to allow a read request or a write request to be executed using the shared resource, and providing to a concurrent process access to the shared resource for executing the allowed read or write request. Further, upon a completion of executing the allowed read or write request, a return token on a return token queue different from the read and write queues may be received, the return token corresponding to the allowed read or write request.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 10, 2019
    Assignee: Oath Inc.
    Inventors: Jay Hobson, Derek Wang
  • Patent number: 10498451
    Abstract: One example of a removable module includes an optical transceiver, optical cables, electrical cables, a power conditioner, and a housing. The optical transceiver converts optical signals received through an optical cable to electrical signals to distribute to a plurality of computing devices through electrical cables and converts electrical signals received from the plurality of computing devices through the electrical cables to optical signals to transmit through the optical cable. The power conditioner receives power from a system with the removable module installed in the system to provide power to the optical transceiver. The housing encloses the optical transceiver and the power conditioner and includes an air intake port and an air exhaust vent. The housing is received by a bay of the system, which provides an interface to the power conditioner and provides air to the air intake port with the removable module installed in the system.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: December 3, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin B Leigh, John Norton
  • Patent number: 10474602
    Abstract: The present disclosure relates to a distributed console server system. The system may have a server and a software module loaded onto the server for communications with a plurality of remote devices within a data center. A remote serial port unit may be included which is in communication with the server and which is controlled in part by the server and the software module. The remote serial port unit may be in communication with the plurality of remote devices. The remote serial port unit may include at least one of a first module including a plurality of RJ45 ports, or a second module including a plurality of USB ports.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 12, 2019
    Assignee: Vertiv IT Systems, Inc.
    Inventors: Dante Kanki, Marcelo E. Peccin
  • Patent number: 10459864
    Abstract: Methods and systems for synchronizing USB 2.0 isochronous IN and OUT transfer clocks over a non-USB network. One method for synchronizing isochronous IN transfer clocks includes: receiving, by a USB host adaptor (USBH), packets from a USB host; writing in each packet an indication of the time in which the packet was received by the USBH; sending the packets from the USBH to a USB device adaptor (USBD) over the network; and synchronizing the USBD clock to the USBH clock based on a property related to the received packets.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 29, 2019
    Assignee: Valens Semiconductor Ltd.
    Inventors: Eyran Lida, Aviv Salamon
  • Patent number: 10461742
    Abstract: The invention is directed to the selectable mode buffer circuit including a plurality of pads, a mode selecting circuit, and a control circuit. The mode selecting circuit has a plurality of switches, coupled to the pads, and performs a charge pumping operation or an interfacing operating by changing on or off status of at least one of the switches according to a mode selecting signal. The control circuit receives the mode selecting signal, and generates a plurality of input signals for controlling the switches according to the mode selecting signal.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 29, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventor: Chun-Hung Chen
  • Patent number: 10437761
    Abstract: According to an example of managing a universal serial bus (“USB”), a device connected to a USB hub controller is sensed and a USB information scheme from the device is fetched. A power requirement of the device is determined through the USB information scheme, and a total power consumption of a plurality of devices connected to the USB hub controller is calculated. USB information scheme data to display to a user and a data display arrangement are determined, and a monitor scalar is instructed to display the USB information scheme in the determined data display arrangement. Power to the device is distributed based on the total power consumption of all devices connected to the hub controller and a user setting.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: October 8, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Wen Shih Chen
  • Patent number: 10432423
    Abstract: A method, a device, and a computer program for operating a data processing system, including at least two nodes that are connectable via a data line for transmitting messages. A message includes an identifier for arbitrating messages to be transmitted, the identifier containing—information concerning a priority via which a processing sequence of messages ready for transmission is determined, and the identifier—containing information concerning a network node, via which a sender of the message is unambiguously determined, and—containing information concerning a service, via which a service is determined.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 1, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Marco Andreas Wagner, Michael Poehnl, Timo Lothspeich
  • Patent number: 10430367
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include: a plurality of processor sockets, each processor socket configured to receive a respective processor; a plurality of slots, each slot configured to receive a corresponding information handling resource; and a program of instructions embodied in non-transitory computer-readable media. The program of instructions may be configured to, when read and executed by one of the respective processors identify a processing node for handling a processing load of an information handling resource to be inserted into one of the slots, determine slots within a proximity domain of the processing node, and identify the slots within the proximity domain of the processing node as optimal slots for insertion of the information handling resource to be inserted.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: October 1, 2019
    Assignee: Dell Products L.P.
    Inventors: Mukund P. Khatri, Srinivas Giri Raju Gowda
  • Patent number: 10425082
    Abstract: An integrated analog and digital adaptive platform includes: a plurality of adaptive analog blocks, each of the plurality of adaptive analog blocks being integrated with a respective digital wrapper; and a programmable digital fabric configured to programmably connect one or more of the plurality of adaptive analog blocks by connecting a plurality of digital wrappers integrated with the one or more of the plurality of adaptive analog blocks. The plurality of adaptive analog blocks that are programmably connected using the programmable digital fabric provide one or more programmable analog functions.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: September 24, 2019
    Assignee: AnDAPT, Inc.
    Inventors: Kapil Shankar, Thomas Chan, Patrick J. Crotty, John Birkner
  • Patent number: 10417164
    Abstract: A synchronous transmission device includes a first communication port, a first bus instance and a second bus instance. The first communication port is connected to the first endpoint and the second endpoint. The first bus instance executes a first data transmission with the first endpoint according to a first node of a first schedule list. The first node corresponds to the first endpoint, and the first bus instance corresponds to the first communication port. When the first data transmission is executed, the first bus instance is further configured to determine whether the second bus instance is idle. When the second bus instance is idle, the first bus instance controls the second bus instance to execute a second data transmission with the second endpoint according to a second node of the first schedule list. The second node of the first schedule list corresponds to the second endpoint.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 17, 2019
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventors: Chin-Lung Wu, Wei-Yun Chang
  • Patent number: 10409835
    Abstract: Data-manipulation-language statements can target data in data store of a data storage system. Data manipulations specified in a statement, including in-place manipulations, can be recorded and maintained. Application of data manipulations to the store can be avoided or potentially initiated at a later time. Prior to application of the data manipulations to the data store, queries over data in the data store can be processed in view of the recorded data manipulations and data acquired from the data store, such that the data manipulations are reflected in the data acquired from the data store.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: September 10, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Nikhil Teletia
  • Patent number: 10409635
    Abstract: Provided are a method and terminal for switching systems and/or application programs. The method includes: receiving a notification and/or event from a second system and/or application during the operation process of a first system and/or application program, and then switching to the second system and/or application program; when it is determined that the notification and/or event is ended, judging whether running processes of all systems and/or application programs in the second system and/or application program are ended; when it is determined that the running process of any one of system and/or application program is not ended, switching to the one of system and/or application program, when it is determined that the running processes of all of systems and/or applications are ended, switching to the first system and/or application program.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 10, 2019
    Assignee: DONGGUAN YULONG TELECOMMUNICATION TECH CO., LTD.
    Inventor: Jingen Sheng
  • Patent number: 10404846
    Abstract: A communication system for a mobile computing device that provides for personal communication. A housing of the communication system provides a receiving aperture for accepting the mobile computing device. An upper wall and lower wall of the housing guide the mobile computing device into the housing towards an interior wall. An audio data transmission system enables communication between the mobile computing device with the audio input and the audio output. Insertion of the mobile computing device into the housing connects the mobile computing device with the communication system. Upon connection with the communication system, the mobile computing device outputs audio to the external audio output. The mobile computing device also receives audio captured by the audio input.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 3, 2019
    Assignee: TECH FRIENDS, INC.
    Inventors: Bobby L. Shipman, Jr., Bryan Taylor, Jason Cochran
  • Patent number: 10402223
    Abstract: A heterogeneous computing system can include a host memory and a host processor. The host memory is configured to maintain a write task queue and a read task queue. The host processor is coupled to the host memory and a processing device. The host processor is adapted to store write tasks in the write task queue. The write tasks cause transfer of input data to the processing device. The processing device is adapted to perform offloaded functions. The host processor is adapted to store read tasks in the read task queue. The read tasks cause transfer of results from the offloaded functions from the processing device. The host processor is further adapted to maintain a number of direct memory access (DMA) worker threads corresponding to concurrent data transfer capability of the processing device. Each DMA worker thread is preconfigured to execute tasks from the write task queue or the read task queue.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventors: Sonal Santan, Soren T. Soe
  • Patent number: 10397021
    Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Martin Kessler, William Hooper, Lewis F. Lahr
  • Patent number: 10387053
    Abstract: Regions of memory in a distributed computing system may be synchronized. A first computing node may comprise a processor writing to a memory via a memory controller. A request to write data to the memory may be received by the memory controller. The memory controller may send a signal to a logic device which forwards the signal to other computing nodes in the distributed system. The memory controller may detect and respond to conflicting writes by instructing the computing nodes to overwrite conflicting memory regions with a data pattern indicative of the conflict.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 20, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Andrea Olgiati
  • Patent number: 10381336
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 10372654
    Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 6, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Ishimi
  • Patent number: 10362175
    Abstract: A network telephone device, an external connection card, and a communication method therefor are provided. The network telephone device includes a controller, a network connection port, a network transmission module and a relay. The relay is coupled between the controller and at least two of a plurality of pins of the network connection port. While an external network cable connected to the network connection port is not capable of supplying power over Ethernet (POE) or a power supply mode of the POE is a first mode of the POE, the relay connects a transmit node and a receive node of the controller to the at least two of the pins respectively. The controller and an external device connected to the external network cable transmit signals compatible with a universal asynchronous receiver/transmitter (UART) interface to transmit data or instructions with each other through the at least two of the pins of the network connection port.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: July 23, 2019
    Assignee: Wistron Corporation
    Inventor: Li-Chun Lu
  • Patent number: 10361934
    Abstract: Embodiments of a device and method are disclosed. A controller area network (CAN) device includes a compare module configured to interface with a CAN transceiver, the compare module having a receive data (RXD) interface configured to receive data from the CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD interface, and an identifier memory configured to store an entry that corresponds to at least one identifier, and compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal when the comparison indicates that the received identifier of the CAN message matches the entry that is stored at the CAN device. The CAN device also includes a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 23, 2019
    Assignee: NXP B.V.
    Inventors: Bernd Uwe Gerhard Elend, Peter Michael Buehring, Matthias Berthold Muth
  • Patent number: 10356504
    Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lior Amarilio, Terrence Brian Remple
  • Patent number: 10346336
    Abstract: The disclosed invention is to provide a semiconductor device enabling it to access an internal device within a USB cable in a simple way. Disclosed is a semiconductor device which is able to be coupled to at least one USB cable and which includes a decision unit that decides whether or not an opposite-end device is detected through the USB cable; and a control unit that, if the decision unit has judged that the opposite-end device is not detected through the USB cable, supplies one of two signal lines which are coupled to an internal device within the USB cable with a power supply voltage and implements control of communication with the internal device within the USB cable through the other one of the signal lines.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masashi Tominaga
  • Patent number: 10347355
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 10346225
    Abstract: Techniques for renaming a module in a module system are disclosed. It is determined that a first module is declared with a corresponding first module name. It is determined that the first module is associated with a second module name. Responsive to determining that the first module is associated with the second module name: a second module declared with the second module name is synthesized, and a dependency of the second module, with the second module name, is declared on the first module with the first module name.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Oracle International Corporation
    Inventors: Alexander R. Buckley, Alan Bateman
  • Patent number: 10313231
    Abstract: A method of identifying a path for forwarding a packet by a packet forwarding element. The method receives a packet that includes a plurality of fields that identify a particular packet flow. The method computes a plurality of hash values from the plurality of fields that identify the particular packet flow. Each hash value computed using a different hash algorithm. Based on the plurality of hash values, the method identifies a plurality of paths configured to forward the packets of the particular flow. The method identifies the status of each of the plurality of paths. Each path status identifies whether or not the corresponding path is operational. The method selects an operational path in the plurality of paths to forward the packet based on a priority scheme using said plurality of identified status bits.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 4, 2019
    Assignee: BAREFOOT NETWORKS, INC.
    Inventor: Patrick Bosshart
  • Patent number: 10296257
    Abstract: A control device according to an embodiment includes a first memory, a controller, a communication unit, and a second memory. The second memory stores a table with which an input area and an output area can be identified within the memory area. The controller sets the input areas to a first predetermined area in one transmission process based on the table when the first data is transmitted from a buffer area which a buffer memory has to the memory area, and sets the output areas to the first predetermined area in one transmission process based on the table when the first data is transmitted from the memory area to the buffer area.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 21, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Motohiko Okabe
  • Patent number: 10298546
    Abstract: Robust security of copyright-protected content is provided when such content is digitally stored in a storage device of a client device in encrypted form. The copyright-protected content is encrypted by a server device using a private key and a corresponding public key is used for decryption by the client device. Because access to the private key cannot be determined from the corresponding public key, and because the private key and public key are based at least in part on a unique ID number embedded in the data storage device, decryption can only be performed by the data storage device in the client device. In some embodiments, robust security of private data stored in a server device is provided using a similar public-key/private-key pair and encryption scheme.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 10296432
    Abstract: Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Karthikeyan Avudaiyappan, Brian McGee
  • Patent number: 10289477
    Abstract: An embodiment of an electronic marker circuit for a USB cable may be configured to detect and error condition on one or more of the USB signals and apply a signal to one of the USB signal that is representative of the cable being disconnected from a source or sink device even if the cable is still physically connected.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 14, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Christian Klein
  • Patent number: 10262627
    Abstract: Mechanisms for managing output of an HDMI source are provided. In accordance with some implementations of the disclosed subject matter, a method for controlling output of an HDMI source is provided, the method comprising: establishing a connection between the HDMI source and an HDMI sink at a first address of a consumer electronic control bus of the HDMI sink; sending a request for an identity of the active source connected to the HDMI sink; monitoring signals on the consumer electronic control bus; receiving a message over the consumer electronic control bus identifying a second address on the consumer electronic control bus different from the first address as an address of an active source; setting a status of the HDMI source as inactive in response to receiving the message; and inhibiting output of video from the HDMI source to the HDMI sink in response to the status being set as inactive.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 16, 2019
    Assignee: Google LLC
    Inventor: Eric Jason Roberts
  • Patent number: 10261927
    Abstract: A DMA controller includes a built-in timing sequence generator that allows the DMA controller to trigger data movement periodically and/or non-equidistantly, without waking a CPU or other peripherals.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: April 16, 2019
    Assignee: NXP USA, INC.
    Inventors: Wangsheng Mei, Gang Shi, Kun Wu