Abstract: A vehicle management device including request information reception means for receiving request information for platooning multiple vehicles; implementation feasibility assessment means for assessing an implementation feasibility of a platoon based on the request information; and implementation permission means for permitting implementation of the platoon based on a result of assessing of the implementation feasibility.

Abstract: A method of identifying a path for forwarding a packet by a packet forwarding element. The method receives a packet that includes a plurality of fields that identify a particular packet flow. The method computes a plurality of hash values from the plurality of fields that identify the particular packet flow. Each hash value computed using a different hash algorithm. Based on the plurality of hash values, the method identifies a plurality of paths configured to forward the packets of the particular flow. The method identifies the status of each of the plurality of paths. Each path status identifies whether or not the corresponding path is operational. The method selects an operational path in the plurality of paths to forward the packet based on a priority scheme using said plurality of identified status bits.

Abstract: A system and method are provided for facilitating efficient management of data structures stored in remote memory. During operation, the system receives a request to allocate memory for a first part in a data structure stored in a remote memory associated with a compute node in a network. The system pre-allocates a buffer in the remote memory for a plurality of parts in the data structure and stores a first local descriptor associated with the buffer in a local worker table stored in a volatile memory of the compute node. The first local descriptor facilitates servicing future access requests to the first and other parts in the data structure. The system stores a first global descriptor for the buffer in a shared global table stored in the remote memory and generates a first reference corresponding to the first part, thereby facilitating faster traversals of the data structure.

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

Abstract: An integrated circuit can be used to regulate data flow in a computing system. The integrated circuit can receive input data via a first interface associated with a first type of bus protocol and provide output data via a second interface associated with a second type of bus protocol. Size of the input data and the output data may vary based on the corresponding protocols. The integrated circuit can receive, via the first interface, an input data size for a write transaction to store the input data in a data storage unit. The integrated circuit can also receive a requested data size, via the second interface, to provide the output data for a read transaction. The integrated circuit can also generate an actual size of the output data based on the requested data size, the input data size, and size of the stored input data.

Abstract: An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Abstract: A management server executes interval adjustment processing to adjust a service frequency of a ride-sharing vehicle group. In the interval adjustment processing, it is judged whether or not a vehicle pair composed of two vehicles in a relationship of a preceding vehicle and a following vehicle includes a stopping vehicle that stops in a pick-up and drop-off point as a following vehicle. Further, it is judged whether or not the vehicle pair corresponds to a separated pair. If it is judged that vehicle pair includes the stopping vehicle as the following vehicle and the said vehicle pair corresponds to the separated pair, selection processing to select an overtaking vehicle is executed. The overtaking vehicle is a ride-sharing vehicle that overtakes with the stopping vehicle to cut into between the separated pair. An overtake instruction is transmitted to the overtaking vehicle selected by the selection processing.

Abstract: A method for operating a data bus subscriber of a local bus, particularly of a ring bus, the method including the steps of: receiving a first data packet over the local bus, wherein the first data packet has an address of the data bus subscriber to which it is directed and at least one instructions list, having a set of instructions for processing process data, receiving a second data packet over the local bus, wherein the second data packet has process data; and executing instructions of the at least one instructions list for processing the received process data. A corresponding data bus subscriber and a local bus master is also provided.

Abstract: An embodiment electronic system comprises a first device, a second device and a clock generator circuit. The clock generator circuit is configured to provide a clock signal having a selectable frequency. The first device comprises a first processing circuit having coupled therewith a first Ethernet interface, and the second electronic device comprises a second processing circuit having coupled therewith a second Ethernet interface. At least one of the first device and the second device is configured to determine a frequency of the clock signal as a function of an operating parameter of the first device and/or of the second device and/or as a function of a parameter of the frames exchanged between the first device and the second device, and to act on the clock generator circuit to operate the clock generator circuit at the frequency.

Abstract: One embodiment is directed to a master unit for a distributed antenna system (DAS). The master unit comprises one or more donor cards and one or more transport cards, and at least one passive backplane. Each passive backplane comprises a plurality of backplane connectors. Each backplane connector is configured to connect a respective donor card or transport card to the passive backplane. Each backplane connector is connected to each of the other connectors via one or more respective passive bi-directional backplane channels. The master unit is configured so that all active processing of streams of digital samples transported via the DAS is performed by the donor cards and transport cards and not the passive backplane.

Abstract: A circuit structure with automatic PCIe lane configuration adjustment and a method thereof are disclosed. The circuit structure includes a plurality of PCIe riser cards and a motherboard. The PCIe riser cards are of at least two lane sizes each associated with a PCIe size identifier. The motherboard includes a plurality of PCIe ports, a CPLD module, a storage unit, a BMC module and a BIOS unit. The PCIe ports are electrically connected to the respective PCIe riser cards via a plurality of PCIe cables. The CPLD module is electrically connected to the PCIe ports so as to be able to read the PCIe size identifiers thereof and determine current configuration information from a comparison between the PCIe size identifiers and present signals.

Abstract: An information handling system, including two or more single-slot M.2 modules; a dual-slot discrete graphics processing unit (dGPU) module; a printed circuit board, including: a plurality of M.2 connectors aligned on a same edge of the printed circuit board such that: a first single-slot M.2 module of the two or more single-slot M.2 modules is coupled to a first M.2 connector of the plurality of M.2 connectors; a second single-slot M.2 module of the two or more single-slot M.2 modules is coupled to a second M.2 connector of the plurality of M.2 connectors; and the dual-slot dGPU module is coupled to a third and a fourth M.2 connector of the plurality of M.2 connectors.

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

Abstract: This disclosure provides systems and methods for routing and topology management of computer networks with steerable beam antennas. A network controller can generate an input graph for a first time period. The input graph can have a plurality of vertices each representing a respective moving node and a plurality of edges each representing a possible link between a pair of moving nodes. The input graph also can include corresponding location information for each of the moving nodes during the first time period. A solver module can receive information corresponding to the input graph, a maximum degree for each vertex in the input graph, and a set of provisioned network flows. The solver module can determine a subgraph representing a network topology based on the input graph, the maximum degree for each vertex in the input graph, and the set of provisioned network flows, such that a number of edges associated with each vertex in the subgraph does not exceed the maximum degree for each vertex.

Abstract: A Multi-Purpose Dynamic Simulation and run-time Control platform includes a virtual process environment coupled to a physical process environment, where components/nodes of the virtual and physical process environments cooperate to dynamically perform run-time process control of an industrial process plant and/or simulations thereof. Virtual components may include virtual run-time nodes and/or simulated nodes. The MPDSC includes an I/O Switch which delivers I/O data between virtual and/or physical nodes, e.g., by using publish/subscribe mechanisms, thereby virtualizing physical I/O process data delivery. Nodes serviced by the I/O Switch may include respective component behavior modules that are unaware as to whether or not they are being utilized on a virtual or physical node. Simulations may be performed in real-time and even in conjunction with run-time operations of the plant, and/or simulations may be manipulated as desired (speed, values, administration, etc.).

Abstract: An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.

Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Abstract: An information handling system may include a plurality of communication destinations, a communication source, a single-source/multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a communication destination respective to such branch, and a logic device communicatively coupled to the communication source and the single-source/multi-destination cable and configured to communicate to each of the plurality of branches both analog source identifying information and digital source identifying information regarding the communication source.

Abstract: Embodiments for providing a timely indication that a wireless transaction has been completed, using a command-based timer solution, are provided. These embodiments include receiving a first command, associated with the wireless transaction, from a reader; initiating, using an applet, a first command-based timer when the first command is received; issuing, using the applet, an activity timeout signal when the first command-based timer expires before a second command is received from the reader; and providing an indication that the wireless transaction has been completed in response to the activity timeout signal. In some embodiments, the command-based timer solution may also include canceling, using the applet, the first command-based timer when the second command is received before the first command-based timer expires; initiating a second command-based timer when the second command is received; and issuing the activity timeout signal when that the second command-based timer expires.

Abstract: A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.

Abstract: A method for improving the performance of applications executed within asynchronous processor architectures. In an embodiment, a method for improving execution time of compiled synchronized source code on an asynchronous processor architecture includes receiving, by a processing system, synchronized source code comprising synchronization instructions to synchronize execution of the synchronized source code on different pipelines of the asynchronous processor architecture. The method also includes analyzing, by the processing system, the synchronized source code to determine whether the synchronized source code includes a broken code condition.

Abstract: A system and method is provided for qualitative analysis of baseband building automation networks. The system may include a processor configured to carry out a plurality of tests on a serial communication network that includes at least one field device that carries out building automation communications on the network. A first test may include: transmitting a series of queries for devices on the network, in which the queries are transmitted at incrementally lower transmission signal levels until message loss is detected; and determining a first lower signal level at which transmissions of queries occur without message loss on the network. In addition, the processor may be configured to determine and output on a display device at least one classification of the relative quality of the network with respect to at least one predetermined scale of relative network quality based at least in part on the first lower signal level.

Abstract: Described is a baseboard management controller (BMC). The BMC comprises a BMC flash storage storing firmware and an access permission table. The access permission table defines an access control policy for access requests to peripherals communicatively coupled to the BMC. The BMC further comprises an access control chip comprising one or more processors and a write-once memory. The write-once memory stores a copy of the access permission table. The access control chip is configured to manage access to the peripherals using the access permission table.

Abstract: An example embodiment may involve a software application executable on a computing device of a computational instance of a remote network management platform associated with a managed network. The managed network may contain an enterprise resource planning (ERP) system comprised of computing devices of the managed network on which ERP software is executable. The managed network may be granted a number of authorizations to access the ERP system and capabilities thereof. The ERP system may store user-related data for individual users of the managed network who access the ERP system. The software application may communicate with one or more of the ERP clients to access the user-related data, use a set of compliance criteria to identify, within the user-related data, a set of users, and store in memory an indication identifying the set of users as a potential source of non-compliance with the number of authorizations.

Abstract: Disclosed is a content wallet device to which a storage device storing a content is connected including a communication unit for communication between the content wallet device and a user terminal device; an encryption unit generating encryption data including a user ID and a password for authentication between the content wallet device and the user terminal device; a switch unit controlling an electrical connection between the storage device and the communication unit; and a reset unit initializing the generated password when the electrical connection between the storage device and the communication unit is released by the switch unit.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for transmitting, as part of a polling loop, a value added services (VAS) command that includes capability data corresponding to a payment terminal. For example, the payment terminal can transmit a VAS command that advertises the payment terminal's capabilities as part of a polling loop. The payment terminal can listen for a response to the VAS command and, after receiving a response, the payment terminal may initiate a VAS protocol. The VAS command can also specify a mode in which the payment terminal is operating, such as a payment-only mode, a VAS mode, a payment-plus-VAS mode, etc.

Abstract: An audio synchronization processing method is provided. The method includes the following steps: receiving an input request signal; in response to receiving the input request signal, starting performing a counting operation according to a basic clock signal; outputting an output request signal according to a sampling-clock signal; in response to outputting the output request signal, stopping performing the counting operation to obtain a counting value; determining whether synchronization has been achieved based on the counting value; and in response to determining that the synchronization has not been reached, adjusting a frequency of the sampling-clock signal according to the counting value.

Abstract: Embodiments are generally directed to techniques for operating a wind turbine of a wind power plant. An associated method comprises determining, using one or more sensors of the wind turbine, a first power production level of the wind turbine; determining, during an unconstrained operation of the wind turbine, one or more available power correction factors using the first power production level; determining, using one or more wind power parameters applied to a predefined model for estimating an available power of the wind turbine, an estimated available power value; adjusting the estimated available power value using the one or more available power correction factors to produce the available power value; and controlling, using the available power value, the wind turbine to produce a second power production level.

Abstract: A method for providing a datum in a receive buffer memory. The method includes storing the datum to be provided in the receive buffer memory, and retrieving an old datum from the receive buffer memory, if the receive buffer memory overflows as a result of storing the datum to be provided.

Abstract: An apparatus according to one aspect of the present invention determines whether or not platoon vehicles can pass through an intersection, and includes: a calculation unit that calculates a first distance, a second distance, and a third distance described below; and a determination unit that determines whether or not the platoon vehicles can pass through the intersection, based on a result of comparison of the first distance with the second and third distances. First distance: a distance from a stop line of the intersection to a position of a leading vehicle at the present time. Second distance: a distance obtained by subtracting a platoon length from a distance of traveling for a remaining green interval at a vehicle speed at the present time. Third distance: a distance required for the leading vehicle to safely stop before the stop line of the intersection, with the vehicle speed at the present time.

Abstract: This patent provides a deadlock-free adaptive routing apparatus, method and computer storage medium for packets in two-dimensional mesh network based on the overlapping virtual network partitioning scheme, including: according to the offset between the source node and the destination node of the packet along the x-dimension or y-dimension, then use the x dimension and the y dimension to partition the two-dimensional mesh network into virtual networks; corresponding to each of the partitioned virtual networks, corresponding packet classes are respectively set, then merge virtual networks; based on the class the packet, inject the packet into the corresponding merged virtual network to route. This routing method balances utilization of the channels and improves efficiency of the data transmission.

Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

Abstract: A message processing system that provides a processing flow, the message processing system comprising an input message consumer configured to consume input messages from an input message queue, where the input messages comprise priority information. The message processing system includes a command producer configured to produce commands for a next step in the processing flow. Each command produced may include a target time determined using priority information extracted from an input message to which that command corresponds. The message processing system comprises a queue for commands. The message processing system further comprises a command consumer configured to select commands that have expired target times from the command queue for processing and consume the selected commands from the command queue.

Abstract: A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.

Abstract: A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.

Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element. The instructions may further configure the processor to classify the USB element as only a producer of power, evaluate whether an enumeration process is initiated within a timeout period, and if so, assign the USB element as a USB host.

Abstract: A traffic signal control apparatus capable of controlling signal light colors at a target intersection and a downstream intersection, and includes: an acquisition unit configured to acquire a platoon length of platoon vehicles that are traveling on an inflow road of the target intersection, and an empty space length in a planned traveling route of the platoon vehicles; and a control unit configured to determine whether or not to control the signal light color at the downstream intersection corresponding to the planned traveling route of the platoon vehicles, according to a result of comparison between the platoon length and the empty space length.

Abstract: A mainboard and a server are provided. The mainboard includes: a board body, a preset number of Purley platform central processors, and one or more memories. The preset number of Purley platform central processors and the one or more memories are installed on the board body. The Purley platform central processors are sequentially connected with each other, and each of the memories is connected to one of the Purley platform central processors. Each of the memories is configured to receive to-be-burned data inputted from outside and transmit the to-be-burned data to the Purley platform central processor connected with the memory. Each of the Purley platform central processors is configured to burn the to-be-burned data when receiving the to-be-burned data transmitted by the connected memory connected with the Purley platform central processor, to have a function corresponding to the to-be-burned data.

Abstract: Multicast expert system information dissemination systems and methods making use of artificial intelligence are provided. The systems and methods include a wireless device for receiving RF multicast information messages from a content provider wherein said information is descriptive of objects potentially of interest to users of the device. Received multicast messages may include information parameters about objects of potentially interest to the user. The wireless device also includes a knowledge base prestored in the wireless device descriptive of the user's level of interest in various objects. Artificial intelligence expert system control is used to evaluate a combination of the user's level of interest in the object information and distance from the user to the location where the object may be obtained. The artificial intelligence expert system derives a user advisory action index. In one embodiment the artificial intelligence may be implemented using fuzzy logic inference engine apparatus.

Abstract: An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.

Abstract: An aspect includes receiving a write request at a storage device. The write request includes data and is received from a file system executing on a host computer communicatively coupled to the storage device. A storage location on the storage device for the data is selected by the storage device based at least in part on characteristics of the storage device. The data is stored at the storage location on the storage device. A write completion message is sent to the file system confirming that the write of the data has been completed. The write completion message includes an identifier of the storage location.

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can be determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

Abstract: An interface control circuit includes an interface wrapper, a logic circuit, a multiplexer and a command decoder. The interface wrapper transceives a plurality of first signals in a first interface, converts the first signals to a plurality of second signals in a second interface, and generates at least one first command signal according to the first signals. The logic circuit receives the second signals, and generates a second command signal according to the second signals. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal and generates the decoded command according to the third command signal.

Abstract: A modular I/O system for an industrial automation network includes a network adapter including first and second adapter modules, wherein each adapter module is configured for connection with an industrial network. The I/O system further includes a first I/O device with first and second I/O modules each configured for operative connection to a controlled system for input/output of data with respect to the controlled system. The I/O system further includes first and second independent backplane data networks that connect each of the first and second adapter modules to each of the first and second I/O modules. The network adapter includes first and second removable backplane network switches and the first I/O device includes third and fourth removable backplane network switches that establish the backplane networks. The backplane network switches can be Ethernet gigabit switches.

Abstract: An information processing device includes a first processor core of 2n-bits unit, a second processor core of n-bit(s) unit, a DRAM set including a first DRAM and a second DRAM of n-bit(s) unit, a first transmitting path between the first processor core and the DRAM set, a second transmitting path between the second processor core and the first or second DRAM, a transmitting path switching circuit, and a power supply controlling circuit. In normal operation, with switching to the first transmitting path and supplying power to the first processor core and the first and second DRAMs, the first processor core uses the first and second DRAMs. In power saving operation, with switching to the second transmitting path, supplying power to the second processor core and the first DRAM and stopping power to the first processor core and the second DRAM, the second processor core uses the first DRAM.

Abstract: A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

Abstract: Embodiments relate to coordinating the operations of subsystems in a communication system of an electronic device where a coexistence hub device monitors the state information transmitted as coexistence messages over one or more multi-drop buses, processes the monitored coexistence messages and sends out control messages as coexistence messages to other systems on chips (SOCs). The coexistence hub device can also update the operations of the communication system. The coexistence hub device may receive an operation policy from a central processor and may execute the operation policy without further coordination of the central processor. The coexistence hub device broadcasts the control messages as coexistence messages according to the executed operation policy.

Abstract: Described herein are several embodiments relating to modular irrigation controllers. In many implementations, the irrigation controllers are modular in that various functional components of the irrigation controller are implemented in removable modules that when inserted into position within the controller, expand the capabilities of the controller. Also described are various different types of expansion modules that may be coupled to the modular controller, having as variety of functions and features, as well as related methods of use and configuration of these modules in the controller. In some embodiments, a serial communication bus is provided between a control unit of a modular irrigation controller and an expansion module.