Abstract: A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register.

Abstract: An information processing apparatus includes a processing unit and a control unit connected with the processing unit through a transmission line. The processing unit has multiple devices including a predetermined low-speed device. The control unit has a processing circuit that issues access to the multiple devices of the processing unit, and the processing unit has a communication circuit that receives the access to the multiple devices through the transmission line and a queue that buffers the access, when the received access is to the predetermined low-speed device.

Abstract: A CAN system includes a plurality of CAN modules and a CAN bus connecting the CAN modules. In at least one embodiment, a filter device is mounted between at least one CAN module and the CAN bus, by which CAN messages transported via the CAN bus and destined for the at least one CAN module can be filtered.

Abstract: A command generating and monitoring system includes a command processor configured to determine a command data set from a command input. A monitoring processor is coupled to the command processor and is configured to generate an authentication key by comparing the command data set received from the command processor to a comparison command data set generated by the monitoring processor. A data bus is coupled to the command processor and the monitoring processor. The data bus is configured to receive the command data set and the authentication key for retrieval by a consuming device.

Abstract: A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.

Abstract: Provided are a method, system, and program for managing path groups to an Input/Output (I/O) device. Indication is made of a connection path on which a processing system initially communicated an establish request to establish a connection with an I/O device, wherein attention that the processing system may own a lock for the I/O device is transmitted down the indicated connection path. A request is received from the processing system to add a path to a path group with respect to the I/O device, wherein the added path is capable of comprising the connection path the processing system used to establish the connection with the I/O device. The received path is added to the path group.

Abstract: An electronic apparatus includes a first board that includes a first processor, a second board that is connected to the first board with a bus and that includes a second processor, and a disconnecting/connecting unit that, when the first board is in a first state in which power of the first processor is turned off and the second board is in a second state in which power of the second processor is turned on, disconnects a signal supplied via the bus between the first board and the second board.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: Techniques to prevent interruption of operations performed by an I/O device. One advantage may be that the I/O device does not need to re-establish its interrupted operation (and waste the associated time to re-establish its interrupted operation). Accordingly, bus utilization efficiency may be improved.

Abstract: A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information.

Abstract: The present invention extends to methods, systems, and computer program products for managing network response buffering behavior. A computer system receives a request for content from a client. The computer system has a default response buffering behavior used when transferring content. The computer system maps the request to a handler configured to serve the requested content. The computer system accesses buffering behavior data for the handler. The computer system determines that the requested content is to be transferred in accordance with altered response buffering behavior based at least on the buffering behavior data. The altered response buffering behavior corresponds to the requested content as an exception to the default response buffering. The computer system accesses a portion of the requested content from the handler. The computer system transfers the portion of requested content to the client in accordance with the altered response buffer behavior.

Abstract: A computing system having a host device and at least one client device having a lock used to prevent modification of data in the client device. A lock clear signal from the host device causes the client device to clear a lock used to prevent modification of data stored in at least a protected portion of the client device where the client device remains fully operational.

Abstract: To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnection, the data caching control units are divided into plural control clusters, each of the control clusters including at least two or more data caching control units, control of a cache memory is conducted independently for each of the control clusters, and one of the plural data caching control units manages, as a single system, protocol transformation units and the plural control clusters based on management information stored in a system management information memory unit.

Abstract: A method for transmitting data in packets between a first circuit element and a second circuit element includes sending the data by the first circuit element followed by a reception and a storage of the data by the second circuit element. A data transmission flow control operation detects an event signaling an imminent state of congestion of the data stored by the second circuit element. In response thereto, the control operation stops the sending of the data from the first circuit element to the second circuit element until a delay period expires and the event is no longer detected.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: A method for protecting a dynamically reconfigurable computing system includes generating an encoding key and passing the encoding key, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library contains a plurality of functions for selective programming into the at least one field programmable logic device. A lock is generated so as to prevent external resources with respect to the system from accessing the encoding key during the passing thereof.

Abstract: A multi CPU system is capable of performing exclusive control of a plurality of CPUs accessing to the same resource by a hardware without depending on an OS. The plurality of CPUs are connected with the same system bus. A plurality of circuits one-to-one correspond to each of the plurality of CPUs and comprise respective semaphore acquisition registers. Each of the CPUs in accessing to the resource is controlled, based on the value written in the semaphore acquisition register of the corresponding circuit, the presence or absence of the priority in the semaphore control, and a semaphore signal received from the another circuit.

Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

Abstract: A method to resolve a deadlock in a bus architecture comprising a first and a second single-envelope bus with at least one master and one slave each, where the first and second single-envelope buses are arranged on different sides of an asynchronous boundary and are coupled via a bus bridge, said method comprising the steps of: granting the bus to a first master arranged on a first side of the asynchronous boundary which requests a transaction within a critical time window; monitoring the bus which has been granted for transaction to the first master; stealing silently the bus from the first master if a deadlock condition arises; granting the bus to a second master arranged on a second side of the asynchronous boundary raising the deadlock condition by requesting a second transaction within the critical time window; completing the second transaction to resolve the deadlock scenario; and returning back the bus to the first master to complete the first transaction.

Abstract: A method of tamper-resistant configuration control for a system, the method comprising reading a flag from a memory of an electronic device, the flag indicating an enable/disable state of at least one component device of the electronic device, setting a register in memory to a disable state for the at least one component device in response to the flag indicating a disabled state for the at least one component device, and locking the register.

Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Abstract: The integrated circuit comprises: —an on-chip access right manager (40) to grant or deny access to a memory segment to a peripheral device (10) according to predetermined access rights upon reception of a read instruction from the peripheral device, —an on-chip lock (50) connected to a memory data bus, the lock being controllable by the access tight manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted.

Abstract: A mechanism is provided for locking an end device for the period of time that the device is needed, thus disabling access by any other application or process. Having the device locked, rather than the bus, allows other applications to use the bus to access other devices at the same time. This is achieved by providing a virtual bus arbitration, which arbitrates applications' use of the physical bus. The virtual bus arbitration algorithms allow bus operations from different applications to overlap on the physical bus as long as their target devices and associated bus locks are on different end devices.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: The object of the present invention is to make information necessary for judging whether control output is possible closer to the latest information than in the conventional method or made the latest, and shorten the time from control start to control execution. In a control and monitoring system for a power system which controls monitoring control objects by supplying a control instruction from a master unit 6 to a plurality of input/output terminal devices BCU1, BCU2, and so on provided for each of the plurality of monitoring control objects in a power system, the master unit 6 starts operations to acquire information necessary for judging whether control output to the input/output terminal devices BCU1, BCU2, and so on is possible at the time of control object selection notification from the master unit 6 to the input/output terminal devices BCU1, BCU2, and so on.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: The systems and methods manage concurrent access requests to a shared resource. The systems and methods utilize an access management algorithm that permits multiple processes to concurrently obtain shared locks on the shared resource, but also limits access to only one process when an exclusive lock is granted. In doing so, the systems and methods avoid the problems of starvation and deadlock.

Abstract: Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for communicating with the memory and a secondary bus. A synchronization block is coupled to the secondary bus of each of the plurality of processors. The synchronization block includes at least one semaphore for controlling access among the plurality of processors to at least one data segment stored within the memory.

Abstract: A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.

Abstract: Locks are placed in a convert queue in a way that compensates for queue bias. Rather than always placing a remote lock in a queue at the tail, a remote lock can be placed further up in the queue, and possibly be interleaved with local locks. As a result, remote processes are granted locks more frequently and swiftly. Locks are placed in a convert queue according based on queue placement factors, which are factors accounted for when placing a lock in a queue.

Abstract: A docking station for a wireless mouse includes an output for communicating with a computer and a mouse detector for detecting when the mouse is docked in the docking station. The docking station is configured to transmit a signal to the computer to automatically deactivate the computer when the mouse is docked in the docking station.

Abstract: A method and apparatus for managing the execution on guest processors of a broadcast instruction requiring a corresponding operation on other processors of a guest machine. Each of a plurality of processors on an information handling system is operable either as a host processor under the control of a host program executing on a host machine or as a guest processor under the control of a guest program executing on a guest machine. The guest machine is defined by the host program executing on the host machine and contains a plurality of such guest processors forming a guest multiprocessing configuration. A lock is defined for the guest machine containing an indication of whether it is being held by a host lock holder from the host program and a count of the number of processors holding the lock as guest lock holders. Upon decoding a broadcast instruction executing on a processor operating as a guest processor, the lock is tested to determine whether it is being held by a host lock holder.

Abstract: A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically from a pulse generating circuit. It is assumed that first device outputted first bus request signal and second device continuously outputted second bus request signal before rising timing of the first pulse. When a bus arbiter outputs a bus grant signal to the first device at the rising timing of the first pulse, the bus master of the first device outputs a bus use acknowledgment signal. Then a use grant inhibiting circuit receives the acknowledgment signal and outputs an inhibition signal for inhibiting use of other devices. Thus, the first device holds the use right of a bus and bus use requests of other devices are reserved.

Abstract: To emulate an interrupt architecture in a data processing system, interrupt emulation code receives from an operating system a first call requesting access to a first resource in a first interrupt architecture. In response to receipt by the interrupt emulation code of the first call, the interrupt emulation code maps the first resource to a second resource in interrupt hardware of the data processing system. The mapping operation includes determining an identifier of the second resource in a different second interrupt architecture. The interrupt emulation code then initiates access to the second resource implemented by the interrupt hardware.

Abstract: Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.

Abstract: A method and apparatus for isolating communications ports that allows access to a communications system for status and/or maintenance purposes via one communications port while preventing access to same system via the other remaining communications ports are disclosed. The isolation is achieved by an active isolation circuit that precludes a communication with the communication system as long as a signal generated by that communication system indicates that the port should be actively isolated. One preferred embodiment uses the Data Terminal Ready (DTR) signal as an input to the active isolation circuit to actively isolate the selected communication ports. This abstract is provided as a tool for those searching for relevant disclosures, and not as a limitation on the scope of the claims.

Abstract: An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

Abstract: The invention relates to a method in a hardware semaphore lock (L1–LN) intended for a multi-processor system, which semaphore lock (L1–LN) protects a shared resource (R1–RN) in connection with the system in such a way that only a process which has reserved the semaphore lock (L1–LN) and has thus become a holder of the lock, has access to use the resource protected by the lock. The semaphore lock (L1–LN) is reserved by a single read operation of a memory location representing the semaphore lock by the process software. The read operation returns to the process the number of vacant holder positions, i.e. keyholes vacant at the time of the reservation of the lock. The semaphore lock does not require the support of the system for atomic read/write operations.

Abstract: A method for blocking a request to a front side bus interconnected between a central processing unit (CPU) and a control chip includes the following steps. First, a bus ownership of the control chip is assigned via a bus priority signal line. Any request from the CPU to the front side bus is blocked when the control chip owns the bus ownership. Meanwhile, any request from the control chip to the front side bus is inhibited when the CPU is blocked from outputting any request to the front side bus.

Abstract: In AV deices connected to a network via a digital interface, a connection request given from the outside via the network is rejected within a preset time after a connection state of the network changes.

Abstract: A plurality of arbitration devices is hierarchically coupled and has a plurality of child devices and at least one parent device. Each of the plurality of arbitration devices is operable to store a previous arbitration winner. In addition, the plurality of arbitration devices is operable to generate a request-out signal based on a plurality of request-in signals, and is operable to generate a select-out signal from a select-in signal, a plurality of request-in signals and from the previous arbitration winner. The request-out signals of the plurality of child devices are coupled to request-in signals of their respective parent devices and select-in signals of the child devices are received from select-out signals of the respective parent devices. Access is granted by a select-out signal from a device of the plurality of arbitration devices that resides at the lowest level of the system.

Abstract: A method for reserving an isochronous resource over a link between a first bus and a second bus, the link including a first interface device connected to the first bus and a second interface device connected to the second bus. The reservation of the resources over the link is transparent to the devices connected to the busses. The method includes, at the level of the interface devices, intercepting the connection set up messages sent by the devices connected to the busses, checking whether a source device and a sink device for which the set-up message has been intercepted are on different busses, and in the affirmative, reserving resources for the connection over the link.

Abstract: Structure and methods for preserving lock requests by master devices on multiple buses each coupled to a port of a multiported device. The invention provides for arbitration among multiple ports of a multiported device to preserve the intent of a lock request to retain exclusive control of the bus over an extended period involving multiple bus transactions directed through a corresponding port. In a first exemplary preferred embodiment, an AMBA AHB compliant bus bridge or multiported slave device is coupled through its ports to multiple AHB buses each having one or more master devices coupled thereto. Logic circuits and methods associated with port arbitration for the bus bridge device or multiported slave device preserve the intent of HLOCK requests asserted by master devices on one of the AHB buses coupled to a port to preserve the intent of the lock request through port arbitration within the multiported device.

Abstract: An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.

Abstract: An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.

Abstract: To address the need for a high availability system (100) and method of initializing that address failures that lock up common communication buses (109) in these systems, the present invention avoids powering-up peripheral components (e.g., 102-103) that have previously locked up the bus. It accomplishes this by storing indicators of successful initializations in memory (105), and then subsequently powering-up components only if such an indicator was stored for that component's last power-up.

Abstract: A two-wire serial (TWS) bus allows bus mastering by any device on the bus utilizing pull-ups. The bus is actively driven low, but typically pulled high by pull-up resistors for each device on the bus. When some of the devices on such a bus have backup power, draining of backup power whenever primary power is lost is avoided by isolating the devices with backup power from the devices without backup power on the TWS bus.

Abstract: An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17. The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM) connected to an external bus EXBUS respectively. The bus controllers 15, 16 respectively output external bus use request signals BRQ1 and BRQ2, and obtain the right for using the external bus EXBUS. When the bus controllers 15, 16 end use of the external bus EXBUS, the bus controllers 15, 16 stop to output the external bus use request signals BRQ1 and BRQ2 and output off-time signals OFT1 and OFT2 immediately thereafter.

Abstract: An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

Abstract: Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a resource to a processor, while at the same time, the fast memory of such a processor is maintained in a coherent state. An exemplary structure includes data structures that help to identify the portion of the fast memory of the processor to be maintained in a coherent state. An exemplary method includes a determination of past and present processors that have had access to the resource so as to maintain the coherency of the fast memory of the processor.