Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Abstract: An activation system for at least one receiving device that is redundantly activatable via a first communication network and via at least one second communication network that is independent of the first communication network. The activation system includes at least two transmitting modules, each of which is designed to generate messages for the receiving device and to transmit them to the receiving device via at least one of the communication networks. At least one transmitting module is connectable to both communication networks, and the transmitting modules are coordinated with one another and/or with the receiving device in such a way that messages from one transmitting module are to be transmitted via a communication network and/or processed by the receiving device with priority over messages from another transmitting module.

Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

Abstract: Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

Abstract: A method for detecting an unauthorized physical access to a bus system. The method includes detecting a test level sequence in the voltage signal; constituting a binary sampled pattern by sampling the voltage signal at specified pattern times associated with the detected test level sequence, and assigning a first value if the voltage signal is above a predefined voltage threshold at the respective pattern time, and a second value if the voltage signal is not above the voltage threshold; comparing the sampled pattern with a reference pattern that is associated with the detected test level sequence and that was constituted for the test level sequence as a sampled pattern in a state of the bus system during which no unauthorized access existed; and determining that a possible unauthorized physical access exists if the reference pattern does not match the sampled pattern.

Abstract: The disclosure relates to a safety module for an automation system assembly, having a safety component which is configured to implement a safe operation of the automation system assembly, and an adaptation component which is configured to mediate between the safety component and a communication system of the automation system assembly in order to incorporate the safety module into the automation system assembly, wherein the safety component and the adaptation component are constructed on separate circuit carriers and are connected in such a way that they are mechanically detachable and reconnectable.

Abstract: The systems and methods are configured to efficiently and effectively access memory. In one embodiment, a memory controller comprises a request queue, a buffer, a control component, and a data path system. The request queue receives memory access requests. The control component is configured to process information associated with access requests via a first narrow memory channel and a second narrow memory channel. The first narrow memory channel and the second narrow memory channel can have a portion of command/control communication lines and address communication lines that are included in and shared between the first narrow memory channel and the second narrow memory channel. The data path system can include a first data module and one set of unshared data lines associated with the first memory channel and a second data module and another set of unshared data lines associated with second memory channel.

Abstract: Zero copy message reception for devices is disclosed. For example, a host has a memory, a processor, a supervisor, and a device with access to device memory addresses mapped in a device page table via an IOMMU. An application has access to application memory addresses and is configured to identify a first page of memory addressed by an application memory address to share with the device as a receiving buffer to store data received by the device for the application, where the first page is mapped to a first device memory address in a first device page table entry (PTE). A supervisor is configured to detect that the first application has disconnected from the device, and in response to detecting the application disconnecting, to update the first device PTE to address a second page instead of the first page.

Abstract: A system on a chip, including a first domain having a first processor, a first local memory coupled to the first processor, wherein the first local memory having a first memory format and a first sub-network coupled to the first processor, a second domain having a second processor, a second local memory coupled to the second processor and a second sub-network coupled to the second processor, wherein the second local memory having a second memory format which differs from the first memory format, a multi-tier network coupled to the first sub-network and the second sub-network, a global memory coupled to the multi-tier network and a multi-port DDR controller coupled to the global memory to receive, transmit and share the first local memory having the first memory format and the second local memory having the second memory format based on a predetermined criteria.

Abstract: A relay device in a communication system receives a plurality of wakeup frames from one or more than one communication device connected to each bus of a plurality of buses via a corresponding port. The relay device obtains an aggregated wakeup pattern by aggregating information on an operating mode of each communication device included in the plurality of wakeup frames so as to include predetermined information to be transmitted and received and reduce the number of wakeup patterns. By using the aggregated wakeup pattern obtained by aggregating the information on the operating mode, a wakeup frame for transmission to each bus via the corresponding port is prepared.

Abstract: An interface/electronics module for reading information from a vehicle data bus and controlling functions available through the vehicle data bus. A graphical user interface is provided. The interface may include a stand-alone tablet computer or may be part of an integrated and permanently-mounted display. The interface/electronics module may include the functionality of the factory audio system (such as a radio tuner, power amplifier, etc.). In addition, the interface/electronics module is able to transmit commands via the vehicle's CAN bus.

Abstract: A circuit provides for processing and routing peer-to-peer (P2P) traffic. A bus request queue store a data request received from a first peer device. A decoder compares an address portion of the data request against an address map to determine whether the data request is directed to either a second peer device or a local memory. A bus interface unit, in response to the data request being directed to the second peer device, 1) generates a memory access request from the bus request and 2) transmits the memory access request toward the second peer device via a bus. A memory controller, in response to the data request being directed to a local memory, accesses the local memory to perform a memory access operation based on the data request.

Abstract: A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.

Abstract: Plural Internet of Things (IoT) gateways detect, secure against and remediate malicious code with an autonomous communication of tokens between the IoT gateways on a time schedule. Detection of an invalid token or a token communication outside of a scheduled time indicates that malicious code may have interfered with token generation or communication. Verification of a token communication to an IoT gateway that failed in turn to pass the token to another IoT gateway indicates that the IoT gateway is a threat that may include malicious code.

Abstract: Embodiments of the present disclosure seek to mitigate the timing issues of prior approaches by performing the NVMe device reset and post-reset re-initialization in parallel. In embodiments, the NVMe device reset and re-initialization operations are logically divided into front-end and back-end operations that may be carried out in parallel. Upon receipt of the command from a host to reset, the NVMe device carries out front-end reset operations for resetting the device, and in parallel performing back-end reinitialization operations. Once the front-end reset operations are complete, or after a predetermined period of time, the NVMe device reports to the host that the device reset is complete, while back-end operations continue. Once all reset and reinitialization operations are complete, the NVMe device may continue to conduct I/O instructions from the host.

Abstract: Apparatus and methods for controlling unmanned systems (UMSs), such as unmanned aircraft, are provided. A UMS can be provided that includes a network, auxiliary systems, and a payload, where the network can connect the auxiliary systems and the payload. A network switch of the network can logically separate the network into at least a second tier of communications and a third tier of communications. The network can be used to control the UMS by at least: controlling the auxiliary systems using messages communicated by the second tier of communications, and communicating with the payload using messages communicated by the third tier of communications.

Abstract: A method comprising: identifying, by a resource manager, a resource of a storage system, the resource being one which a testing system lacks permission to use for testing the storage system; adding, by the resource manager, the resource to a group of resources which the testing system is permitted to use for testing the storage system, wherein adding the resource to the group includes granting the testing system a temporary permission to use the resource for testing the storage system; allocating the resource to a test that is performed by the testing system; and removing, by the resource manager, the resource from the group wherein removing the resource from the group includes revoking the temporary permission.

Abstract: Identifying a first controller and a second controller each connected to a computing device over a first serial bus for monitoring of the computing device; allocating, at the first controller, i) a first internal register bit of a first register indicating an arbitration status of the first controller with respect to the computing device and ii) a second internal register bit of the first register indicating an arbitration status of the second controller with respect to the computing device; allocating, at the second controller, i) a third internal register bit of a second register indicating the arbitration status of the first controller with respect to the computing device and ii) a fourth internal register bit of the second register indicating the arbitration status of the second controller with respect to the computing device.

Abstract: An interface connection method applied to a connection device. The connection device is configured to connect a host end having a first connection interface and a device end having a second connection interface. The interface connection method includes determining a voltage level of a detection pin; performing a first initialization when the detection pin is at a low level; providing an electrical power for detecting whether the electrical power is consumed or not when the detection pin is at a high level; sending a link signal when the electrical power is consumed; and performing a second initialization when the device end is detected to be in a ready state.

Abstract: In some embodiments, a method stores a plurality of requests for routes in a queue based on respective priorities for the routes. The plurality of requests are for programming destinations and next hops for the destinations in a route table that is used by a device in a network to route packets. The method selects a request for a route from the queue based on a respective priority for the queue. Then, the request for the route is sent to an entity to program the route in the route table.

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract: A control system includes a master device and one or a plurality of slave devices connected to the master device via a field network. In a storage unit of each slave device, a node address is arranged in a unique region for each model of the slave devices. The control system further includes an information providing part which provides, in any slave device, information for specifying the region in which the node address is stored in the storage unit to the master device.

Abstract: A method for verification of content of tape cartridges in a tape library system using tape drives of the tape library, is provided. The method includes instructing the tape drive to perform tape cartridge verification on the tape cartridge. The method further includes after completion of the tape cartridge verification, unloading the tape cartridge to its original storage position. The method further includes transmitting verification data of the tape cartridge verification to a database of the tape library system for analysis.

Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.

Abstract: A radio access network (RAN) node is provided for a small cell of a wireless access network having a coaxial line. The RAN node includes an input operably coupled with the coaxial line and an output configured to wirelessly communicate with at least one user equipment device within an operable vicinity of the wireless access network. The RAN node further includes a transmission path configured to (i) connect the input to the output, and (ii) communicate a first radio frequency (RF) signal from the input to the output, and a reception path separate from the transmission path, and configured to (i) connect the output to the input, and (ii) communicate a second radio frequency (RF) signal from the output to the input. The RAN node is configured to dynamically switch between the transmission path and the reception path in response to a tone received from the wireless access network.

Abstract: A system for authenticating messages transmitted on a bus based on physical location of transmitting units, comprising a reflector adapted to inject a plurality of reflection signals at a first point of a line topology bus, each in response to each of a plurality of messages transmitted by a plurality of bus connected units and a probe adapted to intercept the messages and the reflection signals at a second point of the bus. The probe calculates propagation timing between a reception time of the message and a reception time of an associated reflection signal transmitted in response to the message and determines validity of the message according to a match between the calculated propagation timing and a predefined propagation timings associated with the bus connected units. Wherein the bus connected units are statically connected to the bus between the first point and the second point.

Abstract: An aircraft for fixed pitch lift includes a fuselage, a plurality of flight components attached to the fuselage, wherein the plurality of flight components further comprises at least a lift propulsor component, wherein the lift propulsor component comprises a plurality of blades configured at a fixed angle of attack, and a pusher component, wherein the pusher component is configured to produce a forward thrust.

Abstract: A host interconnection device includes a serializing module, an analysis module, an arbitration module, a data-writing tracking module, and a data-reading tracking module. The serializing module serializes at least one first read/write request generated by at least one processing module and a second read/write request generated by a chipset module, and outputs the first read/write request or the second read/write request. The analysis module generates analysis information according to the first read/write request or the second read/write request. The arbitration module arbitrates the analysis information and snoop information, and generates arbitration information. The data-writing tracking module performs a data-writing tracking operation on the arbitration information to generate a first snoop request, a data-writing indication, and a data-writing request.

Abstract: Methods and apparatus relating to heterogeneous compute architecture hardware/software co-design for autonomous driving are described. In one embodiment, a heterogeneous compute architecture for autonomous driving systems (also interchangeably referred to herein as Heterogeneous Compute Architecture or “HCA” for short) integrates scalable heterogeneous processors, flexible networking, benchmarking tools, etc. to enable (e.g., system-level) designers to perform hardware and software co-design. With HCA system engineers can rapidly architect, benchmark, and/or evolve vehicle system architectures for autonomous driving. Other embodiments are also disclosed and claimed.

Abstract: Aspects of the disclosure relate to token-based authentication mechanism. A user token device may receive a first token from an authentication platform. The user token device may store the first token in a personal token chain corresponding to a user. The user token device may receive a token request, where the token request comprises an indication of a source. The user token device may retrieve, from memory, one or more second tokens that are assigned to the source and transmit the one or more second tokens to the authentication platform. The authentication platform may authenticate the user based on the received one or more second tokens.

Abstract: A moving target defense scheme for a serial communications system is disclosed herein. A bus controller generates and broadcasts a nonce to remote terminals over a bus. The bus controller and the remote terminals generate a randomized sequence based upon the nonce and a shared secret that is shared between the bus controller and the remote terminals. The bus controller broadcasts first messages over the bus on first addresses that are derived from first portions of the randomized sequence. The remote terminals listen for the first messages that are broadcast over the bus on the first addresses. The bus controller broadcasts a shift message that causes the remote terminals to listen for second messages that are broadcast over the bus on second addresses that are derived from second portions of the randomized sequence.

Abstract: A storage system and method for determining ecosystem bottlenecks and suggesting improvements are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller comprises a plurality of hardware components, at least one of the hardware components configured to communicate with the memory; a plurality of busses connecting the hardware components; a plurality of monitors, wherein each monitor is configured to collect information on utilization of a respective one of the plurality of busses; and a processor in communication with the plurality of monitors, wherein the processor is configured to: analyze the information on utilization of the busses collected from the plurality of monitors; and provide a result of the analysis to a device external to the storage system.

Abstract: The present invention provides an electronic controller and the like capable of identifying the order of communication apparatuses connected to a bus while minimizing manufacturing cost. In the present invention, bus wiring 2 has one end connected to a port 111 and the other end connected to a port 112. A plurality of lower ECUs 301 to 304 are connected to the bus wiring 2. A current sensor CS measures current Is1 flowing through the port 111 and current Is2 flowing through the port 112 by applying current to the bus wiring 2 from each of the plurality of lower ECUs 301 to 304. The higher controller 12 identifies the order of the plurality of lower ECUs 301 to 304 on the bus wiring 2 on the basis of the current Is1 and the current Is2 which are measured for each of the plurality of lower ECUs 301 to 304.

Abstract: According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.

Abstract: A method for a cloud-computing system to communicatively couple with a remote terminal unit (RTU) that monitors and/or controls one or more operations a well device associated with a hydrocarbon well may include receiving, via at least one processor, a request from an asset attempting to communicatively couple with the cloud-computing system. The method may then include determining whether the asset is known and receiving one or more attributes regarding the asset when the asset is not known. After receiving the attributes, the method may include determining whether a profile that corresponds to the one or more attributes exists and sending configuration data to the asset based on the profile when the profile exists.

Abstract: The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.

Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link.

Abstract: Embodiments of the invention provide system and method for storage and management of confidential information. The system comprises at least one electronic device, wherein each electronic device is configured to store confidential information, and execute a service request using the confidential information stored therein; a control system configured to provide power supply to any one of the at least one electronic device, which is connected to the control system, and communicate a service request from a specific user to an electronic device in connected state which is associated with the specific user; and an enclosure configured to house the at least one electronic device, and the control system.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: A memory system having memory components and a processing device to: receive, from a host system, write commands to store data in the memory components; store the write commands in a buffer; execute at least a portion of the write commands; determine an amount of available capacity of the buffer that becomes available after execution of at least the portion of the write commands; receive, from the host system, a request for information about available capacity of the buffer; and determine whether to transmit a response signal corresponding to the request based at least in part on the amount of available capacity.

Abstract: A memory system includes a memory chip, a queue block and a memory controller. The queue block is configured to store a command to be transmitted to the memory chip. The queue block includes a first queue and a plurality of second queues each corresponding to a plane of the memory chip. The memory controller is configured to determine whether or not a first command enqueued in the first queue is a first read command. The first read command is a command for executing read operation in the planes asynchronously. When the first command is the first read command, the memory controller transfers the first command to one of the second queues corresponding to a plane in which the first command is to be executed. The memory controller selects the first queue or the second queues as a source of a command to be transferred to the memory chip.

Abstract: A communication apparatus includes: a transmitting unit that is capable of transmitting data to a designated destination through any of plural communication interfaces; a storage unit in which plural pieces of destination information are stored; and a registration unit that registers a communication interface used for data transmission in advance for each of the plural pieces of destination information stored in the storage unit.

Abstract: An information handling system may include at least one processor and a network interface controller communicatively coupled thereto. The network interface controller may be configured to provide network communication between the information handling system and a remote information handling system according to a Server Message Block (SMB) protocol. The information handling system may further be configured to establish a communication session with the remote information handling system according to a first SMB channel having a first bandwidth, and in response to an indication from the remote information handling system, transition the communication session to a second, different SMB channel having a second bandwidth greater than the first bandwidth.

Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal.

Abstract: A job assignment apparatus includes a processor configured to perform assignment of a first job to a first arithmetic device and a second arithmetic device in such a way that data is transmitted in a first direction, the first job being processed in a process algorithm in which a plurality of arithmetic devices sequentially transmit data, the first arithmetic device being connected to the second arithmetic device via a first switch and a second switch, the first direction being a direction from the first switch to the second switch, and perform assignment of a second job to a third arithmetic device and a fourth arithmetic device in such a way that data is transmitted in a second direction, the third arithmetic device being connected to the fourth arithmetic device via the first switch and the second switch, the second direction being a different direction from the first direction.

Abstract: Managing input/output (‘I/O’) queues in a data storage system, including: receiving, by a host that is coupled to a plurality of storage devices via a storage network, a plurality of I/O operations to be serviced by a target storage device; determining, for each of a plurality of paths between the host and the target storage device, a data transfer maximum associated with the path; determining, for one or more of the plurality of paths, a cumulative amount of data to be transferred by I/O operations pending on the path; and selecting a target path for transmitting one or more of the plurality of I/O operations to the target storage device in dependence upon the cumulative amount of data to be transferred by I/O operations pending on the path and the data transfer maximum associated with the path.

Abstract: A memory controller and data storage device include a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to an external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via an SRAM bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data in the internal memory device.