Abstract: A wheel end computer, WEC, (220) for hosting and executing one or more motion support device abstraction modules (MSDA, 221) configured to monitor and/or to control operations of one or more respective motion support devices, MSDs, (240, 250, 260, 270) on a heavy duty vehicle, where an MSDA provides a control and/or a monitoring interface between an external vehicle unit computer (VUC, 210), and a respective MSDs operational functionality, wherein the WEC (220) is arranged to identify a matching MSDA for each MSD in a set of MSDs, such that each MSD connected to the WEC is matched to a respective MSDA, and wherein the WEC (220) is arranged to receive a monitor and/or a control command from the VUC (210) for monitoring and/or controlling an MSD connected to the WEC, and to control the MSD via the respective matching MSDA.

Abstract: A method for providing teleportation services includes receiving, by a computing device, a first signal. The first signal indicates a request for a teleportation event between a first quantum computing system (QCS) and a second QCS. A first set of qubits is associated with the first QCS. A second set of qubits is associated with the second QCS. In response to receiving the first signal, the computing device causes an allocation of a first qubit of the first set of qubits for the teleportation event. In response to receiving the signal, the computing device causes an allocation of a second qubit of the second set of qubits for the teleportation event. The computing device receives a second signal that indicates a successful completion of the teleportation event. In response to receiving the second signal, the computing system causes a deallocation of the first qubit of the first set of qubits.

Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.

Abstract: Systems and methods are disclosed for implementing enhanced security measures that include utilizing a backup database included on node devices connected to a CAN bus, so that certain message identifiers are updated according to a matching table stored on the backup database. By updating the message identifiers, outside attackers will not be privy to the new message identifier assigned to the messages and will no longer target such messages.

Abstract: A centralized access control circuit includes a memory, a sub-circuit, and a memory controller. The memory includes a plurality of lock bits mapped to a plurality of bytes of a peripheral register included in a peripheral. The sub-circuit receives, from a processor core, an access request to access a set of bytes of the plurality of bytes. The sub-circuit grants a first level of access privilege to the processor core based on an identifier of the processor core and an address of the set of bytes included in the access request. The memory controller receives the access request and grants, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core. The processor core accesses the set of bytes based on the first and second levels of access privileges.

Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Abstract: A stream processor is disclosed, the stream processor includes: a first in first out memory FIFO, a calculation unit, and a cache. The FIFO receives current stream information, where the current stream information carries a target stream number and target data; when the FIFO receives a read valid signal, the FIFO sends the target stream number and the target data to the calculation unit, and sends the target stream number to the cache; the cache obtains, based on the target stream number, old data that corresponds to the target stream number, and sends the old data that corresponds to the target stream number to the calculation unit; and the calculation unit performs, based on the target data, calculation on the old data that corresponds to the target stream number to obtain new data, and sends the new data to the cache.

Abstract: Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions. The block-based processor core includes execution control logic and core state access logic. The execution control logic can be configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode. The core state access logic can be configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core during the debug mode.

Abstract: Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip.

Abstract: An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.

Abstract: A server apparatus accesses a terminal apparatus connected via an IP network to a router from an externally provided terminal apparatus in a simple and firm manner without previously performing a complex setting operation.

Abstract: An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Abstract: In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each response having an associated tag, and the responses received are sent to the one or more devices based on the corresponding linked list and the corresponding tag.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: An image forming apparatus includes a storage unit, an arbitration unit that controls access to the storage unit, and a plurality of image processing units that are connected to the arbitration unit and access the storage unit via the arbitration unit. And, an operation analysis apparatus includes: an access monitoring unit monitoring which of the image processing units the arbitration unit permits access to the storage unit; a log generation unit generating, in response to the fact that the access monitoring unit detects that the image processing unit with access permitted has been switched, information on the image processing unit with access permitted as a log; a log storage unit storing therein the generated log; and a remaining capacity determination unit determining whether the storage capacity of the log storage unit after storing the log has become equal to or smaller than a particular capacity.

Abstract: Processor-to-processor (P-P) and/or broadcast proxies may be designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.

Abstract: A message is received at a communication interface device coupled to a first media type. A second layer (e.g., a dynamic link layer (DLL)) on the communication interface device communicates with an abstraction layer (AL) regarding relaying of the message. The AL determines whether another communication interface device should relay the message via a second media type. When the AL determines that another communication interface device cannot or should not relay the message, the communication interface device relays the message using relaying functionality provided by the second layer (e.g., the DLL). When the AL determines that another communication interface device should relay the message, the AL forwards the message to the other the communication interface device for relaying via the second media type.

Abstract: Techniques are disclosed to provide arbitration between input ports and output ports of a switch. For each of at least one input port of a group of input ports, a respective request is received specifying for the respective input port to be allocated a clock cycle in which to send data to a group of output ports. A grant of the request of a primary input port is issued at each clock cycle, the primary input port including a first input port of the at least one input port. Upon a determination, subsequent to a first clock cycle count elapsing, that an input arbiter has not yet accepted any grant of the request of the primary input port, a grant is issued at each clock cycle, including alternating between issuing a grant of the request of the primary input port and of an alternate input port, respectively.

Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: A storage tiered that satisfies desired performance is configured by recognizing the type and capacity of storage media of a storage apparatus, which are held by a user, and using the storage media.

Abstract: Embodiments relate to first-in-first-out (FIFO) queue based command spreading. An aspect includes receiving a plurality of commands by a first level priority stage of a memory control unit (MCU), wherein each of the plurality of commands is associated with one of a plurality of ports located on a buffer chip. Another aspect includes storing each of the plurality of commands in a FIFO queue of a plurality of FIFO queues in the MCU, wherein each of the plurality of commands is assigned to a FIFO queue based on the command's associated port, and each of the plurality of FIFO queues is associated with a respective one of the plurality of ports located on the buffer chip. Another aspect includes selecting a FIFO queue of the plurality of FIFO queues and forwarding a command from the selected FIFO queue to the buffer chip by the second level priority stage.

Abstract: A host computer accesses a federated storage volume at first and second frames (physical storage assemblies). The host identifies a preferred frame by (1) obtaining representative values of a performance metric for sets of paths to the volume, each set associated with a different frame, and (2) selecting the frame associated with the path set having the best representative value. In one example a response latency is used to detect different distances to the host and identify the closer frame, which will be preferred. Operating modes of the paths for non-preferred frames are set to “standby”. During subsequent operation using path selection to send storage operations to the volume, the host selects among paths in an “active” operating mode so as to access the volume at the preferred frame under normal operating condition. Standby paths are reserved for less normal operating conditions, such as when no active path is available.

Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract: Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

Abstract: Exemplary method embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.

Abstract: Exemplary system and computer program embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.

Abstract: A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.

Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

Abstract: An interface system which is adapted to a portable device is provided. The interface system includes a control chip, a first peripheral device, an external interface port, a first, a second, a third bus driver and a control unit. The control chip provides at least a first and a second interface port. The first bus driver has a first, a second input port and an output port. The first bus driver is used to interface the first input port with the output port or interface the second input port with the output port according to a first control signal. The second bus driver is used to interface the first interface port with the external interface port or interface the output port with the external interface port according to a second control signal. The third bus driver is used to interface the first peripheral device with the second input port or interface the second interface port with the first peripheral device according to the first control signal.

Abstract: Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: An apparatus comprising a first sub-arbiter circuit and a second sub-arbiter circuit. The first sub-arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. The second sub-arbiter circuit may be configured to determine a winning channel received from the plurality of channel requests based on a second criteria. The second sub-arbiter may also be configured to optimize the order of the winning channels from the first sub-arbiter by overriding the first sub-arbiter if the second criteria creates a more efficient data transfer.

Abstract: The methods and apparatuses of the present invention for efficiently providing file information in a portable device with limited screen size. When a plurality of files contain substantially identical file information, the present invention utilizes the file information that is different to distinguish from other files.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.

Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.

Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.

Abstract: In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality of superordinate hierarchical bus circuits, access requests from respective bus masters included in each corresponding bus master group are arbitrated according to priority levels assigned thereto, and based on the result of the arbitration, a priority communication signal PRA/PRB indicating a priority level of each access-request-permitted bus master is fed to a subordinate bus controller. In a subordinate hierarchical bus circuit, under control of the subordinate bus controller, access request arbitration is carried out according to the priority communication signal PRA/PRB to select a superordinate hierarchical bus circuit or bus master having the highest priority level.

Abstract: Method for rapidly detecting identifier (ID) of tags, by radio frequency identification (RFID) reader in communication system that includes RFID reader and at least two tags communicating with RFID reader, is provided. RFID reader generates a prefix when IDs contained in at least two messages received collide with each other, prefix including a first colliding bit, which is set to ‘0’ or ‘1’, from high-order bits and non-colliding high-order bits. RFID reader sends a first message containing information that requests transmission of an assigned ID in a preset transmission period when the bits of the generated prefix match bits corresponding to the prefix, in the assigned ID. Tags receive a first message that contains a prefix including at least one bit, and sends a second message containing an assigned ID during a preset transmission period when the bits of the prefix match bits corresponding to the prefix, in assigned ID.

Abstract: Embodiments related to arbitration are described and depicted.

Abstract: A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system operations including activation processing and application processing and an operation clock information circuit or the like that becomes effective when a SoC bus region is divided by an operation clock frequency are utilized in assignment of priority of buses of the system arbiter. Thus, the information transfer efficiency of the whole system bus and the information transfer efficiency of every transfer originator can be improved.

Abstract: A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.

Abstract: Systems and methods are provided for modularly constructing a software defined radio (“SDR”). Given an SDR kernel (i.e., a potentially platform-neutral definition of digital signal processing functionality and control operations necessary to implement the core portion of a software defined radio implementing a particular radio standard), an optional description of governmental regulations for a particular locality, and an interface harness providing the necessary components for interfacing to specific communication channels and devices (including SDR hardware components), an SDR factory component performs a process of constructing an SDR software component for implementing a particular radio standard on a particular host. The SDR software component may additionally construct components which restrict the operation of the resulting SDR software component.

Abstract: A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.