Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: The present invention provides a display driving circuit and a display device. The display driving circuit comprises a timing controller and a driving chip, and the timing controller comprises a first generation module and a first timing module. The first generation module is connected with the first timing module and the driving chip respectively, and configured to generate a row starting signal for triggering the first timing module to start timing and the driving chip which is idle to turn on. The first timing module is connected with the driving chip, and configured to trigger the driving chip which is idle in a non-effective pixel display duration to turn off, in case a current timing duration equals to an effective pixel display duration. The display driving circuit can prevent an idle driving chip from staying in the on-state and consuming power, so that current requirements for energy saving against a display device can be satisfied, and the quality of display device can be improved.(FIG.

Abstract: Aspects of the disclosure provide a circuit including an encoding circuit and a valid circuit. The encoding circuit is configured to encode data to be transmitted as signals on a data bus to satisfy a requirement that limits a number of bit transitions between consecutive transmissions. The valid circuit is configured to selectively corrupt the signals not to satisfy the requirement that limits the number of bit transitions between the consecutive transmissions to indicate whether the signals to be transmitted on the data bus constitute valid data or invalid data.

Abstract: Non-address data is received that is to be transmitted on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium.

Abstract: Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in parallel, determine preliminary DBI bits based on a block of data. Individual preliminary DBI bits are associated with respective sub-blocks of the block of data. The DBI circuit is further configured to serially determine DBI bits based on the preliminary DBI bits. Individual ones of the DBI bits are associated with respective ones of the sub-blocks. The DBI circuit is further configured to invert bits of individual sub-blocks responsive to the respective associated DBI bits having a particular logical value to provide DBI data. The apparatus further includes data outputs configured to serially output sub-blocks of the DBI data and the DBI bits.

Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.

Abstract: Techniques are disclosed to provide arbitration between input ports and output ports of a switch. For each of at least one input port of a group of input ports, a respective request is received specifying for the respective input port to be allocated a clock cycle in which to send data to a group of output ports. A grant of the request of a primary input port is issued at each clock cycle, the primary input port including a first input port of the at least one input port. Upon a determination, subsequent to a first clock cycle count elapsing, that an input arbiter has not yet accepted any grant of the request of the primary input port, a grant is issued at each clock cycle, including alternating between issuing a grant of the request of the primary input port and of an alternate input port, respectively.

Abstract: Systems and methods for encoding a slot table for a communications controller of a communications network are described. In one embodiment, a method for encoding a slot table for a communications controller of a communications network includes classifying branches of the communications network that are connected to the communications controller into at least one group, where each of the at least one group includes multiple branches, and generating a slot table entry for a time slot for accessing the communications network through the communications controller based on the at least one group. Other embodiments are also described.

Abstract: Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.

Abstract: The invention relates to an immersive vehicle multimedia system that that is affected by vehicle sensors and collected data concerning environmental. The immersive vehicle multimedia system includes a vehicle, at least one sensor or other vehicle component gathering input as data from an external and internal vehicle environment, an immersive multimedia device connected to each sensor, and media content run through the multimedia device. The media content includes a primary script and a secondary script, the secondary script depending on the gathered input.

Abstract: A method operates a bus system for communication with a plurality of communication nodes, in particular in a land vehicle and/or aircraft. A static, cyclically recurring time window of fixed length each communication node is assigned a time slot for transmission of user information of a byte count that can be specified at least once and fixed during the operation of the bus system. The time window has at least two cohesive sub-time windows. The same byte count is specified for all time slots of a sub-time window.

Abstract: A reception apparatus that receives data through a plurality of lanes and includes a plurality of buffers that store received data, the buffers being provided for each of the plurality of lanes; a speed difference controller outputs a first timing signal for adjusting timing among the lanes, based on a communication speed on the lanes and operational clocks for the transmission apparatus and the reception apparatus; a deskew controller that outputs a second timing signal for adjusting a skew among the lanes; and a controller that adjusts timing for reading the received data from the buffers, based on a value of the second timing signal and a difference between a read position for reading the received data from the buffers and a write position for writing the received data to the buffers, in the first timing signal, upon adjusting a frequency difference between the transmission apparatus and the reception apparatus.

Abstract: A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: Multiple components on a programmable chip are interconnected using a shared bus fabric. Each component has an interface with multiple input lines including an input valid line, an input ready line, and an input data line and multiple output lines including an output valid line, an output ready line, and an output data line. Positive valid latency is provided on the input side while positive ready latency is provided on the output side. Adapters are inserted automatically between components to allow implementation of interfaces without buffers.

Abstract: A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel.

Abstract: Provided is a conveyance control system in which fast and smooth control is realized without causing a control delay by a processing delay of a control apparatus such as a PLC, and wiring between a control object and a central control unit is omitted. A conveyance control system according to the present invention includes a plurality of data processing slave stations connected through a common transmission line. The data processing slave station obtains information about a predetermined station from monitor/control data about a plurality of stations of the data processing slave station transmitted to the common transmission line, determines and adjusts control/monitoring of an own station and outputs information about an own station to the common transmission line. The information about an own station output to the common transmission line from the data processing slave station is obtained by a different station as part of the monitor/control data to become a control/monitor factor of the different station.

Abstract: Method and device for arbitration for time division multiple access using delta-sigma modulation for an integrated circuit are described. A method for arbitrating access to a shared resource among multiple devices includes obtaining a first arbitration factor. The first arbitration factor is first delta-sigma modulated to produce a first slot signal. The first slot signal is for Time Division Multiple Access-arbitrated access to the shared resource.

Abstract: A method is described and presented for creation of an optimized schedule for execution of a functionality by means of a time-controlled distributed computer system, in which the distributed computer system and the functionality have a set of (especially structural and functional) elements of at least one element class and the elements are at least partially in a dependence. The method according to the invention, in which the task is solved, is initially and essentially characterized by the fact that the dependences between the elements are recognized, classified and the elements are assigned to corresponding dependence classes, and that optimization of schedule occurs by coordination of elements of at least one dependence class.

Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Abstract: An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period.

Abstract: In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.

Abstract: A network node (1) with a communication unit (2), which is provided for the implementation of a communication protocol for the purpose of communication with other network nodes via a communication medium (5), and with a bus monitor (3), which, mutually independently, each implement an access time schedule contained in a configuration data record, and which each make available, in accordance with the access time schedule, a release signal for a bus driver (4) provided in the network node (1), which evaluates these two signals and, in the event that the two release signals do not coincide, blocks the access of the network node (1) to the communication medium (5).

Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

Abstract: Transmission of probe configuration data is initiated upon recognition by the probe of a prescribed condition. Probe configuration data protocol includes a data frame, subdivided into a desired number of time slots. Unlike measurement data protocol, where inter-pulse pair timing within a slot varies based on a magnet position or temperature sensor resistance, configuration data protocol in accordance with the invention uses fixed inter-pulse timing to represent the various states of digital data. In such manner, at least a portion of the time slots making up the particular data frame can be used for containing data sent from the probe, and which can then be interpreted by the receiving processing device as at least one bit of binary code allocated to each individual slot of the portion of time slots.

Abstract: A method for extracting an original message from a received signal including data bits representing the original message or an inverted version thereof, an indicator indicating whether the data bits represent the original message or the inverted version thereof, and a check information which depends on the data bits and the indicator, the method including determining a check information based on the received data bits and the received indicator, comparing the determined check information with the received check information and extracting the original message based on the result of the comparison.

Abstract: A system and method of broadcasting data to multiple targets across a system bus, such as the peripheral component interconnect (PCI) bus, that does not normally support broadcast transfers, in which one target responds to the bus transaction and the remaining targets listen in on the bus transaction to receive data from the system bus. The responding target stalls the bus transaction when any of the listening targets communicate to the responding target that they are temporarily unable to accept the data on the bus.

Abstract: A processing system includes a shared resource, an arbitration module, and a requesting device for issuing requests to the arbitration module to access the shared resource to perform transactions on the shared resource. The arbitration module grants access to the requesting device for a fixed time duration. The fixed time duration comprises one of a plurality of time durations including a first and a second time duration; the second longer than the first. The requesting device prioritizes performance of the transactions on the shared resource based upon the fixed time duration and types of transactions to be performed. Transaction type comprises one of a plurality of types including a first type that requires a time duration that can be performed within the first time duration and a second type that requires a time duration that exceeds the first time duration but can be performed within the second time duration.

Abstract: A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting patterns of the appearances preceding a qualifying quiet period on the data bus; a qualifying quiet period being a time interval having a duration greater than a predetermined duration with no traffic on the data bus; (c) employing the patterns to determine probability of occurrence of a qualifying quiet period following at least one pattern; and (d) permitting the second bus controller to control operation of the data bus during a respective qualifying quiet period when the probability of occurrence for the respective qualifying quiet period is greater than a predetermined value.

Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract: One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel based on the latency values. The second channel master is configured to obtain the latency values and maintain a second schedule of data traffic on the communications channel based on the latency values. The first channel master manages data on the communications channel via the first schedule and the second channel master manages data on the communications channel via the second schedule.

Abstract: Various methods and processing systems are disclosed which include sending and receiving components communicating over a bus having first and second channels. The sending component may broadcast on the first channel a plurality of read and write address locations, a plurality of transfer qualifiers, and write data. The receiving component may store the write data broadcast on the first channel at the receiving component based on the write address locations and a first portion of the transfer qualifiers. The receiving component may also retrieve read data from the receiving component based on the read address locations and a second portion of the transfer qualifiers, and broadcast the retrieved read data on the second channel.

Abstract: A method for connecting at least one sensor or actuator to a time-controlled bus system, the sensor or actuator carrying out a signal processing in at least two phases, the signal processing in a first phase taking place at a higher speed than in a second phase, the sensor or actuator being synchronized to a time, which is external to the sensor, of the time-controlled bus system in at least one of the phases.

Abstract: There is described an apparatus and method for implementing a communications port. The apparatus comprises a core, which is operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing. Each sub-port is allocated a corresponding data transfer capacity.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: A bi-directional single-conductor interface is provided, comprising (1) a switching means for applying a voltage level to the interface that is outside a normal voltage operating range for the interface and for removing the applied voltage level at an end of a specified time duration; and (2) a timer initiated by detection of the applied voltage and arranged to include a timing interval following removal of the applied voltage. With the interface of the invention, data is caused to be transmitted via the interface in a first direction during the timing interval of the timer, and in an opposite direction during other times.

Abstract: A debugging proxy can be used to manage communication between a client and a debugger or debugging component. A debugging protocol can be used by the debugging proxy to facilitate communication management. A debugging protocol can provide for asynchronous messaging, and can allow for the communication of large grain messages. A debugging protocol can also implement a priority scheme that can be used to process messages between a client and a debugger based upon a priority assigned to each message.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: An electronic apparatus includes a memory, first and second bus masters, a counting unit and a control unit. The first and second bus masters are capable of accessing the memory. The counting unit counts an amount of addresses reserved by the second bus master for accessing the memory. The control unit controls to avoid permitting a request made by the second bus master if a value counted by the counting unit becomes larger than a first threshold value, until the value counted by the counting unit becomes smaller than a second threshold value. The request made by the second bus master is used to reserve addresses of the memory, and the second threshold value is smaller than the first threshold value.

Abstract: An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an address corresponding to an access request to the second bus sent from a first bus, responsive to the access request, and a count value generator generating a count value up to the wait periodicity set to the number-of-waits setting circuit. A control signal holding circuit holds a control signal for holding a state of the second bus at the setting of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintains the access state of the status controller. A clock control circuit divides a clock for the first bus according to the wait periodicity set and outputs the result of division to the second bus.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.