Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Abstract: A data storage system can transfer user-generated data from a data storage device to a host responsive to a host workload that consists of data read requests from the host received at a requested rate. A completion rate of a data read request can be delayed in accordance to a data access uniformity strategy to nominally match the requested rate.

Abstract: An example computing system may include a plurality of processors, persistent memory that is shared by the plurality of processors, and a memory-side accelerator that is to control access to the memory. A requesting processor of the plurality of processors may simultaneously request locking of and access to a target data object of the persistent memory by sending a single lock-and-access message to the memory-side accelerator. The lock-and-access message may include a first memory capability pointing to the target data object, a second memory capability pointing to a lock object that controls locking of the target data object, and a specified access operation that is requested.

Abstract: Sequential write management in accordance with the present description permits impermissible write retries to be processed by a hard drive such as a Shingled Magnetic Recording (SMR) hard dive. In one embodiment, logic returns a successful write indication in response to a received retry write request operation without writing data to the SMR hard drive if the data of the received retry write operation has already been successfully written to the same location requested by the received retry write request operation. Conversely, a failure notice is returned if the data of the received retry write request operation has not been previously successfully written to the same location requested by the received retry write request operation. Other features and aspects may be realized, depending upon the particular application.

Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Abstract: A connector can be activated or deactivated by providing power and data signals to the connector at different times. In some embodiments, the power signals are provided to a connector, and then the data signals are provided to the connector after a delay. Providing power and data signals at different times can, in at least some cases, better mimic the timing of signals provided by a connector as the connector is attached to an electronic device. This can aid automated testing of the electronic device. It can also be used to control access of the device through the connector.

Abstract: A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. These various subsystems can include one or more sensing devices, processors, data storage devices, patient alert devices, power management devices, signal processing and other devices implemented to perform a variety of different functions.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: An apparatus and method for operating many applications between a portable storage device and a digital device are provided. The method includes opening at least two logical channels from the digital device to the portable storage device through a physical channel, transmitting and receiving data between a plurality of applications of the digital device and a plurality of applications of the portable storage device through the opened logical channels, and closing the logical channels after finishing the transmitting and receiving of the data.

Abstract: A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: An electronic apparatus includes a memory, first and second bus masters, a counting unit and a control unit. The first and second bus masters are capable of accessing the memory. The counting unit counts an amount of addresses reserved by the second bus master for accessing the memory. The control unit controls to avoid permitting a request made by the second bus master if a value counted by the counting unit becomes larger than a first threshold value, until the value counted by the counting unit becomes smaller than a second threshold value. The request made by the second bus master is used to reserve addresses of the memory, and the second threshold value is smaller than the first threshold value.

Abstract: A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost.

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

Abstract: A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to an IDLE state after the electronic device generates error information representing an error of the access wait signal or performs access to the I/O device according to a transition of the access wait signal to a state for determining a delay of access to the I/O device. Therefore, with the method, even when the access wait signal transmitted from the I/O device to the electronic device erroneously maintains a signal state for delaying access to the I/O device, the electronic device can be released automatically from an access delayed state after a predetermined time period.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.

Abstract: The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device includes an address storage area that is configured to store system addresses corresponding to data contemporaneously stored in the data storage area. The device further includes a first circuit configured to indicate validity status of data within the data storage area for immediate access from the I/O data bus. A similar, second circuit is also included and configured to indicate validity status of data within the data storage area for immediate access from the system data bus.

Abstract: A method of communicating between an initial device and a target device connected by a plurality of intermediate segments in a distributed arbitration system is provided. The method includes establishing an arbitration timer for a communication request by the initial device. Furthermore, use of each of the intermediate segments is arbitrated based on the arbitration timer.

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.

Abstract: A bus has a local section (10a,b) and a shared section (11a,b). An arbiter circuit (16) issues an arbited grant (25) to access the shared section (11a,b) in response to a request (22) to perform a bus access transaction. A bus station (12) has a request output (17a) for issuing the request to the arbiter (16), the bus station (12) having a grant input (19c) arranged to receive a local grant (24) in response to the request (22), independently of the arbited grant (25). The bus station (12) is arranged to start the transaction, applying an address to the local section (10a,b) in response to the local grant (24) in a bus cycle following the local grant (24). A bridge circuit (16) provides a coupling between the local section (10a,b) and shared section (11a,b). The bridge station receives the arbited grant (25) and enables the coupling to pass the address to the shared section (11a,b) in said bus cycle conditional on the arbited grant (25).

Abstract: An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the processor and the modules is connected to a fast AMBA-AHB bus, several advantages are achieved: for one, faster access is possible to each register. For another, the placement of the registers and the routing for the registers is simplified. This in particular allows chip area to be saved, which leads to cost savings in manufacture and enables higher component density. Furthermore, a slow AMBA-APB bus has now become optional.

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the interface's Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value.

Abstract: An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system balances interrupt assignments among both fixed devices mounted on the processor board and interrupt assignments to devices situated in expansion slots. When the system is populated with a large number of devices relative to the number of available interrupts, improved interrupt sharing is desirably achieved by causing a device which generates a large number of interrupt requests to share a common interrupt with a device which generates a lower number of interrupts.

Abstract: A conveying apparatus is provided with a control device for performing infinite rotation control of rotation of a strut or wrist shaft of a robot conveying an article and a drive shaft of a conveyor. The control device comprises a rotary shaft (6) rotationally driven, a drive (7) for rotating the rotary shaft, an encoder for detecting a rotation of the rotary shaft, a servo control device (22) for controlling the drive (7) based on a program command, a main control device (10) for controlling rotation, and an infinite rotation control device (12) for controlling infinite rotation. The program command is prepared and position control is carried out based on a reference encoder value. In the case of issuance of a command from a command circuit, by adding or subtracting an encoder value equivalent to a position-moving amount, the reference encoder value is changed and stored.

Abstract: A bus system and a command delivering method includes (a) delivering a first command to a first slave device, and (b) delivering a second command to a second slave device at a point in time which is less than or equal to a latency time of the second slave device in advance of the completion of data transfer according to the first command. Accordingly, preparation necessary for data transfer can begin sooner, thereby reducing idle clock cycles of a data bus.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: A computer readable media for use with a computer, the computer readable media bearing software configured to present to a user of the computer an interface with which the user can select from a superset of print features provided by multiple printers; receive from the user data indicating print features selected by the user; and suggest a printer to the user based on print features selected by the user. A method of configuring a computer for printing, the method comprising presenting to a user an interface with which the user can select from a superset of print features provided by multiple printers; receiving from the user data indicating print features selected by the user; and suggesting a printer to the user based on print features selected by the user.

Abstract: The present invention is built on a time out control apparatus to control the time out when a packet is transferred between terminal units connected to different buses. In the time out control apparatus, delay measuring means measures the delay time required for a response packet to be received after a request packet is sent to a terminal unit (control unit) connected via a bus. Delay information list generating means generates a delay information list in which the delay times measured by the delay measuring means are related to the individual identification information on the respective terminal units. Information output means reads out the delay time from the delay information list in accordance with a request from the terminal unit and outputs the delay time to the terminal unit. This sets the delay time on the time out register of the terminal unit.

Abstract: A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units are associated respectively with a set of request signals that allow these PCI-compliant units to request the use of the PCI bus system for data transfer. The access sequencing scheme includes a first-layer access sequence loop and a second-layer access sequence loop, with the first-layer access sequence loop having a higher priority over the second-layer access sequence loop The request signals are assigned to either the first-layer access sequence loop or the second-layer access sequence loop in a predetermined manner. The user can change the assignment of a certian request signal from one loop to the other through PC's BIOS (Basic Input/Output System), so as to allow the associated PCI-compliant unit to have a higher priority level to the use of the PCI bus system.

Abstract: A multiport device is configured to recognize each active segment on a bus, and to selectively propagate signals within the device depending upon whether the segment is active. Optimal signal propagation is achieved by invoking the control of the propagation of signals only after a first active-transition on the bus. Initial transitions are propagated unconditionally, to minimize propagation delay, and subsequent signal propagations are conditionally controlled, to avoid latch-up. A latch is associated with each port. The latch is set each time the port is actively driven by a device on that port. The latch is reset when all the devices are in the quiescent state, or when another port remains active after the currently active port becomes inactive. The state of each port's latch controls the propagation of internally generated signals to the port. If the latch is set, internally generated signals are not propagated to the port, thereby preventing latch-up.

Abstract: A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.

Abstract: With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor. In the bus controlling unit, parameters regarding output disable times of external devices such as a first device are utilized. When a device with a long output disable time is read in a bus cycle, an idle state is forcibly inserted before a following bus cycle activation to avoid a data conflict.

Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is detected where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A notebook computer for stably operating a floppy disk drive, includes: a floppy disk drive for writing or reading information to or from a floppy disk according to predetermined control signals; a motherboard having a controller generating control signals for controlling reading and writing data from and to the floppy disk drive, the controller being mounted on the motherboard, the floppy disk drive driving the floppy disk according to the control signals transmitted from the controller; and a connection unit for transmitting the control signals and power supply potentials from the controller to the floppy disk drive, the connection unit being physically and electrically disposed between the motherboard and the floppy disk drive. The connection unit includes a pull-up device disposed between terminals connected to the control signals and one of the power supply potentials.

Abstract: A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.

Abstract: A system for improving system cycle time while supporting 1½ cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a first chip and a memory circuit.

Abstract: The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, including a first bus on one side of a bridge and a second bus on another side of the bridge. A first initiator device and a second initiator device are coupled to the first bus. The first and second initiator devices are both adapted to request ownership of the first bus and receive a respective first and second grant signal responsive thereto. A target device is coupled to the second bus. The bridge is coupled to the first bus and the second bus. The bridge is adapted to implement data transactions between the target device and the first device or the second device.

Abstract: A method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus is described. In one embodiment, the method includes detecting a write cycle by an initiator for transmitting data to a device. The method further includes asserting a write request to the device, responsive to detecting the write cycle, asserting a ready request to the initiator without detecting an acknowledge from the device, and receiving the data from the initiator.

Abstract: A bus arbitration apparatus includes N number of hierarchical arbitrators, wherein each hierarchical arbitrator contained in the lowest hierarchy is connected to p number of the bus request units. Especially the hierarchical arbitrator of each hierarchy has: a selector for generating a selection signal based on bus requests from the hierarchical arbitrators of a lower hierarchy and priorities of the hierarchical arbitrators of the lower hierarchy, wherein the selection signal represents a selected hierarchical arbitrator of the lower hierarchy, and for generating the bus request from the selected hierarchical arbitrator as a bus request from said each hierarchy; and a multiplexer, in response to the selection signal, for providing bus cycle information from the selected hierarchical arbitrator as bus cycle information of said each hierarchy.

Abstract: An SCSI quick arbitration and select protocol reduces the timing overhead associated with multiple, sequential data transfer operations, thereby significantly increasing bus efficiencies and average throughput. The conventional arbitration and selection phases are collapsed into a quick arbitrated and select phase, whereby the current SCSI target hosts an arbitration proceeding without the bus transitioning to a bus free phase. The quick arbitrate and select phase is invoked by a current target device by broadcasting a QAS message code during the message-in phase of the current process. QAS capable devices snoop the bus, recognize the QAS message code and enter a quick arbitrate and select phase. A fairness algorithm grants control of the bus to a participating QAS target with the next lowest SCSI ID from that of the current QAS target.

Abstract: In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, during the transmission of a message packet from a first routing element to a second routing element in the MPP system, link lock-up can be prevented effectively by determining whether the message packet contains a certain predefined quantity of data. Control codes, used for establishing the end to the message packet, can then be inserted into the message packet if it is determined that the message packet does, in fact, contain the predefined quantity of data.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.