Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: An autonomous driving controller includes a plurality of parallel processors operating on common input data. Each of the plurality of parallel processors includes a general processor, a security processor subsystem (SCS), and a safety subsystem (SMS). The general processors, the SCSs, and the SMSs of the plurality of parallel processors are configured to first, boot the plurality of SCSs from ROM second, boot the plurality of SMSs of the plurality of parallel processors from RAM or ROM, and, third, boot the plurality of general processors of the plurality of parallel processors from RAM. Between booting of the SCSs and the SMSs, at least one of the plurality of SCSs may load SMS boot code into the RAM that is dedicated to the plurality of SMSs.

Abstract: In some examples, a controller for a storage system separate from a host system checks whether a storage cartridge in a storage system is associated with an indication set, in an electronic memory, during a configuration operation in the storage system to indicate write protection is enabled for the storage cartridge. In response to determining that the storage cartridge is associated with the indication, the controller triggers the write protection for the storage cartridge to prevent writing of data to the storage cartridge if the storage cartridge already contains previously written data.

Abstract: A computer-readable medium may store machine-readable instructions for execution by a processor. There may be a connection between the processor and a virtual computer. The processor may establish a first data channel between the processor and the virtual computer based on the connection between the processor and the virtual computer. The connection may comprise a second data channel to transfer input/output (I/O) data between the processor and the virtual computer. The processor may receive an input signal from an I/O device coupled to the processor. The processor may provide an input message to the virtual computer via the first data channel, the input message based on the input signal.

Abstract: Approaches in accordance with various embodiments can be used to provide bootstrap data for a computing device, such as a system on chip (SoC). In particular, various embodiments can use one or more shift registers to receive bits of a sequence of bootstrap data in parallel. Individual bits of this bootstrap data sequence can then be provided to the SoC, from the shift register(s), serially and using a single input. Such an approach prevents the need for multiple bootstrap pins on the SoC, as well as the need to multiplex those pins for use with other external devices.

Abstract: A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

Abstract: A first solid state drive (SSD) includes a built-in network interface device configured to communicate via a network fabric, and a second SSD includes a built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric, where the first SSD is further communicatively coupled to the second SSD further over an interconnect associated with a host computer. The first SSD encapsulates a non-volatile memory over fabric (NVMe-oF) command to transfer data between the first SSD and the second SSD in a capsule and sends the capsule to the second SSD over the connection. The second SSD executes the NVMe command to transfer the data between the first SSD and the second SSD over the connection according to an NVMe-oF communication protocol and without transferring any of the data to the host computer.

Abstract: A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintena

Abstract: The disclosure relates to a test system for improving test stability. One end of the connection pin is fixed to a bottom surface of a corresponding pin socket, the bottom surface is near an end of the plug end, the other end of each connection pin is disposed in the corresponding pin socket and a portion of the other end of the connection pin protrudes from a top surface of an end of the plug end. The connection pin in the plug end will not be deformed by external force, which can avoid the deformation of the connection pin caused by external force, and ensure the electrical connection and test stability.

Abstract: Embodiments are described for prioritizing input/output (I/O) operations dispatched from a storage media to a host bus adapter in a network, by tagging, in an I/O tagging module, the I/O operations in a file system supporting applications generating the I/O operations, wherein all child I/O operations initiated from a parent I/O operation are tagged with a same unique tag ID; tracking a time of arrival of each I/O operation of the I/O operations; and dispatching, in a transactional I/O scheduler, all sibling I/O's of the parent I/O operation based on a unique tag ID for the sibling I/Os, a respective time of arrival of each of the sibling I/Os, and defined quality of service (QoS) requirements.

Abstract: A novel storage router with an acceleration gate is disclosed. The storage router includes one or more network interfaces for receiving storage traffic and a hardware engine for processing data storage commands. The hardware engine transfers commands and data to target storage devices by means of more than one storage interface, the storage interfaces having unequal processing latencies. The hardware engine contains an acceleration gate for storing the number of outstanding commands to each storage interface on a per-target-device basis. If the target device is not idle, the hardware engine uses the acceleration gate count to automatically route commands to the lowest latency path with outstanding commands for the target device.

Abstract: In some examples, a network accessory includes a computing device interface to communicate with a computing device that is separate from the network accessory, a network interface to communicate over a network, and a processor to access a first network address of the computing device and to use the first network address of the computing device to communicate information of the computing device over the network with a network device.

Abstract: Systems and methods for automated management of buildings and rooms employ a common set of components that may be paired together to form a modular room control interface. The components may comprise a base plate and a front plate that are in data communication with each other when connected together. The base plate may include one set of room monitoring and control functions and the front plate may include a different set of room monitoring and control functions. Different combinations of base plates and front plates may then be paired together to achieve a desired functionality in the modular room control interface. Such an arrangement provides a room control interface that can be quickly and easily configured for any number of different room monitoring and control functions as needed.

Abstract: A slide rail mechanism includes a first slide rail assembly, a second slide rail assembly and a supporting assembly. Each of the slide rail assemblies includes a first rail, a second rail and a third rail movably mounted between the first rail and the second rail. The second rail is longitudinally movable relative to the first rail. The second rail of the first slide rail assembly and the second rail of the second slide rail assembly are respectively arranged with a first mounting device and a second mounting device. The supporting assembly includes a supporting member, and a first connecting device and a second connecting device arranged on the supporting member. The first connecting device and the second connecting device are respectively connected to the first mounting device and the second mounting device.

Abstract: Systems and methods for automated management of buildings and rooms employ a common set of components that may be paired together to form a modular room control interface. The components may comprise a base plate and a front plate that are in data communication with each other when connected together. The base plate may include one set of room monitoring and control functions and the front plate may include a different set of room monitoring and control functions. Different combinations of base plates and front plates may then be paired together to achieve a desired functionality in the modular room control interface. Such an arrangement provides a room control interface that can be quickly and easily configured for any number of different room monitoring and control functions as needed.

Abstract: There is an operation mode that is switchable between a first mode and a second mode. In the first mode, a screen is divided into two display areas, and a game image in which a first player character is included in one of the areas and a second player character is included in the other area is displayed. In the second mode, a game image in which the first player character and the second player character are included is displayed in a single screen. In addition, the first player character can be moved using the first controller, and the second player character can be moved using a second controller. The second player character can be freely moved in the first mode, and can be moved within a predetermined range based on the position of the first player character in the second mode.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.

Abstract: An apparatus including a handshake window enabler having a pair of differential inputs and a window enablement output, a common mode detector coupled to a power input and a ground input and having a handshake inhibit output, and a handshake disabler coupled to the handshake window enabler, the common mode detector, and the pair of differential inputs. If a common mode voltage that out of range (“too high”) is detected, high speed handshake protocols are such that the bus operates a lower data rate.

Abstract: Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.

Abstract: Examples of devices, methods, systems, and machine readable media for reducing the burden of a master device of a second wireless connection by utilizing the channel map of a first wireless connection are provided. Since both the first and second wireless connections are located at nearly the same location, the “good channels” are very similar for both connections. Therefore a second wireless connection may take advantage of the channel assessment conducted by a first wireless connection in identifying channels by using one or more channels of the first wireless connection for communications in the second wireless connection.

Abstract: The present invention is intended to permit both real-time display of a picture represented by a non-compressed video signal on a television and display of a picture represented by a compressed video signal at any desired time by simultaneously transmitting the compressed video signal and non-compressed video signal via one interface. An STB packetizes a compressed video signal, and multiplexes the compressed video signal and a blanking signal combined with a non-compressed video signal. Thus, both the video signals are transmitted simultaneously. A picture represented by the non-compressed video signal is displayed on a television in real time. The compressed video signal is stored in a storage medium incorporated in the television, read at any user's desired time, and decoded so that a picture represented by the compressed video signal can be viewed at the user's desired time.

Abstract: A computerized method that assists in preventing malware from evading detection through analysis of the virtual hardware components operating within a malware detection system is described. First, a virtual machine (VM) is provisioned in accordance with a guest image, which includes a guest operating system and one or more virtual hardware component. The virtual hardware component including an identifier, and the guest operating system includes a software driver that controls access to the virtual hardware component and features the identifier of the virtual hardware component. Responsive to processing an object within the VM and issuance of a request for an identifier of a hardware component, the identifier of the first virtualized hardware component (virtualization of the hardware component) is received. The first identifier of the first virtual hardware component being an identifier substituted for a prior identifier of the first virtual hardware component before creation of the guest image.

Abstract: An autonomous on-road vehicle having an outer nontransparent Shock-Absorbing Energy Dissipation Padding (SAEDP). In one embodiment, the SAEDP is mounted, during normal driving, to the front side of the vehicle at eye level of an occupant who sits in a front seat of the vehicle. A camera is mounted to the vehicle and takes video of the outside environment in front of the occupant. And a computer generates a representation of the outside environment at eye level for the occupant.

Abstract: A Shock-Absorbing Energy Dissipation Padding (SAEDP) is coupled to the compartment of an autonomous on-road vehicle, and is located, during normal driving, at eye level in front of an occupant who sits in a front seat of the vehicle. The vehicle further includes a stiff element that supports the SAEDP and resists deformation during collision in order to reduce compartment intrusion. The stiff element is located, during normal driving, at eye level between the SAEDP and the outside environment. Optionally, a camera takes video of the outside environment in front of the occupant, and a computer generates for the occupant a representation of the outside environment.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: A method of enhancing security of at least one of a host computing device and a peripheral device coupled to the host computing device through a communication interface. Data is transparently received from the peripheral device or the host computing device, and the received data is stored. The stored data is analyzed to detect a circumstance associated with a security risk. If such a circumstance is not detected, then the data is transparently forwarded to the other of the peripheral device or the host. However, if a circumstance associated with a security risk is detected, then a security process, defined by a rule, is performed. Related apparatus are provided, as well as other methods and apparatus.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: When data output is requested by an application whose default output setting is set ineffective among a plurality of applications, an output setting updating part (120) updates an output setting of the requesting application from ineffective to effective and updates an output setting of another application which outputs data to the same output destination as the output destination of the requesting application and whose default output setting is set effective, from effective to ineffective. An output control part (160) outputs data of an application whose output setting is effective.

Abstract: A computer-implemented method includes establishing, during boot time of a virtual machine, a virtual remote access service (VRAS) device between the virtual machine and a hypervisor booting the virtual machine. A request for scoped data relevant to the virtual machine is received at the hypervisor from the virtual machine, by way of the VRAS device. The scoped data relevant to the virtual machine is collected by the hypervisor. The scoped data relevant to the virtual machine is transmitted across the VRAS device from the hypervisor to the virtual machine.

Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. A local logic device manages each hard drive sub-board. A master logic device manages the local logic devices. The master logic device receives management commands from a host computer system coupled to the storage enclosure, and routes those commands to specific local logic devices. The local logic devices then relay the commands to specifically targeted hard drives. Thus, each hard drive within the storage enclosure can be independently controlled, allowing a single hard drive to be powered down without powering down other hard drives in the enclosure.

Abstract: Methods and apparatuses for data transformation are disclosed. An exemplary apparatus includes a first memory, a second memory, a cross-bar switch communicatively coupled between the first memory and the second memory, and a lookup table that specifies one or more memory addresses of the first memory to read out to the cross-bar switch, one or more memory addresses of the second memory to which to write data from the cross-bar switch, and a configuration of the cross-bar switch. An exemplary method includes determining, based on a lookup table, one or more memory addresses of a first memory to read out to a cross-bar switch, determining, based on the lookup table, one or more memory addresses of a second memory to which to write data from the cross-bar switch, and determining, based on the lookup table, a configuration of the cross-bar switch.

Abstract: A processing board mounted on a medical diagnostic apparatus, the medical diagnostic apparatus, and a method of controlling the medical diagnostic apparatus are provided. The processing board includes a sensor configured to sense at least one selected from the group consisting of an installation position, an installation direction, and a power consumption of the processing board. The processing board further includes a controller configured to set an identifier (ID) of the processing board based on an output signal of the sensor.

Abstract: According to one example, to access at least one computer device from a virtual machine, a control domain accesses a list of at least one device. For each device in the list of devices, a determination is made as to whether the device is to be exposed to a virtual machine, and a table of devices determined to be exposed to the virtual machine is created and provided to the virtual machine. Determining whether a device is to be exposed to a virtual machine is based on at least one device attribute.

Abstract: A configuration tool includes a tangible, non-transitory computer-readable medium having computer-executable instructions for configuring a model of a technical system and displaying the model on a display connected to a computer. The model includes at least two model components. Each model component has at least one port. Each model component is displayable in an expanded component representation on the display. The at least one port of each model component is connectable to at least one port of another model component by port association lines. Each model component is displayable in an expanded line representation on the display along with the at least one port and the port association lines of each model component. At least for one selected model component the port association lines connected to ports of the selected model component can be selected to be displayed in a reduced line representation.

Abstract: An object of the invention is to provide a field programmable gate array which is able to prevent an inappropriate value from being output to the outside of an FPGA even when an SRAM-based programmable logic portion is out of order and to secure safety of a system. The field programmable gate array of the invention includes a hard macro CPU in which a circuit structure is fixed, a programmable logic in which a circuit structure is changeable, a diagnosis circuit which diagnoses an abnormality of the programmable logic, and a fail-safe interface circuit which is able to control an external output from the programmable logic to a safe side, and the hard macro CPU outputs a fail-safe signal which is an output of a safe side to the fail-sate interface circuit when an error is detected by the diagnosis circuit.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of controlling data flow over a communication network. For example, an apparatus may include a communication unit to communicate between first and second devices a transfer response, the transfer response in response to a transfer request, the transfer response including a transfer pending status indicating data is pending to be received at the second device, the communication unit is to communicate the transfer response regardless of whether a retry indicator of the transfer request represents a first request for transfer or a retried request.

Abstract: A single universal sensor interface of a machine monitoring system is capable of providing a sensor supply voltage range that is selectable from 0V to ?30V, 0V to +30V, or +/?15V, and a sensor signal input range of ?30V to +30V to accommodate various types of sensors typically used in machine monitoring applications. Some embodiments of the interface also provide a buffered, unaltered sensor signal output.

Abstract: A converter for use in a distributed power system for stepping up or down a voltage of a power source connected thereto includes a step up/down circuit that receives the voltage, steps up or steps down the voltage from the power source, and then outputs the stepped up/down voltage; and a control circuit that detects the voltage from the power source and transmits a control signal for stepping up or stepping down the voltage to the step up/down circuit. The control circuit transmits an identification signal that identifies the converter and is configured to receive an identification signal from another converter when the other converter is connected to the converter.

Abstract: A control device for controlling a safety device which can be connected to a master assembly by means of an IO link is characterized in that a safety protocol can be transmitted via an IO link connection.

Abstract: A method is provided for cutting and pasting text at a computing device. A user selects an area of text on a display of the computing device. The computing device expands the selected area of text to form an expanded area of text to make sure that no text that the user wanted to select is inadvertently omitted. The computing device associates a data label with a portion of the expanded area of text, and the computing device stores the data label and the associated portion of the expanded area of text, preferably within the clipboard of the computing device. When a user enters input text on the computing device, the computing device parses the input text to determine if a data label stored in the clipboard matches the input text. If there is a match, the computing device displays stored text associated with that data label within a popup window, for example. If a user chooses one of the items in the popup window, the data label is replaced by the portion of text that was chosen and matches the data label.

Abstract: In one aspect, a video processing device includes a processor and a transmitter, for example implemented as separate integrated circuits on a printed circuit board. Pins on the processor are coupled to pins on the transmitter via a data channel, for example conductive leads on the printed circuit board. Video data is transmitted from the processor to the transmitter via this data channel, which is high speed enough to accommodate video data. The transmitter also includes an encryption engine used to encrypt the video data. Encryption control data, which determines the encryption to be applied, is transmitted from the processor to the transmitter over the same data channel as the video data. This is more secure than transmitting the encryption control data over a slower separate data channel, because the high speed video channel is harder to tamper with.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: According to an embodiment, a storage device may be provided. The storage device may include a semiconductor memory device, and a memory controller configured for controlling the semiconductor memory device. The semiconductor memory device may include a memory unit including a plurality of memory chips. The semiconductor memory device may include an interface chip realigning serial data received from the memory controller into parallel data and transferring the parallel data to each of the plurality of memory chips.

Abstract: A manufacturing equipment digital interface includes a shared Small Computer Standard Interface (SCSI) connector that is electrically connected to a manufacturing equipment SCSI bus. A plurality of SCSI-to-target-memory bridges is electrically connected to the shared SCSI connector. The plurality of SCSI-to-target-memory bridges interfaces the shared SCSI connector to a plurality of target memory devices. A drive controller includes a memory buffer that provides temporary storage of the information being transferred from the manufacturing equipment SCSI bus to the plurality of target memory devices. Also, the drive controller includes a SCSI-to-target-memory bridge arbitrator that controls the transfers of information from the manufacturing equipment SCSI bus to the target memory device. A network interface is electrically connected to the drive controller.

Abstract: A system for enforcing energy regulations is described. The system helps building departments maximize energy savings from the energy regulation enforcement process. The system is configured to optimize enforcement given a fixed level of enforcement resources within a building department. Optimization is achieved through the use of building science and sampling systems to structure building-by-building specialized inspection lists, which are delivered to building inspectors. Information collected during the inspection process is used to determine amounts of money that can be saved via complying or not complying with specific provisions of the energy regulations.

Abstract: A serial peripheral interface system with a slave expander method and apparatus can include: receiving a data stream from a master device, the data stream beginning with an address; decoding the address as the data stream is being received; activating an independent slave select after the address is decoded and before a second portion of the data stream is received; and deactivating the independent slave select based on a slave select from the master device being deactivated.

Abstract: Techniques to determine an adjustment to front end bandwidth of a server based on backend bandwidth and to adjust power consumption of an input/output (I/O) device.

Abstract: Systems and methods are disclosed herein to provide improved data communication test systems for the testing of wireless data communication devices and systems. A flexible arrangement of physical layer interfaces, hardware traffic generator/analyzers and software traffic generator/analyzers is disclosed that partitions the data communication test system into interfacing and processing modules. Such a system may offer improved capabilities such as a lower-cost and more efficient test system, a reduction in redundant processing capabilities, and a dynamic balancing of interfaces and processing power.

Abstract: An advanced PCI Express board assembly is intended for efficiently placing more electronic components or modules having a large height (up to 8.57 mm) in comparison with traditional PCI Express add-in boards. This assembly comprises two PCBs connected together. The first one has the minimum possible sizes. This PCB includes a PCI Express male edge connector and is intended to be plugged in to motherboard female PCI Express connector. The second PCB is parallel to first one and is located in the middle of the space (slot) defined for one add-in PCI Express board. This position makes possible to place high electronic components or modules on the both sides (top and bottom) of the second PCB.