Abstract: A memory expander includes memory sub-modules, power management integrated circuits, a controller, and a power controller. The memory sub-modules store data, and each of the memory sub-modules includes one or more memories. The power management integrated circuits independently supply powers to the memory sub-modules, respectively. The controller communicates with an external device through an interface (e.g., compute express link (CXL)), controls operations of the memory sub-modules, and checks whether the memory sub-modules are abnormal. The power controller controls operations of the power management integrated circuits. In response to a first memory sub-module becoming abnormal, the power controller controls a first power management integrated circuit to block a first power supplied to the first memory sub-module.

Abstract: A wireless input/output (IO) device synchronized wakeup and packet polling system of a wireless communication dongle at an information handling system may comprise a wireless radio system in a receive (RX) mode to monitor a designated radio frequency (RF) wake channel upon a timeout without wireless communications from a wireless IO device, the controller to receive a request to connect on the designated RF wake channel from the wireless IO device upon a wake event at the wireless IO device, the wireless radio system to respond by switching to a transmit (TX) mode and transmitting instructions for a data packet communication frame having a selected number and length of data packets to be sent at selected time slots, and the wireless radio system to receive the data packet communication frame.

Abstract: An electronic apparatus includes a display; an input interface including a first high-speed multimedia interface (HDMI) port configured to connect to a first source device, and a second HDMI port configured to connect to a second source device; and at least one processor operatively connected with the display and the input interface, wherein a first switching device is provided in a first consumer electronic control (CEC) line corresponding to the first HDMI port, and a second switching device is provided in a second CEC line corresponding to the second HDMI port, and wherein the at least one processor is configured to: control, based on a malfunction associated with a CEC function being identified from the first source device or the second source device, the display to display a user interface (UI) for turning off the CEC function, and turn off the CEC function by separately controlling at least one of the first switching device or the second switching device based on a user command received through the UI.

Abstract: Embodiments described herein provide a device for storing parity information. The device includes a wireless transceiver, a memory, and an electronic processor coupled to the wireless transceiver and the memory. The electronic processor is configured to receive, with the wireless transceiver, the parity information from a data storage device controller, and store the parity information in the memory.

Abstract: In a control and monitoring signal transmission system according to the present invention, a master station that transmits and receives data to and from a control unit, a plurality of remote stations that transmit and receive data to and from the master station by a transmission synchronization method via a common transmission line, and a terminator that is connected to the common transmission line are provided, and transmitting and receiving data between the master station and the remote stations is performed by superimposing data on a frame repeatedly transmitted from the master station. The terminator extracts all of the monitoring data transmitted from the remote stations, converts the monitoring data into check data by a predetermined rule, and superimposes the check data on a check data output range provided at the end of the frame.

Abstract: An apparatus includes two PHY circuits, each including a PHY transmitter circuit and connected to a universal serial bus (USB)-C connector. The apparatus includes a USB circuit to issue a receiver detect signal through one of the PHY transmitters circuit to the USB-C connector, issue another receiver detect signal through the other PHY transmitter circuit to the USB-C connector, determine which receiver detect signal resulted in a termination in a USB-C element, and consequently determine an orientation of a USB plug connected between the apparatus and the USB-C element.

Abstract: A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintena

Abstract: The present disclosure relates to a circuit board that includes a first edge connector configured to communicatively couple the circuit board to a first connector of a second circuit board. The first edge connector extends from a side of the circuit board a first length. The circuit board also includes a second edge connector configured to communicatively couple the circuit board to a second connector of the second circuit board. The second edge connector extends from the side of the circuit board a second length that is different than the first length.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: The invention relates to a computer system and method having at least one peripheral device, a control module for controlling the peripheral device, and a connection module, which is connected to the control module via a first data link. The connection module has I/O data ports for exchanging pieces of information with the peripheral device, and the peripheral device is connected to one or multiple of the I/O data ports via a second data link. The number of channels in the first data link is smaller than the number of I/O data ports of the connection module. The control module includes a first gateway, which receives pieces of setpoint state information relating to the I/O data ports of the connection module.

Abstract: A video enhanced time tracking system is provided. The system may include a video capturing device, software applications (such as an application running on the video capturing device), and a backend system. The application may include a time tracking application that tracks time simultaneously as the video capturing device captures video. The captured video and the tracked time information may be uploaded to the backend system where it may be stored and processed. The system may correlate the tracked time information with the captured video and provide it to a client for review. In some embodiments, the system also includes an image recognition system that recognizes the user to authenticate the user's identity, that recognizes the user's workspace to determine when the user is working, and that recognizes the work being performed to determine the client that the user may be working for.

Abstract: One aspect of the invention provides a computer processing architecture including: a plurality of processors, each processor configured to: receive a set of data from one or more input channels or from another processor; execute at least one of a plurality of individualized processes on the data; and output the processed data according to an independent clock domain of the processor; a plurality of switches, wherein each switch connects a processor to an input channel of the one or more input channels or to another processor; and a micro-controller configured to: receive the processed data; control the plurality of switches by activating or deactivating each switch; generate a pipeline of processors from activating and deactivating the plurality of switches; and select one or more individualized processes of the plurality of individualized processes that each processor within the pipeline executes.

Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.

Abstract: Methods and systems are disclosed to aggregate traffic from multiple server devices through a peripheral component interconnect (PCI) hosting device. In one embodiment, the PCI hosting device comprises a network interface to couple the PCI hosting device to a network, a plurality of PCI interfaces, a processing circuit to forward packets, and a power supply to supply power to the PCI interfaces independently from the plurality of server devices. Each of the PCI interfaces is designed to be coupled to one server device to the PCI hosting device, which is registered as a first PCI board of a first server device through a first PCI interface and as a second PCI board of a second server device through a second PCI interface, and the PCI hosting device is designed to forward packets between the network interface and the first server device, and the network interface and the second server device.

Abstract: A configuration dataset indicative of a setting of one or more operational policies of a control of an industrial field device and a measurement dataset indicative of an event associated with the industrial field device is read from a distributed database. An analysis of the measurement dataset is performed, depending on the configuration dataset.

Abstract: An integrated circuit (IC) for adaptive memory expansion scheme is proposed, which comprises: a home agent comprising a first memory expansion pool and a second memory expansion pool; a first port connecting the home agent to a first memory expansion device, where the first memory expansion device comprises a first memory pool; a second port connecting the home agent to a second memory expansion device, where the second memory expansion device comprises a second memory pool; a first address table mapping the first memory expansion pool to the first memory pool based on a size of the first memory expansion pool or a size of the first memory pool; and a second address table mapping the second memory expansion pool to the second memory pool based on a size of the second memory expansion pool or a size of the second memory pool.

Abstract: A method and system for hardware-based predictive fault detection and analysis are described herein. Logic components of a computing cluster can baseline a plurality of telemetries associated with at least one processing node of the computing cluster. The logic components can monitor the plurality of telemetries while the at least one processing node is in operation. The logic components of the computing cluster can compare the monitored plurality of telemetries with the baselined plurality of telemetries. The logic components can predict one or more impending faults associated with the at least one processing node based on the comparisons.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: In some examples, a controller for a storage system separate from a host system checks whether a storage cartridge in a storage system is associated with an indication set, in an electronic memory, during a configuration operation in the storage system to indicate write protection is enabled for the storage cartridge. In response to determining that the storage cartridge is associated with the indication, the controller triggers the write protection for the storage cartridge to prevent writing of data to the storage cartridge if the storage cartridge already contains previously written data.

Abstract: An autonomous driving controller includes a plurality of parallel processors operating on common input data. Each of the plurality of parallel processors includes a general processor, a security processor subsystem (SCS), and a safety subsystem (SMS). The general processors, the SCSs, and the SMSs of the plurality of parallel processors are configured to first, boot the plurality of SCSs from ROM second, boot the plurality of SMSs of the plurality of parallel processors from RAM or ROM, and, third, boot the plurality of general processors of the plurality of parallel processors from RAM. Between booting of the SCSs and the SMSs, at least one of the plurality of SCSs may load SMS boot code into the RAM that is dedicated to the plurality of SMSs.

Abstract: A computer-readable medium may store machine-readable instructions for execution by a processor. There may be a connection between the processor and a virtual computer. The processor may establish a first data channel between the processor and the virtual computer based on the connection between the processor and the virtual computer. The connection may comprise a second data channel to transfer input/output (I/O) data between the processor and the virtual computer. The processor may receive an input signal from an I/O device coupled to the processor. The processor may provide an input message to the virtual computer via the first data channel, the input message based on the input signal.

Abstract: Approaches in accordance with various embodiments can be used to provide bootstrap data for a computing device, such as a system on chip (SoC). In particular, various embodiments can use one or more shift registers to receive bits of a sequence of bootstrap data in parallel. Individual bits of this bootstrap data sequence can then be provided to the SoC, from the shift register(s), serially and using a single input. Such an approach prevents the need for multiple bootstrap pins on the SoC, as well as the need to multiplex those pins for use with other external devices.

Abstract: A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

Abstract: A first solid state drive (SSD) includes a built-in network interface device configured to communicate via a network fabric, and a second SSD includes a built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric, where the first SSD is further communicatively coupled to the second SSD further over an interconnect associated with a host computer. The first SSD encapsulates a non-volatile memory over fabric (NVMe-oF) command to transfer data between the first SSD and the second SSD in a capsule and sends the capsule to the second SSD over the connection. The second SSD executes the NVMe command to transfer the data between the first SSD and the second SSD over the connection according to an NVMe-oF communication protocol and without transferring any of the data to the host computer.

Abstract: A data processing method for safe Instrumentation and Control Systems (I&C Systems) based on data processing in safety I&C Systems consisting of self-diagnosable modules of the platform with the unified architecture, to use specifically developed computing facilities implemented in FPGA, to design and configure the modules with the unified architecture of the unified units, to use units operation in different clock domains and diversity technologies, to design and configure the computing facilities, to provide mutual diagnostics and self-diagnostics for hardware, computing facilities, interfaces and data transfer at both modular and system levels implemented by hardware design tools and module platform logic, to use different software for application diverse logic design, to provide I&C System functional safety, to simplify design of modules and I&C Systems, to provide unified process and diagnostics and self-diagnostics coverage, to simplify user operation, to simplify I&C System maintena

Abstract: The disclosure relates to a test system for improving test stability. One end of the connection pin is fixed to a bottom surface of a corresponding pin socket, the bottom surface is near an end of the plug end, the other end of each connection pin is disposed in the corresponding pin socket and a portion of the other end of the connection pin protrudes from a top surface of an end of the plug end. The connection pin in the plug end will not be deformed by external force, which can avoid the deformation of the connection pin caused by external force, and ensure the electrical connection and test stability.

Abstract: Embodiments are described for prioritizing input/output (I/O) operations dispatched from a storage media to a host bus adapter in a network, by tagging, in an I/O tagging module, the I/O operations in a file system supporting applications generating the I/O operations, wherein all child I/O operations initiated from a parent I/O operation are tagged with a same unique tag ID; tracking a time of arrival of each I/O operation of the I/O operations; and dispatching, in a transactional I/O scheduler, all sibling I/O's of the parent I/O operation based on a unique tag ID for the sibling I/Os, a respective time of arrival of each of the sibling I/Os, and defined quality of service (QoS) requirements.

Abstract: A novel storage router with an acceleration gate is disclosed. The storage router includes one or more network interfaces for receiving storage traffic and a hardware engine for processing data storage commands. The hardware engine transfers commands and data to target storage devices by means of more than one storage interface, the storage interfaces having unequal processing latencies. The hardware engine contains an acceleration gate for storing the number of outstanding commands to each storage interface on a per-target-device basis. If the target device is not idle, the hardware engine uses the acceleration gate count to automatically route commands to the lowest latency path with outstanding commands for the target device.

Abstract: In some examples, a network accessory includes a computing device interface to communicate with a computing device that is separate from the network accessory, a network interface to communicate over a network, and a processor to access a first network address of the computing device and to use the first network address of the computing device to communicate information of the computing device over the network with a network device.

Abstract: Systems and methods for automated management of buildings and rooms employ a common set of components that may be paired together to form a modular room control interface. The components may comprise a base plate and a front plate that are in data communication with each other when connected together. The base plate may include one set of room monitoring and control functions and the front plate may include a different set of room monitoring and control functions. Different combinations of base plates and front plates may then be paired together to achieve a desired functionality in the modular room control interface. Such an arrangement provides a room control interface that can be quickly and easily configured for any number of different room monitoring and control functions as needed.

Abstract: A slide rail mechanism includes a first slide rail assembly, a second slide rail assembly and a supporting assembly. Each of the slide rail assemblies includes a first rail, a second rail and a third rail movably mounted between the first rail and the second rail. The second rail is longitudinally movable relative to the first rail. The second rail of the first slide rail assembly and the second rail of the second slide rail assembly are respectively arranged with a first mounting device and a second mounting device. The supporting assembly includes a supporting member, and a first connecting device and a second connecting device arranged on the supporting member. The first connecting device and the second connecting device are respectively connected to the first mounting device and the second mounting device.

Abstract: Systems and methods for automated management of buildings and rooms employ a common set of components that may be paired together to form a modular room control interface. The components may comprise a base plate and a front plate that are in data communication with each other when connected together. The base plate may include one set of room monitoring and control functions and the front plate may include a different set of room monitoring and control functions. Different combinations of base plates and front plates may then be paired together to achieve a desired functionality in the modular room control interface. Such an arrangement provides a room control interface that can be quickly and easily configured for any number of different room monitoring and control functions as needed.

Abstract: There is an operation mode that is switchable between a first mode and a second mode. In the first mode, a screen is divided into two display areas, and a game image in which a first player character is included in one of the areas and a second player character is included in the other area is displayed. In the second mode, a game image in which the first player character and the second player character are included is displayed in a single screen. In addition, the first player character can be moved using the first controller, and the second player character can be moved using a second controller. The second player character can be freely moved in the first mode, and can be moved within a predetermined range based on the position of the first player character in the second mode.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.

Abstract: An apparatus including a handshake window enabler having a pair of differential inputs and a window enablement output, a common mode detector coupled to a power input and a ground input and having a handshake inhibit output, and a handshake disabler coupled to the handshake window enabler, the common mode detector, and the pair of differential inputs. If a common mode voltage that out of range (“too high”) is detected, high speed handshake protocols are such that the bus operates a lower data rate.

Abstract: Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.

Abstract: Examples of devices, methods, systems, and machine readable media for reducing the burden of a master device of a second wireless connection by utilizing the channel map of a first wireless connection are provided. Since both the first and second wireless connections are located at nearly the same location, the “good channels” are very similar for both connections. Therefore a second wireless connection may take advantage of the channel assessment conducted by a first wireless connection in identifying channels by using one or more channels of the first wireless connection for communications in the second wireless connection.

Abstract: The present invention is intended to permit both real-time display of a picture represented by a non-compressed video signal on a television and display of a picture represented by a compressed video signal at any desired time by simultaneously transmitting the compressed video signal and non-compressed video signal via one interface. An STB packetizes a compressed video signal, and multiplexes the compressed video signal and a blanking signal combined with a non-compressed video signal. Thus, both the video signals are transmitted simultaneously. A picture represented by the non-compressed video signal is displayed on a television in real time. The compressed video signal is stored in a storage medium incorporated in the television, read at any user's desired time, and decoded so that a picture represented by the compressed video signal can be viewed at the user's desired time.

Abstract: A computerized method that assists in preventing malware from evading detection through analysis of the virtual hardware components operating within a malware detection system is described. First, a virtual machine (VM) is provisioned in accordance with a guest image, which includes a guest operating system and one or more virtual hardware component. The virtual hardware component including an identifier, and the guest operating system includes a software driver that controls access to the virtual hardware component and features the identifier of the virtual hardware component. Responsive to processing an object within the VM and issuance of a request for an identifier of a hardware component, the identifier of the first virtualized hardware component (virtualization of the hardware component) is received. The first identifier of the first virtual hardware component being an identifier substituted for a prior identifier of the first virtual hardware component before creation of the guest image.

Abstract: Embodiments can provide concurrent (or substantially concurrent) wireless communication that can achieve load and/or battery consumption balance between or among a set of wireless devices. In wireless transmission, each receiving device is typically identified by an address or an ID, which can be used for device identification and wireless configuration over wireless link. Under the concurrent wireless transmission in accordance with the embodiments, a secondary device can “impersonate” the primary device by assuming an ID or address assigned to primary device. In this way, load and/or battery consumption balance can be achieved among multiple wireless devices in the concurrent wireless transmission.

Abstract: A Shock-Absorbing Energy Dissipation Padding (SAEDP) is coupled to the compartment of an autonomous on-road vehicle, and is located, during normal driving, at eye level in front of an occupant who sits in a front seat of the vehicle. The vehicle further includes a stiff element that supports the SAEDP and resists deformation during collision in order to reduce compartment intrusion. The stiff element is located, during normal driving, at eye level between the SAEDP and the outside environment. Optionally, a camera takes video of the outside environment in front of the occupant, and a computer generates for the occupant a representation of the outside environment.

Abstract: An autonomous on-road vehicle having an outer nontransparent Shock-Absorbing Energy Dissipation Padding (SAEDP). In one embodiment, the SAEDP is mounted, during normal driving, to the front side of the vehicle at eye level of an occupant who sits in a front seat of the vehicle. A camera is mounted to the vehicle and takes video of the outside environment in front of the occupant. And a computer generates a representation of the outside environment at eye level for the occupant.

Abstract: A method of enhancing security of at least one of a host computing device and a peripheral device coupled to the host computing device through a communication interface. Data is transparently received from the peripheral device or the host computing device, and the received data is stored. The stored data is analyzed to detect a circumstance associated with a security risk. If such a circumstance is not detected, then the data is transparently forwarded to the other of the peripheral device or the host. However, if a circumstance associated with a security risk is detected, then a security process, defined by a rule, is performed. Related apparatus are provided, as well as other methods and apparatus.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: When data output is requested by an application whose default output setting is set ineffective among a plurality of applications, an output setting updating part (120) updates an output setting of the requesting application from ineffective to effective and updates an output setting of another application which outputs data to the same output destination as the output destination of the requesting application and whose default output setting is set effective, from effective to ineffective. An output control part (160) outputs data of an application whose output setting is effective.

Abstract: A computer-implemented method includes establishing, during boot time of a virtual machine, a virtual remote access service (VRAS) device between the virtual machine and a hypervisor booting the virtual machine. A request for scoped data relevant to the virtual machine is received at the hypervisor from the virtual machine, by way of the VRAS device. The scoped data relevant to the virtual machine is collected by the hypervisor. The scoped data relevant to the virtual machine is transmitted across the VRAS device from the hypervisor to the virtual machine.

Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. A local logic device manages each hard drive sub-board. A master logic device manages the local logic devices. The master logic device receives management commands from a host computer system coupled to the storage enclosure, and routes those commands to specific local logic devices. The local logic devices then relay the commands to specifically targeted hard drives. Thus, each hard drive within the storage enclosure can be independently controlled, allowing a single hard drive to be powered down without powering down other hard drives in the enclosure.

Abstract: Methods and apparatuses for data transformation are disclosed. An exemplary apparatus includes a first memory, a second memory, a cross-bar switch communicatively coupled between the first memory and the second memory, and a lookup table that specifies one or more memory addresses of the first memory to read out to the cross-bar switch, one or more memory addresses of the second memory to which to write data from the cross-bar switch, and a configuration of the cross-bar switch. An exemplary method includes determining, based on a lookup table, one or more memory addresses of a first memory to read out to a cross-bar switch, determining, based on the lookup table, one or more memory addresses of a second memory to which to write data from the cross-bar switch, and determining, based on the lookup table, a configuration of the cross-bar switch.