Abstract: A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

Abstract: A shared device unit, which comprises a storage device, is coupled to a plurality of storage systems. The shared device unit provides a plurality of storage areas, which are based on the storage device, to the plurality of storage systems. Each storage system stores allocation management information which comprises an ID of a storage area provided to thereof among the plurality of storage areas, and provides the storage area corresponded to the ID included in the allocation management information to the host computer coupled thereto among the plurality of host computers.

Abstract: A device comprises circuitry and a transceiver. In operation, the device is configured to cause the transceiver to: receive a first message from another device to support at least one aspect of attachment of the device and the another device, send, to the another device, a second message after the first message and prior to attachment, receive, from the another device, a third message that is sent after the second message and prior to attachment, send, to the another device, a fourth message after the third message and prior to attachment, receive, from the another device, a fifth message that is sent after the fourth message and prior to attachment, and send, directly to the another device, data utilizing at least one channel for data transfer utilizing a second one of the addresses for identification in association with the device on the shared wireless communication medium.

Abstract: There is provided a portable data storage device with wireless functionality. The portable storage device includes a digital switch circuit for controlling a flow of data in the portable storage device; a non-volatile memory module coupled to the digital switch circuit, the non-volatile memory module being for storing data; an interface coupled to the digital switch circuit for enabling the portable data storage device to be used for data transfer with a host device; a microcontroller coupled to the digital switch circuit for controlling the digital switch circuit; and a wireless communications module coupled to the microcontroller for wireless transmission/reception of data. The microcontroller is configured to toggle amongst a plurality of discrete modes of the digital switch circuit such that in at least one of the plurality of discrete modes the digital switch circuit diverts data away from the microcontroller to reduce a processing load on the microcontroller. A corresponding method is also disclosed.

Abstract: An I/O device sharing system characterized by comprising: an I/O device (50) shared by a plurality of hosts (20-1 to 20-N); a system manager (10) which sets the I/O device (50); a virtual bridge (40) which virtualizes the I/O device (50); and a network (3) which connects the I/O device (50), the system manager (10), the plurality of hosts (20-1 to 20-N) and the virtual bridge (40) to each other, wherein the virtual bridge (40) includes a connection virtualization unit (41) by which it is detected that an address setting of a plurality of virtual functions provided in the I/O device (50) that is set by the system manager (10) is performed, the virtual function is enabled, or both of them are performed and each host is permitted to access each virtual function.

Abstract: Described herein is a system (102) having a virtualization and switching system configured to virtualize I/O devices (108) and perform switching of the I/O devices (108) and I/O requests. The virtualization and switching system (102) includes a peripheral virtualization controller (PVC) (204), at least one device control module (206) connected to the PVC (204), and at least one command parser (210). The PVC (204) is configured to manage I/O virtualization and I/O command access of different I/O devices (108). The device control module (206) is configured to store configuration and I/O device registers, implemented by the PVC (204) to enable virtualization of I/O devices (108). The device control module (206) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (104).

Abstract: A system for achieving a uniform device abstraction layer is described. The system includes a device class determiner coupled with a local server, the device class determiner configured for establishing a device class for at least one device residing in a domain at a premises, wherein the domain is coupled with a remote server, and a device of the at least one device includes a communication port that supports a first protocol corresponding to a second protocol, wherein the second protocol is supported by a device driver coupled with the domain, wherein based on the establishing the device class, an action is enabled to be mapped to the device, thereby enabling an application to run on and utilize a capability of the device.

Abstract: A CEC block termination function, operated by a manipulating switch including at least one HDMI-CEC input port and at least two HDMI-CEC output ports, enables the manipulating switch to receive a CEC block which was initiated by a device, optionally acknowledge (ACK) the block, modify the received block, and supply the modified block to one or more devices. Optionally, a section of the CEC block may be modified, the entire CEC block may be modified, or the CEC message may be partially or completely modified.

Abstract: A method and apparatus in a vehicular telemetry system for an intelligent I/O expander. The intelligent I/O expander may be configured in an active mode or a passive mode. A vehicular telemetry hardware system may be configured in a passive serial control mode or an active serial control mode. The intelligent I/O expander capable of adding additional device to the vehicular telemetry system.

Abstract: A method and apparatus in a vehicular telemetry system for an intelligent I/O expander. The intelligent I/O expander may be configured in an active mode or a passive mode. A vehicular telemetry hardware system may be configured in a passive serial control mode or an active serial control mode. The intelligent I/O expander capable of adding additional device to the vehicular telemetry system.

Abstract: A data transfer method of a storage device which includes a host bus adaptor to communicate with an external host via a first interface and to communicate internally via a second interface is provided. The data transfer method may include issuing a write command and a read command to the host bus adaptor; performing a read direct memory access operation using the first interface in response to the write command and simultaneously performing a write direct memory access operation using the second interface in response to the read command; and generating frame information structure (FIS) sequences according to the second interface in response to the issued write command and the issued read command. The first interface may perform a full duplex data transfer and the second interface may perform a half-duplex data transfer.

Abstract: A hybrid drive includes multiple parts: a performance part (e.g., a flash memory device) and a base part (e.g., a magnetic or other rotational disk drive). A drive access system, which is typically part of an operating system of a computing device, issues input/output (I/O) commands to the hybrid drive to store data to and retrieve data from the hybrid drive. The drive access system assigns, based on various available information, a priority level to groups of data identified by logical block addresses (LBAs). With each I/O command, the drive access system includes an indication of the priority level of the LBA(s) associated with the I/O command. The hybrid drive determines, based on the priority level indications received from the drive access system, which LBAs are stored on which part or parts of the hybrid drive.

Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.

Abstract: A method for communicating data between peripheral devices and an embedded processor that includes receiving, at a data buffer unit of the embedded processor, the data from a peripheral device. The method also includes copying data from the data buffer unit into the bridge buffer of the embedded processor as a bridge buffer message. Additionally, the method includes creating, after storing the data as a bridge buffer message, a peripheral device message comprising the bridge buffer message, and sending the peripheral device message to a thread message queue of a subscriber.

Abstract: A data storage device and a FLASH memory control method with a cache space. The FLASH memory control method includes the following steps: using a plurality of channels to access a FLASH memory, wherein the FLASH memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels; allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively; distributing the data issued from a host to correspond to the different channels; and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to.

Abstract: The defined architecture allows for format-efficient data storage on bit-patterned media, while allowing for typical variations in the drive, such as reader to writer gap variations. The defined BPM architecture relaxes some timing requirements on real-time signaling from the formatter to the channel, while enabling bit-accurate alignment between data accesses and the media.

Abstract: A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor.

Abstract: A method, executed by a computer, for controlling storages includes obtaining time elapsed since data to be moved in a source storage in three or more storages whose performance for response to an access request is different is accessed in accordance with the access request, identifying, from the storages, a destination storage that meets condition under which the data to be moved in the source storage is moved, based on the obtained elapsed time by referring to a storage unit that stores the condition under which data is moved to each of the storages, and moving the data to be moved in the source storage to the identified destination storage.

Abstract: A storage device and memory accessing method configure two separate memory units, each with dedicated I/O channel, accessible by two controllers, each corresponding to an interface connected to a host, and allows the storage device to establish at least two connections to the different hosts. As more than one connection is established between the storage device and the hosts at the same time, a first controller has both read and write accessibility to a first memory unit and a second controller has both read and write accessibility to a second memory unit, while the first controller has read-only accessibility to the second memory unit and the second controller has read-only accessibility to the second memory unit.

Abstract: The present invention provides a wireless expansion card including: a contact power receiving module, configured to: in a first time period, receive contact power supply of a first contact user equipment to obtain first electric power; a contact communications module, electrically connected to the contact power receiving module, and configured to: in the first time period, perform first contact communication with the first contact user equipment to transmit a first read/write instruction and first data that needs to be read or written according to the first read/write instruction; and a wireless communications module, electrically connected to the contact power receiving module, in communication connection with the contact communications module, and configured to: in the first time period, use the first electric power, to perform first wireless communication with a first wireless peripheral device by using ultra-wideband impulse radio to transmit the first read/write instruction and the first data.

Abstract: Provided is a method for controlling and driving constituent elements of an external device connected to user equipment. The method may include obtaining external device information from the external device when coupled to the user equipment, obtaining application information based on the obtained external device information, and running an application tailored for the external device based on the obtained application information.

Abstract: Described is a technology by which the operation of an auxiliary computing device, comprising a display and/or actuator set, may be automatically modified based on detected state data. For example, user input may be routed from the actuator set to the host computer system when the host computer system is in an online state, or to the auxiliary computing device when the host computer system is offline. State may be determined based on one or more various criteria, such as online or offline, laptop lid position, display orientation, current communication and/or other criteria. The auxiliary display and/or actuator set may be embedded in the host computer system, or each may be separable from it or standalone, such as a remote control or cellular phone.

Abstract: Method for detecting presses on buttons of an electronic device with a reduced number of General Purpose In/Out (GPI/O) ports includes a number of the GPI/O ports The number of the buttons is greater than the number of the GPI/O ports. A proportion of the buttons are each coupled between one of the I/O ports and ground, and the remaining proportion of the buttons are each coupled between any two of the I/O ports. The GPI/O ports are set to work in a first working state or in a second state to provide a first signal or second signal respectively. When a signal provided by a GPI/O port working at the first working mode changes, the method determines which one of the buttons has been pressed.

Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

Abstract: A communications cable including a first communications interface configured to be connected to a storage device, a second communications interface configured to receive data and power, a wireless access module configured to be powered by the power received by the second communications interface and to enable wireless access of the storage device, and a cable unit including one or more cables and configured to connect the wireless access module to the first communications interface and the second communications interface, and the first communications interface to the second communications interface.

Abstract: A device comprises circuitry configured for being communicatively coupled to a transceiver. In operation, the device is configured to receive a first message from another device to support at least one aspect of attachment of the device and the another device and to send, to the another device, a second message after the first message and prior to attachment. In operation, the device is further configured to receive, from the another device, a third message that is sent after the second message and prior to attachment and send, directly to the another device, data utilizing at least one channel for data transfer utilizing a second one of the addresses for identification in association with the device on the shared wireless communication medium, for data transfer after attachment in connection with a group that is controlled by the another device.

Abstract: A method for replicating data between two or more network connected data storage devices, the method including dynamically determining whether to compress data prior to transmitting across the network based, at least in part, on bandwidth throughput between the network connected data storage devices. If it has been determined to compress the data, the method involves compressing the data and transmitting the compressed data over the network. If it has been determined not to compress the data, the method involves transmitting the data, uncompressed, over the network. Dynamically determining whether to compress data may include comparing bandwidth measurements with a predetermined policy defining when compression should be utilized. In some embodiments, the policy may define that compression should be utilized when an estimated time for compressing the data and transmitting the compressed data is less than an estimated time for transmitting the data uncompressed.

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

Abstract: A data storage architecture extension (DAX) system and method that daisy-chains multiple SATA disk drive storage elements to allow a single host bus adapter (HBA) to view the daisy-chain as one logical SATA disk drive is disclosed. The system/method may be broadly described as comprising a pass-thru disk drive controller (PTDDC) further comprising a pass-thru input (PTI) port, disk drive interface (DDI) port, and pass-thru output (PTO) port. The PTDDC intercepts and translates PTI port input to the requirements of a SATA disk drive connected to the DDI. Each PTDDC may be daisy-chained to other PTDDCs to permit a plethora of SATA drives to be associated with a given HBA, with the first PTDDC providing a presentation interface to the HBA integrating all SATA disk drive storage connected to the PTDDCs. Rack mounting of PTDDC-enabled SATA disk drives enables creation of inexpensive dynamically expandable petabyte-class storage arrays.

Abstract: A semiconductor device includes a controller chip, a plurality of semiconductor chips operatively connected to the controller chip, wherein at least one of the plurality of semiconductor chips is operatively supplied with a pulse signal from the controller chip, and operatively supplied identification information, wherein each of the plurality of semiconductor chips is configured to store the identification information in response to the pulse signal received from the controller chip, and wherein each of the plurality of semiconductor chips is configured to block transmission of the pulse signal to a following semiconductor chip in a signal path among the plurality of semiconductor chips until identification information is stored therein.

Abstract: A first storage system is configured as a proxy for a logical volume stored on a second storage system. The first computer system receives an I/O request from a host computer for the logical volume, the host computer, and identifies a port on the second storage system for the I/O request. In some embodiments, the second storage system has multiple SCSI ports, and the identified port comprises a least busy SCSI port. A probe request verifying availability of the logical volume is conveyed to the identified port, and upon receiving a response from the second storage system verifying the availability of the logical volume for the I/O request, the I/O request is conveyed to the identified port, a result of the I/O request is received from the identified port, the result is conveyed to the host computer.

Abstract: A control method for a USB 3.0 (USB: Universal Serial Bus) device includes controlling the USB 3.0 device that has entered an SS.Disabled state to transition to an Rx.Detect state when a USB 2.0 connection is not established with a USB host even after a predetermined time, the USB 2.0 connection including any one of an HS (High Speed) connection, an FS (Full Speed) connection, and an LS (Low Speed) connection.

Abstract: A device for transmitting multiple control formats from an audio/video source to an audio/video monitor receiver. The device includes a high definition multimedia interface cable that has a plurality of communication channels, including a consumer electronic control channel. Furthermore, a pair of plugs are coupled to the respective ends of the high definition multimedia interface cable and can be coupled to audio/video sources and receivers. A pair of interface ports are further coupled to the high definition multimedia interface cable and communicatively coupled to the consumer electronic control channel. The device transmits a first control format on the consumer electronic control channel when the input port is not coupled to a switching device and transmits a second control format on the consumer electronic control channel when the input port is coupled to a switching device.

Abstract: Described is a data switching device comprising a plurality of input ports, a plurality of output ports, a plurality of first conductive connectors, a plurality of second conductive connectors, a plurality of crosspoint regions, and a memory device at each crosspoint region. The first conductive connectors are in communication with the input ports. The second conductive connectors are in communication with the output ports. Each crosspoint region includes a first conductive connector and a second conductive connector. The memory device is coupled between the first conductive connector and the second conductive connector for exchanging data between the input ports and the output ports.

Abstract: A system is provided that includes a controller that is configured to enable communication between one or more sensors and a processor. The controller includes a plurality of input-output (IO) ports each configured to couple to the one or more sensors. Moreover, each of the IO ports is configured to couple to a plurality of sensor types such that each IO port is configured to couple more than one sensor type. The controller also includes an interface configured to receive a selection of a selected mode from a plurality of modes each corresponding to a sensor type. Furthermore, the controller includes a switch block having a plurality of switches each configured to toggle a connection in the switch block according to the selected mode.

Abstract: A method and apparatus in a vehicular telemetry system for an intelligent I/O expander. The intelligent I/O expander may be configured in an active mode or a passive mode. A vehicular telemetry hardware system may be configured in a passive serial control mode or an active serial control mode. The intelligent I/O expander capable of adding additional device to the vehicular telemetry system.

Abstract: A computer program product is provided for performing an input/output (I/O) operation initiated by an I/O operation instruction at a host computer system configured for communication with a control unit. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing: receiving, by the control unit, a transport mode command message from a channel subsystem of the host computer system, the command message include a command for data to be transferred between the host computer system and an I/O device controlled by the control unit; and sending a command retry message to the channel subsystem, the command retry message including a request that the command message be re-sent to the control unit and a reason code indicating a reason for the request.

Abstract: A detection circuit can be configured to receive a digital value from an identification register and to determine a resistance at a conducting terminal of an audio or video jack plug using the digital value. The detection circuit can include a current source that outputs a current according to the digital value from the identification register and a comparator that compares a reference voltage to a voltage created by the current source across the resistance at the conducting terminal of the audio or video jack plug. A control logic circuit can be configured to store the digital value in the identification register, generate an interrupt signal to cause a processor to read the digital value, and identify a function of an accessory device including the audio or video jack plug, when the detection circuit determines the resistance at the conducting terminal of the audio or video jack plug.

Abstract: A data storage architecture extension (DAX) system and method that permits multiple disk drive storage elements to be logically daisy-chained to allow a single host bus adapter (HBA) to view the storage elements as one logical disk drive is disclosed. The system/method may be broadly described as comprising a pass-thru disk drive controller (PTDDC) further comprising a HBA port, a disk drive interface port, pass-thru input port, and a pass-thru output port. The PTDDC intercepts and translates the HBA port input to the requirements of an individual disk drive connected to the drive interface port. Each PTDDC may be daisy-chained to other PTDDCs to permit a plethora of disk drives to be associated with a given HBA, with the first PTDDC providing a presentation interface to the HBA integrating all disk drive storage connected to the PTDDCs. The system/method also permits RAID configuration of disk drives using one or more PTDDCs.

Abstract: A method, apparatus and computer program product are provided herein to enable buffer initialization and/or clearance to occur on, for example, a mobile terminal. In some example embodiments, a method is provided that comprises receiving an indication that a buffer has been initialized by a host. The method of this embodiment may also include receiving source code from the host. In some example embodiments, the source code is received from a program running on the host and is configured to cause the buffer that has been initialized by the host to be cleared. The method of this embodiment may also include executing the source code such that the buffer that has been initialized by the host is cleared.

Abstract: A fast masked summing comparator apparatus includes a comparator unit configured to compare a masked first number to a masked sum of a second number and a third number to determine whether the masked sum is equivalent to the masked first number without performing a summation portion of an addition operation between the second number and the third number. The comparator unit may concurrently mask both the sum and the first number using the same mask value.

Abstract: A power consumption of a semiconductor integrated circuit is reduced. A semiconductor integrated circuit comprises a first path P1 for performing data processing in a data processing circuit and a second path P2 for bypassing the data processing circuit or for performing data processing in a simplified circuit. The semiconductor integrated circuit exclusively selects the first path and the second path depending on an operational mode, and stops a data input into a path that is not selected, resulting in a reduction of the power consumption.

Abstract: A method for data transfer includes receiving in an input/output (I/O) operation a first segment of data to be written to a specified virtual address in a host memory. Upon receiving the first segment of the data, it is detected that a first page that contains the specified virtual address is swapped out of the host memory. At least one second page of the host memory is identified, to which a second segment of the data is expected to be written. Responsively to detecting that the first page is swapped out and to identifying the at least one second page, at least the first and second pages are swapped into the host memory. After swapping at least the first and second pages into the host memory, the data are written to the first and second pages.

Abstract: A peripheral component interconnect (PCI) express switch apparatus and a method of controlling a connection thereof are provided. In this apparatus, a first virtual bridge is connected to a computer system through a first PCI express port to perform data transmission and reception according to a PCI method with an external device, and a second virtual bridge is connected to an external device through the first virtual bridge and a second PCI express port and enables the external device to perform data transmission and reception with the computer system and according to the PCI method by cooperating with the first virtual bridge. A first cable matching device is connected to the first virtual bridge. Further, a second cable matching device is connected to the second virtual bridge and is connected to the first cable matching device through a PCI cable.

Abstract: Provided are devices and methods for transmitting two or more data streams through the same cable. An exemplary cable includes at least two sets of conductive points, each set capable of independently transmitting a separate data stream. The cable may be a USB 2.0 type cable, with two contacts assigned for transmitting one data stream, and two other contacts assigned for transmitting another data stream. In some embodiments, one data stream is an audio-video signal transmitted to an audio-video receiver.

Abstract: In a Universal Serial Bus (USB) enumeration procedure, a USB Host questions a USB Device for its capabilities and chooses a set of capabilities that best fit. When the USB Device is enumerated, the USB Host may perform several time-consuming and power-consuming operations. However, when the USB Device is tightly or permanently coupled to the USB Host, part of the enumeration procedure may be redundant and can be eliminated. Accordingly, a method, an apparatus, and a computer program product for shortening enumeration of the USB Device tightly coupled to the USB Host are provided. The USB Host sends a request for a Device descriptor to the USB Device, receives a plurality of descriptors in a single transfer from the USB Device, and sets a configuration of the USB Device based on the received plurality of descriptors.

Abstract: Embodiments of the invention are directed to input devices configured for use with computing devices. The present invention relates to methods and devices for establishing, maintaining and managing, wireless connections with between an input device and one or more host devices that the input device is paired with. The input device may include sensory feedback indicating the host device actively paired with the input device, and may enable switching between host devices.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.