Abstract: A method and system for creating and navigating linear hypermedia resource programs are disclosed. The system includes a distributed hypermedia resource network having a plurality of hypermedia resources residing on one or more remote information nodes. A common remote information node is in communication with a subscriber station and the remote information nodes in the distributed network. The common remote information node contains at least one linear hypermedia resource program consisting of pre-selected media elements from one or more hypermedia resources linked with exclusive linear links, each media element in the linear program having only one forward link to the next media element. The method includes the steps of downloading and displaying a media element in the linear program and responding to user commands to download and display the next media element in the linear program.

Abstract: A process of forming an identification marking within article formed from an at least partially optically transparent material for identification and validation, said process including the steps of (i) forming an indicia with an at least partially optically transparent material by way of subsurface laser engraving (SSLE); and (ii) forming a plurality of defects within or adjacent indicia within said at least partially optically transparent material resultant of the step of forming the indicia and from localized heating and irregularities in said at least partially optically transparent material, wherein said plurality of defects forms said identification marking.

Abstract: A system and method for full-duplex communications provided by modifying the Media Access Control sub-layer of communication node protocols. The modification allows communication nodes to communicate with one another in full-duplex, where each node transmits and receives data simultaneously with other nodes in a single frequency. A timing of the simultaneous data transmissions, acknowledgments, and short-interframe-space waiting periods can be determined based on network-allocation-vector data transmitted in association with request-to-send or clear-to-send signals.

Abstract: A method and system for supplying a digital video signal from a source to a sink are described. The digital video signal includes digital video data for three different colors and a pixel clock signal, such as DVI and HDMI. The digital video data and the pixel clock signal are received at a transmitter which sends a signal representative of the frequency of the pixel clock signal over a cable connecting the transmitter and a receiver. Digital video data for three different colors is sent over three different twisted wire pairs of the cable to the receiver. A local pixel clock signal is generated at the receiver using the signal representative of the frequency of the pixel clock signal. The local pixel clock signal is used to process the received digital video data and recovered digital video data and the local pixel clock signal are output.

Abstract: The present invention is intended to permit both real-time display of a picture represented by a non-compressed video signal on a television and display of a picture represented by a compressed video signal at any desired time by simultaneously transmitting the compressed video signal and non-compressed video signal via one interface. An STB packetizes a compressed video signal, and multiplexes the compressed video signal and a blanking signal combined with a non-compressed video signal. Thus, both the video signals are transmitted simultaneously. A picture represented by the non-compressed video signal is displayed on a television in real time. The compressed video signal is stored in a storage medium incorporated in the television, read at any user's desired time, and decoded so that a picture represented by the compressed video signal can be viewed at the user's desired time.

Abstract: According to one general aspect, a method may include executing, by a processor of a computing device, at least a portion of an application that includes a plurality of tabs, each tab associated with a respective document that is configured to be rendered for display by the application. The method may also include determining a particular tab of the plurality of tabs that is recording an audio and/or visual signal derived from an environment of the computing device. The method may further include providing a graphical indication, associated with the particular tab, that indicates to a user of the computing device that the particular tab is recording the audio and/or visual signal.

Abstract: Dynamic power routing is utilized to route power from other components, which are transitioned to lower power consuming states, in order to accommodate more efficient processing of computational tasks by hardware accelerators, thereby staying within electrical power thresholds that would otherwise not have accommodated simultaneous full-power operation of the other components and such hardware accelerators. Once a portion of a workflow is being processed by hardware accelerators, the workflow, or the hardware accelerators, can be self-throttling to stay within power thresholds, or they can be throttled by independent coordinators, including device-centric and system-wide coordinators.

Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.

Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic and a display controller. The display controller includes a first interface coupled to receive coded data, a renderer to generate display-agnostic data from the coded data, a transmitter to generate display data from the display-agnostic data in accordance with a first protocol, a second interface coupled to provide the display data as output, and a third interface coupled to provide the display-agnostic data to the programmable logic.

Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.

Abstract: Disclosed is a mobile terminal network port management method and device. The method includes: after PPPOE dial up completes, scanning current mobile network equipment port numbers and acquiring currently occupied mobile network ports; detecting and analyzing whether the currently occupied mobile network ports are virtually occupied ports or not; if yes, releasing said virtually occupied ports. The abovementioned technical solution solves an existing problem of possible virtual occupancy of network ports after a PPPOE connection is established, thereby greatly enhancing availability of the mobile terminal and improving the user experience on the terminal.

Abstract: Described herein are techniques for cancelling I/O requests. Initially, virtual memory of an application is assigned to a first portion of memory. The application may issue a read request to an external device. The external device is instructed to record any response to the read request in the first portion of memory. The read request may be cancelled as follows. The virtual memory of the application may be re-assigned to a second portion of the memory. If and when the external device finishes processing the read request, the external device's response to the read request may still be saved in the first portion of memory, even though the read request has been cancelled. Such action of the external device would ordinarily corrupt the virtual memory of the application, but due to the memory re-assignment, no corruption of the virtual memory occurs. Similar techniques may be applied to cancel write requests.

Abstract: A method includes configuring one or more network nodes in a radio access network using information to be used by the one or more network nodes to determine whether an event detected by the one or more network nodes and associated with the radio access network should be reported. Another method includes configuring a network node in a radio access network using information to be used by the network node to determine whether an event detected by the network node and associated with the radio access network should be reported. Responsive to the configuring, the network node may or may not report the event. Apparatus, computer programs, computer program products, and communication systems are also disclosed.

Abstract: A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

Abstract: A magnetic resonance imaging (MRI) system, method and/or apparatus is configured to effect MR imaging where data corresponding to MR signals is transmitted from a radio frequency (RF) receive coil to the MRI data processor via a path that includes a near-field wireless communication (NFC) connection. A receiver for the NFC connection is selected from of the one or more wireless signal receivers that are arranged on a restraining belt when the restraining belt is placed, during operation of an MRI system for imaging an object located on a patient table, over at least a portion of the object and the receive RF coil is located between the restraining belt and the object.

Abstract: A subassembly for an integrated wireless module is provided. The subassembly includes an integrated-wireless-module input/output (I/O) connector, a modem controller; at least one internal antenna, and at least two modem connectors communicatively coupled to the modem controller, the modem connectors configured to interface with at least two modems. The modem controller digitally selects to one of: communicatively couple one of the at least two modem connectors to one of the at least one internal antenna; communicatively couple one of the at least two modem connectors to the integrated-wireless-module I/O connector; and communicatively couple a first one of the at least two modem connectors to one of the at least one internal antenna and communicatively couple a second one of the at least two modem connectors to the integrated-wireless-module I/O connector.

Abstract: Embodiments of the present invention relate to a peripheral component interconnect express endpoint device accessing method, a computer system, and an apparatus. A state of an access request sent by a processor is monitored, and a simulation response message for the access request is sent to the processor when it is determined that the PCIe endpoint device sends no response message for the access request. Therefore, according to the simulation response message, the processor can confirm completion of the procedure corresponding to the previously sent access request, and shut down a timer for timing the access request and clear the buffered access request, thereby keeping normal processing in the processor and avoiding the MCE resetting problem that arises from accumulation of access requests in the processor.

Abstract: Methods and systems for associating a mobile station subscriber with at least one application or service are provided. The subscriber is provided with a subscriber identity module (“SIM”) identifier, which identifies a SIM associated with the subscriber. The SIM identifier is bound to the application or service. The SIM identifier and the application or service are registered with a home location register (“HLR”) to bind the SIM identifier to the application or service. If the SIM is a virtual SIM, the provider of an application or service may cover the data costs associated with the use of that application or service.

Abstract: Embodiments of the present invention relate to a peripheral component interconnect express endpoint device accessing method, a computer system, and an apparatus. A state of an access request sent by a processor is monitored, and a simulation response message for the access request is sent to the processor when it is determined that the PCIe endpoint device sends no response message for the access request. Therefore, according to the simulation response message, the processor can confirm completion of the procedure corresponding to the previously sent access request, and shut down a timer for timing the access request and clear the buffered access request, thereby keeping normal processing in the processor and avoiding the MCE resetting problem that arises from accumulation of access requests in the processor.

Abstract: A cable backplane system includes a backplane having a plurality of openings extending between a front and a rear of the backplane. The backplane has mounting locations proximate the openings. Mounting blocks are coupled to the front of the backplane at corresponding mounting locations. The mounting blocks are secured to the backplane by fasteners. A cable rack is coupled to the rear of the backplane and has a tray with a frame surrounding a raceway and spacers coupled to the tray. The spacers hold corresponding cable connectors and are secured to corresponding mounting blocks to position the spacers and cable connector assemblies relative to the backplane. The cable connectors are received in corresponding openings in the backplane and are held in position relative to the backplane by the spacers and mounting blocks.

Abstract: We disclose an optical receiver that can receive PDM-QDB and PDM-QPSK signals without hardware changes. In an example embodiment, the optical receiver includes a MIMO equalizer configured to perform electronic polarization de-multiplexing and ISI compensation. The constant modulus algorithm that controls the configuration of the MIMO equalizer also causes the MIMO equalizer to output signal samples corresponding to the QPSK modulation format regardless of whether the received optical signal is QDB-modulated or QPSK-modulated. A QPSK-to-QDB constellation converter processes the signal samples generated by the MIMO equalizer to convert them into the QDB modulation format. A QDB decoder coupled to the constellation converter then recovers the data encoded in the received optical signal by mapping the processed signal samples onto the QDB constellation.

Abstract: System and method for remotely performing a power cycle operation for a storage shelf of a storage server using a control path independent of a data path used for processing I/O requests is provided. The storage server maintains a data structure for storing information regarding a state of a plurality of power latches that are used to control power for the storage shelf having an alternate control path module for receiving control commands via the control path. Depending on the state of the plurality of power latches, the storage server sends one or more commands to the alternate control path module to turn off power to the storage shelf during a power cycle operation. When the power shelf is powered off, the storage server waits for a certain duration and then sends one or more power on commands to the alternate control path module to power on the storage shelf.

Abstract: Method and system for configuring a port of a network device are provided. One method for a port of a network device communicating with another network device port includes reading manufacturing, license and user provided port configuration data by a processor of the network device; obtaining capabilities information for the port by the processor of the network device from an external pluggable media device; setting port configuration data based on the capabilities information obtained from the external pluggable media; executing auto-negotiation on the port, when enabled and obtaining configuration data from the other port; determining that enough data is available to set port configuration; attempting to configure the port by using a highest permissible bandwidth configuration when enough data is available to set the port configuration; and setting port configuration based on the attempt to configure the port to operate when a link connected to the port is operational.

Abstract: A display apparatus and method are disclosed. The display apparatus according to the present disclosure includes a plurality of terminals, a display unit which displays a selection screen for selecting an external device to be connected to the display apparatus, and a control unit which controls the display unit to display a terminal image which shows a placement of the plurality of terminals and a guiding image for guiding to a terminal which corresponds corresponding to the selected external device from among the plurality of terminals when an external device is selected through the selection screen. Accordingly, a user may easily and quickly connect a connector of the external device to the terminal of the display apparatus.

Abstract: A method of charging a battery of a device using a battery of a computer powered by the battery, in which the procedure is implemented by a circuit independent of the computer's processors. The method includes supplying a power supply voltage, insufficient to charge a battery, to a computer port, as long as a device is detected as connected to the port, controlling the supply of a charging voltage to the port, while supplying charging voltage to the port, detecting an end of charging condition of a battery of the device, and controlling the cutting off of the charging voltage to the port if the end of charging condition is detected, where this condition is determined according to the intensity of a charging current and according to a quantity of electrical charge supplied to the port and/or of a charging period.

Abstract: A locking apparatus is configured to lock a first panel and a second panel to a computer device. The locking apparatus includes a lock rotatable between a first position and a second position, a mounting panel, a driving lever pivotably attached on the mounting panel, a blocking member attached to the mounting panel, and a latch member. When moved to the first position, the rotatable post rotates the driving lever, the driving lever pushes the latch member to unlatch from the second panel, and the rotatable post is disengaged from the blocking member to unlock the first panel. When moved to the second position, the rotatable post is blocked by the blocking member for locking the first panel, the driving lever is rotated to its original position, and the latch member latches the second panel.

Abstract: A method includes determining, by a management controller of a first server in a storage network, if a first virtual initiator is used by a second server in the storage network, wherein the first virtual initiator includes first boot information for allocating a first storage resource of the storage network, aborting a boot up of the first server in response to determining that the first virtual initiator is being used by the second server, and proceeding with the boot up of the first server in response to determining that the first virtual initiator is not used by the second server, wherein the boot up proceeds using the first boot information to allocate the first storage resource to the first server.

Abstract: A data storage RAID architecture system and method that daisy-chains multiple SATA disk drive storage elements to allow a single host bus adapter (HBA) to view the daisy-chain as one logical SATA disk drive is disclosed. The system/method may be broadly described as comprising a pass-thru disk drive controller (PTDDC) further comprising a pass-thru input (PTI) port, disk drive interface (DDI) port, and pass-thru output (PTO) port. The PTDDC intercepts and translates PTI port input to the requirements of a SATA disk drive connected to the DDI. Each PTDDC may be daisy-chained to other PTDDCs to permit a plethora of SATA drives to be associated with a given HBA, with the first PTDDC providing a presentation interface to the HBA integrating all SATA disk drive storage connected to the PTDDCs. Rack mounting of PTDDC-enabled SATA disk drives enables creation of inexpensive dynamically expandable petabyte-class RAID storage arrays.

Abstract: Systems and methods for analyzing the risk associated with lenders offering vehicle loans is determined based on historical data associated with the vehicle. Vehicle registration data for a region is accessed to determine the vehicles registered in the region and the lien holders of the vehicles. Historical data of the vehicles is accessed and analyzed to determine if any events adversely affecting the value of the vehicles, such as vehicle title brands, are associated with the vehicles. The vehicle history data is associated with the lien holders of the vehicles. A risk value may be determined for each lien holder by comparing the lien holder's total number of liens to those liens on vehicles associated with history events adversely affecting the value of the vehicle.

Abstract: A Storage Area Network (SAN) system has host computers, front-end SAN controllers (FE_SAN) connected via a bus or network interconnect to back-end SAN controllers (BE_SAN), and physical disk drives connected via network interconnect to the BE_SANs to provide distributed high performance centrally managed storage. Described are hardware and software architectural solutions designed to eliminate I/O traffic bottlenecks, improve scalability, and reduce the overall cost of SAN systems. In an embodiment, the BE_SAN has firmware to recognize when, in order to support a multidisc volume, such as a RAID volume, it is configured to support, it requires access to a physical disk attached to a second BE_SAN; when such a reference is recognized it passes assess commands to the second BE_SAN. Buffer memory of each FE_SAN is mapped into application memory space to increase access speed, where multiple hosts share an LBA the BE_SAN tracks writes and invalidates the unwritten buffers.

Abstract: A system for condition monitoring and fault diagnosis includes a data collection function that acquires time histories of selected variables for one or more of the components, a pre-processing function that calculates specified characteristics of the time histories, an analysis function for evaluating the characteristics to produce one or more hypotheses of a condition of the one or more components, and a reasoning function for determining the condition of the one or more components from the one or more hypotheses.

Abstract: Method and system for configuring a receive packet queue in a network device are provided. The method includes determining how many sub-ports of a port of the network device are configured; assigning memory to each of the configured sub-ports based on the determination of how many sub-ports are configured; determining a flow control scheme to be used for packet transmission; and dividing the receive packet queue based on the determination of the flow control scheme to be used.

Abstract: A method initiates boot of a multi-node system including a first compute node scaled together with a second compute node, wherein the multi-node system boots from a basic input output system of the first compute node that is identified as a primary node by a trusted platform module of the first compute node. The method further includes receiving a request to reconfigure the multi-node system so that the second compute node would become the primary node, and reconfiguring the multi-node system so that the second node is the primary mode only in response to a user manually asserting physical presence to a trusted platform module of the first compute node. A system provides compute nodes that each include a trusted platform module having first and second non-volatile indices for controlling the configuration of the multimode system.

Abstract: A dispersed storage network memory includes a pool of storage nodes, where the pool of storage nodes stores a multitude of encoded data files. A storage node obtains and analyzes data access response performance data for each of the storage nodes to produce a modified data access response plan that includes identity of an undesired performing storage node and an alternative data access response for the undesired performing storage node. The storage nodes receive corresponding portions of a data access request for at least a portion of one of the multitude of encoded data files. The undesired performing storage node or another storage node processes one of the corresponding portions of the data access request in accordance with the alternative data access response.

Abstract: A processor having a streaming unit is disclosed. In one embodiment, a processor includes one or more execution units configured to execute instructions of a processor instruction set. The processor further includes a streaming unit configured to execute a first instruction of the processor instruction set, wherein executing the first instruction comprises the streaming unit loading a first data stream from a memory of a computer system responsive to execution of a first instruction. The first data stream comprises a plurality of data elements. The first instruction includes a first argument indicating a starting address of the first stream, a second argument indicating a stride between the data elements, and a third argument indicative of an ending address of the stream. The streaming unit is configured to output a second data stream corresponding to the first data stream.

Abstract: A data storage device includes a first memory device configured to store data having a first property, a second memory device configured to store data having a second property, and a controller. The controller selects data stored in the first memory device, and transfers the selected data to the second memory device or stores the selected data in another physical location of the first memory device selectively depending on an update count (UC) of an address at which the selected data is stored.

Abstract: A virtual machine (VM) migration from a source virtual machine monitor (VMM) to a destination VMM on a computer system. Each of the VMMs includes virtualization software, and one or more VMs are executed in each of the VMMs. The virtualization software allocates hardware resources in a form of virtual resources for the concurrent execution of one or more VMs and the virtualization software. A portion of a memory of the hardware resources includes hardware memory segments. A first portion of the memory segments is assigned to a source logical partition and a second portion is assigned to a destination logical partition. The source VMM operates in the source logical partition and the destination VMM operates in the destination logical partition. The first portion of the memory segments is mapped into a source VMM memory, and the second portion of the memory segments is mapped into a destination VMM memory.

Abstract: An electronic device, including: one or more hardware interfaces each for connecting to a signal source to receive at least one type of application resources; a control chip electrically connected to the one or more hardware interfaces, the control chip being configured to classify and integrate one or more types of application resources received through the one or more hardware interfaces, and generate a display signal for a main interface including a number of areas arranged according to a predetermined layout, wherein each area is configured to display information regarding a same type of the classified and integrated application resources, and different areas are configured to display information regarding different types of the classified and integrated application resources; and a display screen electrically connected to the control chip to display the main interface according to the display signal.

Abstract: Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages.

Abstract: Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state.

Abstract: A data acquisition system includes a receptacle and a data acquisition device. The receptacle has a housing, sensor inputs to receive data signals from sensors coupled to an object, and a rib to block insertion of a standard Universal Serial Bus (USB) plug and facilitate insertion of a modified USB plug having a slot that mates with the rib. The data acquisition device includes circuitry to receive, store and process data, a USB plug having pins operatively coupled to the circuitry, a first subset of pins configured to receive data signals from the receptacle and a second subset of pins configured to support standard USB communication with USB-compliant devices, and a slot formed in the USB plug such that the slot facilitates interconnection of the USB plug both with standard USB-compliant devices and with the receptacle, the slot mating with the rib to facilitate interconnection.

Abstract: Systems and methodologies are described that facilitate utilizing timers in conjunction with transmitting buffer status reports (BSR). A prohibit timer can be utilized to determine when BSRs can be transmitted to an eNB. The prohibit timer can be initialized or restarted upon transmitting a BSR to an eNB. A BSR retransmit timer can be used to determine when to retransmit a BSR. The BSR retransmit timer can be initialized upon transmitting a BSR to an eNB and restarted each time an uplink resource allocation is received from the eNB. Once the timer expires, if an uplink transmission buffer contains data (e.g., size>0), the BSR can be retransmitted to the eNB. Control data feedback can additionally be used to determine when to retransmit the BSR. In addition, in either case, the timer duration values can be provided by the eNB.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: A method for processing a first input/output (I/O) request on a network attached storage (NAS) device that includes receiving the first I/O request from a source by the NAS device, placing the first I/O request in an I/O queue associated with the NAS device, wherein the first I/O request is placed in the I/O queue based on a priority of the first I/O request using a remote storage access protocol, and when the first I/O request is associated with the highest priority in the I/O queue, determining whether a bandwidth associated with the source of the first I/O request is exceeded, processing the first I/O request if the bandwidth associated with the source of the first I/O request is not exceeded, and placing the first I/O request in sleep mode if the bandwidth associated with the source of the first I/O request is exceeded.

Abstract: An operating method of a semiconductor device includes selecting a block requiring storage space recycling from a memory device, checking costs required for performing the respective recycling techniques, selecting one of the recycling techniques based on the costs, and recycling a storage space by applying the selected recycling technique to the selected block.

Abstract: A data storage architecture extension (DAX) system and method that daisy-chains multiple SATA disk drive storage elements to allow a single host bus adapter (HBA) to view the daisy-chain as one logical SATA disk drive is disclosed. The system/method may be broadly described as comprising a pass-thru disk drive controller (PTDDC) further comprising a pass-thru input (PTI) port, disk drive interface (DDI) port, and pass-thru output (PTO) port. The PTDDC intercepts and translates PTI port input to the requirements of a SATA disk drive connected to the DDI. Each PTDDC may be daisy-chained to other PTDDCs to permit a plethora of SATA drives to be associated with a given HBA, with the first PTDDC providing a presentation interface to the HBA integrating all SATA disk drive storage connected to the PTDDCs. Rack mounting of PTDDC-enabled SATA disk drives enables creation of inexpensive dynamically expandable petabyte-class storage arrays.

Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Abstract: In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the computing device, that may be executing a basic input/output system (BIOS) associated with the computing device. The request may include a request for a value that may represent a maximum authorized storage size for a storage contained in the computing device. The control unit may generate the value and send the value to the CPU. The CPU may generate a system address map based on the value. The CPU may send the system address map to the control unit which may acquire the system address map and configure an address decoder, contained in the computing device, based on the acquired system address map.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: A BIOS storage unit of an electronic device is connected to a USB 3.0 extension unit of a USB 3.0 host connector. A microcomputer of a USB compatible device is connected to a USB 3.0 extension unit of a USB 3.0 device connector. The microcomputer of the USB compatible device can write and read the BIOS data to/from the BIOS storage unit of the electronic device through the USB 3.0 extension units. Moreover, the microcomputer of the USB compatible device compares the BIOS data read from the BIOS storage unit of the electronic device with the BIOS data stored in its own storage unit, and notifies a result of the comparison.