Abstract: To improve data throughput and data transfer rate, a contiguous block of host memory can be allocated for data transfers between the host system and an integrated circuit device such as a peripheral component. By using a contiguous block of memory that acts as a circular buffer, the memory address field of memory descriptors can be eliminated because the host system only need to inform the data movement engine of the length of each data transfer. The data movement engine can maintain pointers to keep track of the memory address in the host memory to read from and write to. After each data transfer, the relevant pointer can be incremented by a value corresponding to the length indicated in the memory descriptor for the transfer. As such, it is not necessary for the host system to provide the data movement engine with the memory address of each transfer.

Abstract: A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

Abstract: A graphics processing unit may, in accordance with a kernel, determine that at least a first packet is written to a memory buffer of the graphics processing unit by a network interface card via a direct memory access, process the at least the first packet in accordance with the kernel, and provide a first notification to a central processing unit that the at least the first packet is processed in accordance with the kernel. The graphics processing unit may further determine that at least a second packet is written to the memory buffer by the network interface card via the direct memory access, process the at least the second packet in accordance with the kernel, where the kernel comprises a persistent kernel, and provide a second notification to the central processing unit that the at least the second packet is processed in accordance with the kernel.

Abstract: Devices, methods and instruction sets are provided for performing operations with respect to analyzing firmware. A firmware event tracker includes a tracker event log in which events occurring during execution of firmware are recorded as event-items and stored in volatile. Flushing of event-items from volatile memory to non-volatile memory via a flush strategy and flush access path. In other aspects, the stored tracker event log, is used for performing failure analysis of the firmware.

Abstract: Disclosed is an interference canceller capable of generating a cancellation signal for reducing cross port alien near-end (XPAN) crosstalk of a reception signal received by a receiver of a network device.

Abstract: Secure computer architectures, systems, and applications are provided herein. An exemplary system includes a legacy environment which is an off-the-shelf computing system, a trusted environment device that communicates with a network, and at least one peripheral that is communicatively coupled with the trusted environment device or having an authentication module.

Abstract: The invention introduces a method for uninstalling SSD (Solid-state Disk) cards, performed by a processing unit when loading and executing a driver, including at least the following steps: reading the value of the register of an SSD card on which there is an access attempt according to a data access command in the time period between reception of the data access command from an application and transmission of a data access request corresponding to the data access command to lower layers; and executing an uninstall procedure when detecting that the SSD card has been removed according to a result of the reading.

Abstract: A sensor module includes a first sensor device, a second sensor device, and a microcontroller. The first sensor device includes a first synchronization terminal to which an external synchronization signal or a synchronization signal which is a signal based on the external synchronization signal is input, a first interface outputs first measurement data to the microcontroller on the basis of the synchronization signal which is input to the first synchronization terminal, the second sensor device includes a second synchronization terminal to which the synchronization signal is input, and a second interface outputs second measurement data to the microcontroller on the basis of the synchronization signal which is input to the second synchronization terminal.

Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.

Abstract: A wireless data transceiver includes a media access controller (MAC) configured to receive an inbound data packet from an air interface and to buffer the inbound packet for transport to a host, and to receive an outbound data packet from elsewhere in the transceiver and to transfer the outbound packet to the air interface. The transceiver further includes a host interface configured to receive the inbound packet transported from the MAC and to transfer the inbound packet to the host, and to receive the outbound packet from the host for transfer to the MAC. The transceiver also includes transport controller circuitry configured to execute instructions to generate and transfer management packets. In addition, the wireless data transceiver includes hardware data transport circuitry for transporting the inbound packet from the MAC to the host interface, and for transporting the outbound packet from the host interface to the MAC, without executing instructions.

Abstract: System, methods, and media are provided for enforcing segmentation of multi-tenant data. An example method includes informing hardware of direct memory access (DMA) segmented regions, in which the hardware is informed of software-specified size and count parameters relating to DMA windows. Identifying an originating DMA window for each DMA descriptor and referenced data. Verifying that contents of one or more DMA transfers are entirely from memory controlled by a single process. Setting DMA window-describing registers based the software-specified size and count parameters. Enforcing restrictions, based on the DMA window-describing registers, for DMA requests relating to the DMA windows as DMA requests are received.

Abstract: A server system may be configured to access a first contiguous portion of memory for a first activity of a plurality of activities, and to transfer data associated with the first activity into the first contiguous portion of memory. The first contiguous portion of memory may be placed in a memory repository to make the first contiguous portion of memory available for access by at least a second activity of the plurality of activities, and an identifier may be assigned to the first contiguous portion of memory placed in the memory repository. The server system may also be configured to access the first contiguous portion of memory for the second activity, and to transfer the data associated with the first activity from the first contiguous portion of memory to memory specifically associated with the second activity.

Abstract: Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

Abstract: Some embodiments of the invention provide a network forwarding element that includes a set of data plane circuits with several configurable packet processing stages for receiving and processing incoming packet traffic to the forwarding element. The forwarding element also includes a set of control plane circuits that include a set of direct memory access (DMA) buffers for configuring the configurable packet processing stages of the data plane. The control plane loads configuration data for reconfiguring the data plane packet processing stages into the set of DMA buffers while the data plane packet processing stages are processing the incoming packet traffic. The control plane pauses the incoming packet traffic to the data plane packet processing stages. The control plane loads the configuration data from the DMA buffers into the data plane packet processing stages. The control plane resumes the incoming packet traffic to the data plane packet processing stages.

Abstract: A data communication apparatus for performing communication of data with a master device via a bus includes a clock control signal generation circuit that outputs a clock control signal corresponding to a reset state and a communication state of the data communication apparatus, a communication start detection circuit that detects a start of communication on the basis of a clock signal on the bus and the data, a clock generation circuit that generates an internal clock signal on the basis of the clock signal on the bus, and a data processing control circuit that receives the internal clock signal and controls communication of the data with the master device. The clock generation circuit stops generating the internal clock signal in accordance with the clock control signal, in the reset state of the data communication apparatus and in a period from release of the reset state to the start of communication.

Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.

Abstract: An encoder for generating an optical data code from a symbol performs a symbol mapping and an encoding, wherein the symbol mapping performs providing a first constellation format having first and second amplitude rings with circular grids corresponding to phase angles, providing a second constellation format having the first and second amplitude rings with the circular grids corresponding to the phase angles, applying a first part of the symbol to one of the first and second constellation formats to represent the first part of the symbol by one of the first and second amplitude rings with one of the circular grids, and applying a second part of the symbol to another one of the first and second constellation formats to represent the second part of the symbol by one of the first and second amplitude rings with one of the circular grids. The first and the second constellation can be mapped to subcarrier modulation in three different ways.

Abstract: A method for performing dynamic resource management in a memory device, the memory device, and a controller thereof are provided. The memory device includes a non-volatile (NV) memory, and the NV memory includes a plurality of NV memory elements. The method may include: storing a plurality of sets of physical region descriptor (PRD) information related to a plurality of host commands, respectively, and storing a plurality of intermediate PRDs respectively corresponding to the plurality of sets of PRD information into a first queue; obtaining an intermediate PRD of the plurality of intermediate PRDs from the first queue, and storing the intermediate PRD into a second queue; sending a command to the NV memory according to the intermediate PRD in the second queue to access data; and when an operation of accessing the data is successful, releasing the intermediate PRD from the second queue to the first queue.

Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Abstract: An information exchange between at least two processes (FEED_PROC-1, FEED_PROC-2, CONSUME_PROC-1) communicating with each other using at least one queue (QUEUE-001) uses a placement plan for determining the order in which messages are placed into the queue. The information feeding processes (FEED_PROC-1, FEED_PROC-2) place pieces of information (MESG-001, MESG-002) into the queue (QUEUE-001), from where an information consuming process (CONSUME_PROC-1) sequentially consumes the pieces of information. The placement plan describes, for at least one possible value of identifying information contained in each of the pieces of information, a respective position (POS-001, POS-002) in the queue (QUEUE-001), such that the pieces of information (MESG-001, MESCG-002) or respective references thereto are placed into the queue according to positions in the queue (QUEUE-001) corresponding to the respective values of the identifying information in the pieces of information.

Abstract: In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.

Abstract: Systems and methods for a direct memory access (DMA) operation are provided. The method includes receiving a host memory address by a device coupled to a computing device; storing the host memory address at a device memory by a DMA engine; receiving a packet at the device for the computing device; instructing the DMA engine by a device processor to retrieve the host memory address from the device memory; retrieving the host memory address by the DMA engine without the device processor reading the host memory address; and transferring the packet to the computing device by a DMA operation.

Abstract: A data processing system may have a strict separation of processor tasks and data categories, wherein processor tasks are separated into software loading and initialization (loading processor) and data processing (main processor) and data categories are separated into address data, instructions, internal function data, target data of the main processor and target data of the loading processor. In this way, protection is provided against malware, irrespective of the transmission medium and of the type of malware, and also against future malware and without performance losses in the computer system.

Abstract: A method for configuring a transfer of signals associated with an iterative and synchronized, time-based data acquisition (DAQ) operation between at least one input device and at least one output device is disclosed herein. The method includes requesting and receiving signal data samples (SDSs) from the at least one input device. A series of the SDSs are mapped to a buffer. The time indicators of SDSs are compared to confirm that SDSs are incrementally-next in time relative one another. A missing signal data sample is retransmitted if necessary. The series of SDSs is remapped in the buffer as necessary to arrange the series in time sequence. The method also includes transmitting in real time at least a portion of the present signal data sample to an output device prior to receiving the missing signal data sample.

Abstract: Provided are techniques for sharing a partitioned data set across parallel applications. Under control of a producing application, a partitioned data set is generated; a descriptor that describes the partitioned data set is generated; and the descriptor is registered in a registry. Under control of a consuming application, the registry is accessed to obtain the descriptor of the partitioned data set; and the descriptor is uses to determine how to process the partitioned data set.

Abstract: Systems and methods for self-checking a direct memory access system are disclosed. These may include generating a check sum value associated with a first job of the plurality of jobs, the first job comprising a read job; if a first predetermined check value is available, comparing the first check sum value with the first predetermined check value; generating a second check sum value associated with a last job of the plurality of jobs, the last job comprising a write job; if a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and if the second predetermined check value is not available, comparing the first check sum value with the second check sum value.

Abstract: The present application is directed towards systems and methods for systems and methods for handling real-time streaming protocol sessions by an intermediary multi-core system. When a multi-core intermediary receives a setup request for a real-time streaming protocol session, the intermediary processes and forwards the request to a server providing the streaming media. The server sets up an RTSP session and transmits a session identification to the multi-core intermediary. A core of the intermediary receives the transmitted session identification and determines an owner core of the session, based on a hash of the session identification. The core transmits the session information to the determined owner core, which selects two consecutive ports on which to establish listening services. The owner core then notifies all other cores to establish listening services on the same consecutive ports, such that any core that receives an RTSP control message from a client can handle it properly.

Abstract: Systems and methods are disclosed for hardware assisted format changes in a display controller. One embodiment of the invention relates to a format change system comprising a register DMA controller and a register update list. The register update list contains at least one instruction. The register DMA controller is adapted to obtain and use at least one instruction to configure at least one display pipeline from a plurality of display pipelines in response to at least one trigger event.

Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.

Abstract: Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

Abstract: A cache memory device includes a plurality of cache areas, each the cache area comprising a plurality of entries. The cache memory device is configured to maintain a separate lock attribute for each the cache area and temporarily assign possession of a lock attribute for a particular the cache area to a processor thread attempting to update the particular the cache area, the processor thread being unable to update the particular the cache area without possession of the lock attribute for the particular the cache area.

Abstract: A serial advanced technology attachment (SATA) module includes a number of circuit boards and a number of SATA devices. Each of the circuit boards includes an expansion microchip. The expansion microchip includes an input terminal, an output terminal and an expansion terminal. The expansion microchips are electrically connected in series with the input terminal of one expansion microchip connecting to the expansion terminal of another expansion microchip. The input terminal of a front expansion terminal positioned at a first end of the expansion microchips is configured to connect to a SATA controller. Each of the SATA devices is electrically connected to the output terminal of one expansion microchip and configured to transmit data with the SATA controller by the corresponding expansion microchip.

Abstract: A communication terminal includes a storage section that stores a file to be transmitted to an opponent terminal, a communication section that transmits the file to the opponent terminal, a cluster information calculation section that determines cluster information about clusters, and a DMA transfer section that DMA-transfers the file from the storage section to the communication section on the basis of the cluster information about the clusters to be transferred determined by the cluster information calculation section. The cluster information calculation section determines cluster information about clusters to be transferred next during the course of the DMA transfer.

Abstract: Presented herein are system(s) and method(s) for faster throughput for video decoding. In one embodiment, there is presented a pixel reconstructor for generating reconstructed pixels. The pixel reconstructor comprises a SIMD processor, a data access unit, and a circuit. The SIMD processor applies at least one prediction error to at least one block of prediction pixels. The data access unit provides the at least one prediction error and the at least one block of prediction pixels. A circuit determines whether two or more prediction errors and two or more prediction pixels can be concurrently processed by the SIMD processor.

Abstract: An electronic device includes a first CPU, a second CPU, an auxiliary storage unit, and a controller. The auxiliary storage unit includes a first starting program for the first CPU and a second starting program for the second CPU. The first CPU loads the first starting program via the controller, and causes the controller to load the second starting program in DMA transfer. The controller, if the controller is caused by the first CPU to transfer part of the first starting program while the controller is loading the second starting program, stops loading the second starting program. When completing the transfer of the part of the first starting program, the controller restarts loading the second starting program.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.

Abstract: An apparatus comprises a cable including conductors to carry data signals and a power voltage from a device when the cable is connected to the device, and at least one active display assembly fixed along a length of the cable. The active display assembly includes a power converter connected to the conductors to convert the power voltage to a supply voltage, and a programmable display and a controller powered by the power converter. The programmable display is configured to display programmed indicia responsive to the supply voltage, and the controller is configured to program the display.

Abstract: In one embodiment, a method includes storing, in a storage unit, a number of data transfer requests to issue for a data request signal. Data transfer requests are issued to a direct memory access (DMA) controller of a system for transfer of data to a buffer unit. The stored number of data transfer requests is determined. The issuance of data transfer requests are stopped when the stored number of data transfer requests is met.

Abstract: A method and apparatus for inputting and outputting data by using a virtualization technique are provided. The method includes generating a virtual operating system (OS) for the external device, which is connected to a host, based on OS information stored in the external device, setting a partial area of a storage of the host as virtual storage for the external device, and storing the data in the virtual storage or a memory of the external device in response to a request for inputting and outputting the data from the virtual OS.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time.

Abstract: A data processing apparatus comprises a processor having an internal state dependent upon execution of application program code, the processor being configured to generate display data relating to images to be displayed and to buffer display data relating to a most recent period of execution of a currently executing application. The apparatus includes RAM for storing temporary data relating to a current operational state of program execution. The apparatus also includes a data transfer controller configured to transfer data from the RAM relating to the currently executing application, data relating to a current internal state of the processor and buffered display data to suspend data memory, and to transfer data from the suspend data memory to RAM and to the processor to recreate an execution state of an application at a time the suspend instruction was executed, and to retrieve display data relating to the resumed application.

Abstract: It is provided a storage system for inputting and outputting data in accordance with a request from a host computer, comprising: at least one processor for processing data requested to be input or output; a plurality of transfer controllers for transferring data between memories in the storage system; and at least one transfer sequencer for requesting a data transfer to the plurality of transfer controllers in accordance with an instruction from the processor. The processor transmits a series of data transfer requests to the at least one transfer sequencer. The at least one transfer sequencer requests a data transfer to each of the plurality of transfer controllers based on the series of data transfer requests. The each transfer controller transfers data between the memories in accordance with an instruction from the at least one transfer sequencer.

Abstract: Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations.

Abstract: A data processing device includes a memory, a direct memory access controller including a receiving module configured to receive data coming from outside the device and for writing the data in a main buffer memory of the memory, and a processing unit programmed to read and process data written by the receiving module in a work area of the main buffer memory. The main buffer memory is divided between a used space, where the receiving module is configured not to write, and free space, where the receiving module is configured to write. The processing unit is further programmed to define the work area, and the direct memory access controller includes a buffer memory manager configured to free data written in the main buffer memory, by defining a location of this data as a free space, only when this data is outside the work area.

Abstract: A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the particular field of the data stream and (ii) the length parameter of the first list.

Abstract: A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer.

Abstract: The disclosed embodiments relate to a system for controlling accesses to one or more memory devices. This system includes one or more write queues configured to store entries for write requests, wherein a given entry for a write request includes an address and write data to be written to the address. The system also includes a search mechanism configured to receive a read request which includes an address, and to search the one or more write queues for an entry with a matching address. If a matching address is found in an entry in a write queue, the search mechanism is configured to retrieve the write data from the entry and to cancel the associated write request, whereby the read request can be satisfied without accessing the one or more memory devices.