Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

Abstract: A network device may include an off-chip memory to store a free-list of buffer pointers. The network device may further include an on-chip controller that includes a prefetch buffer. The prefetch buffer may store unallocated buffer pointers that point to available memory locations in a different off-chip memory. The on-chip controller may receive an unallocated buffer pointer, determine, in response to receiving the unallocated buffer pointer, whether the prefetch buffer is full, store the unallocated buffer pointer in the prefetch buffer when the prefetch buffer is determined not to be full, and store the unallocated buffer pointer in the free-list, in the off-chip memory, when the prefetch buffer is determined to be full.

Abstract: Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.

Abstract: A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be tra

Abstract: In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized.

Abstract: A local RDMA (Remote Direct Memory Access) network adapter that comprises a simplex switchless connection with a counterpart QP on a remote RDMA network adapter in an example is selected for a Queue Pair (QP). An apparatus in an example comprises a requester RDMA (Remote Direct Memory Access) session fail-over coordinator on a coherency domain that adds a session fail-over header to a front of a data payload sent by an RDMA computer program from the coherency domain. Upon termination, of an RDMA adapter not coherent with the coherency domain and in a communication path of the data payload, before delivery to the RDMA computer program of a receive completion notification for the data payload, the session fail-over header is employable by a responder RDMA session fail-over coordinator to reconstruct the receive completion notification.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank.

Abstract: A method for communicating between a computer and a data storage device comprises receiving, by a data storage device, information indicative of a plurality of commands and information indicative of a memory location in a computer associated with each of the plurality of commands. The method further comprises executing, by the data storage device, one of the plurality of commands. In one embodiment, executing the command comprises directly accessing the computer memory location associated with the command.

Abstract: An apparatus (such as a printer) including a combination engine controller circuit board having a integrated circuit (IC) chip configured to process (format) incoming data as well as to control the operations of the apparatus is disclosed. The IC chip is adapted to receive and process data as well as to control the operations of the apparatus. For this reason, the IC chip is referred to as a combined controller IC.

Abstract: A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and arbitrarily sized fragment (segment) based memory management schemes. This is different from modern CPU implementations with MMUs that support page-based implementations. A primary application of embodiments of the present invention is in DMA applications. The system enables frequent switching of contexts between I/Os using a novel caching technique. An embodiment of the present invention also includes the modification of the conventional scatter-gather element used in DMA for supporting multiple memory spaces, backward list traversals, better error recovery and debugging.

Abstract: A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H?, thereafter generating Q? and R? subject to the same constraints as was described for Q and R. Transformed variables Z and Z? are formed by multiplying Y by QH and Q?H, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and also including a distance metric.

Abstract: Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section.

Abstract: In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information.

Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device.

Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.

Abstract: The invention provides an architecture and method for implementing a programmable I/O interface. The primary function provides a generic reconfigurable interface for serial communications between a laser printer controller and the print mechanism. The design also supports vertical page synchronization (top of page detection).

Abstract: A DMA control system includes: a plurality of DMA control units that are controlled in a manner that, while one of the plurality of DMA control units use a transmission path, the other DMA control units other than the one of the plurality of DMA control unit are prevented from using the transmission path; and a transfer instruction unit that defines transfer amounts of DMA transfers for the respective DMA control units and gives transfer instructions thereto. The transfer instruction unit, when the transfer instruction unit gives a transfer instruction to a first DMA control unit of the plurality of the DMA control units, defines a transfer amount for the first DMA control unit and gives the transfer instruction thereto in accordance with a state of utilizing a second DMA control units of the plurality of the DMA control units.

Abstract: In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer construct is made accessible to one or more direct memory access (DMA) operations. Upon completion of the one or more DMA operations, the buffer construct transitions from the closed state to the open state. The region of memory represented by the buffer construct is made accessible for use with one or more cache operations when the buffer construct is in the open state, so that the one or more cache operations are not in conflict with the one or more DMA operations.

Abstract: In an AV-data transfer system, AV data stored in a RAID embedded in an AV server is supplied to a client personal computer connected to a network such as the Internet or an intranet by way of the network, and AV data output by the client personal computer is transmitted to the AV server through the network to be stored in the RAID. The AV server makes accesses to the RAID to write and read out data into and from the RAID. In addition to the AV server, the AV-data transfer system also includes another personal computer for exchanging AV data with the client personal computer and receiving a variety of commands from the client personal computer by way of the network in accordance with an FTP (File Transfer Protocol). As a result, it is possible to fast handle access requests made by a larger number of client personal computers.

Abstract: In a data processing system having multiple input/output adapters, a DMA memory block is assigned to each adapter. The DMA memory block has a data area and a generic common control area. All adapters have the same translation control entry for the control area. The control area includes a mapped page assigned to each adapter request and an unmapped buffer space interposed between the mapped pages. By mapping the generic DMA memory, memory space which is not required by an adapter is not mapped unnecessarily. Because the generic DMA memory space is part of each adapter's DMA memory space, adapters are unable to write to partitions to which they do not belong and the possibility of cross-partition memory writes is reduced. Moreover, runaway writes to dedicated DMA memory space may be caught as soon as they occur.

Abstract: Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Abstract: There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address into a physical address. The address conversion table stores the effective address to which an area in a memory of a processor unit 10 is allocated to each peripheral device 30 and identification information of an access source to which access permission is given, in association with each other. When the peripheral device 30 accesses, the address converter 14 determines to permit access to the effective address under the condition that the device identification information, included in an access request packet, by which the peripheral device 30 can be uniquely identified, matches the identification information of the access source corresponding to the effective address, in the address conversion table, designated by the access request packet.

Abstract: Methods and apparatus provide for: entering a secure mode in which a given processor may initiate a transfer of information into or out of said processor, but no external device may initiate a transfer of information into or out of said processor; and programming at least one trusted data storage location using a direct memory access (DMA) command to be one of read-only, write-only, readable and writeable, limited access, and reset, where said at least one trusted data storage location is located external to said processor.

Abstract: A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.

Abstract: A system for enforcing a storage allocation usage right(s) for an application may include a controllable storage and a storage manager to control the access of the application to the storage according to an associated storage allocation usage right. A SIM card for enforcing a storage allocation usage right for an application may include an application register to store an access rule of the storage allocation usage right(s) and an APREC module to identify the application and thereby an access rule to enable controlling of the access of the application to storage according to the storage allocation usage right. A high-capacity SIM card for enforcing a storage allocation usage right for an application may include a storage; a storage manager to control the access of an application to the storage according to an associated access rule of the storage allocation usage right; and an APREC module.

Abstract: A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors.

Abstract: A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

Abstract: A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.

Abstract: Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.

Abstract: Method and devices for discovering, maintaining and updating network views of a multi display network supporting CEC. Some embodiments include determining CEC logical addresses of HDMI-CEC devices coupled to HDMI-CEC ports using selective CEC message generation and handling. Other embodiments eliminate an HDMI-CEC device from selected cluster trees upon identifying TMDS communication.

Abstract: Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: In a first embodiment of the present invention, a method for operating an I/O interconnect midpoint device is presented, wherein the midpoint device has a direct memory access (DMA) controller and a plurality of ports, the method comprising: generating, using the DMA controller, a DMA read request; sending, using the DMA controller, the DMA read request to a first device connected to a first of the plurality of ports; receiving data responsive to the DMA read request from the first device; generating, using the DMA controller, a DMA write request including the received data; and sending, using the DMA controller, the DMA write request to a second device connected to the second of the plurality of ports.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the transmit circuit 10 includes a flag generation circuit 11 and an encoding circuit 12. The flag generation circuit 11 generates a flag indicating whether bit inversion has occurred in consecutive bits in each of the bit sequences to be transferred through the buses and transmits the generated flag to the receive unit 20. The encoding circuit 12 encodes the bit sequences based on the flag, for transmission to the receive unit 20. The receive unit includes a decoding circuit 21 that decodes the bit sequences based on the bit sequences and the flag.

Abstract: To improve throughput in data transfer in a remote I/O system, this invention provides a computer system including: a host computer; a device which communicates with the host computer; and a network which connects the host computer and the device, in which the device is coupled to the network via a device bridge including a bridge memory, and the host computer includes a host memory and a device driver. The device driver writes, when at least one of data and an address is written in the host memory, in the bridge memory the at least one of the data and address stored through the writing in the host memory; and sends a data transfer request to the device bridge, and the device bridge reads, upon reception of the data transfer request, an address from a predetermined area; and reads data from an area that is indicated by the read address.

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop bus. The multi-drop bus includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays.

Abstract: A storage system includes a host computer coupled to a device to transfer a DMA descriptor between the host and the device. An integrity manager manages the integrity of the DMA descriptor between the host computer and the device. The integrity manager embeds a host-side DMA descriptor integrity value in the DMA descriptor and the device transfers the DMA descriptor to a device memory. The device generates a device-side DMA descriptor integrity value and compares it to the host-side DMA descriptor integrity value to determine if the descriptor is corrupted.

Abstract: A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a first buffer starting address identifying a starting location of a first buffer allocated in memory for the DMA transfer and to generate a first buffer offset address by applying the first offset to the first buffer starting address. The data transfer unit may be further configured to use the first buffer offset address as a starting location in the first buffer for data transferred in the DMA transfer. By applying various offsets, such DMA devices may spread memory access workload across multiple memory controllers, thereby achieving better workload balance and performance in the memory system.

Abstract: A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability. A storage system includes an interface unit having an interface with a server or hard drives, a memory unit, a processor unit, and an interconnection.

Abstract: A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a memory access request requires multiple data bursts on the memory bus, the SDRAM controller stores the data from the multiple data bursts in respective buffers. Data is then retrieved from the buffers such that data is read from a part of the first buffer, then from the other buffers, and finally from the remaining part of the first buffer. Storing the required data in the remaining part of the first buffer avoids the need to occupy the memory bus with a new data burst.

Abstract: Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.