Hierarchical Or Multilevel Arbitrating Patents (Class 710/243)
  • Patent number: 9760507
    Abstract: A data processing device includes a first sub-arbiter configured to arbitrate an access by first and second masters that access data stored in a memory; a second sub-arbiter configured to arbitrate an access to the memory by a plurality of masters other than the first and the second masters; a main arbiter configured to prioritize the access to the memory by the first sub-arbiter over the access to the memory by the second sub-arbiter; and a limiting unit configured to limit an amount of the access to the memory by the second master within a preset range.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 12, 2017
    Assignee: RICOH COMPANY, LIMITED
    Inventor: Yoshikazu Gyobu
  • Patent number: 9501553
    Abstract: An organization categorization system and method is disclosed. The organization categorization system and method relies on server data to discover which business organizations are consuming the finite resources of the server and in what proportions. Organizations are categorized according to their consumption of resources. The categorization system and method further ascribes a relative business value to each organization to facilitate the allocation of resources among the various organizations in a business. In an example embodiment, users of the server resources use the SAS programming language and the server resources execute SAS applications that support the SAS programming language. The organization categorization system and method connects an executed computer program to a business-defined classification of applicability to purpose.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 22, 2016
    Assignee: Humana Inc.
    Inventors: Andrew B. Hollister, Elizabeth Barth-Thacker
  • Patent number: 9208108
    Abstract: A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: December 8, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Dmitry Vyshetsky, Howard Tsai, Paul Gyugyi
  • Patent number: 9135193
    Abstract: In one example in accordance with aspects of the present disclosure, an expander is provided. The expander comprises a workload scheduling module to cause the expander to enter a first mode of operation where the expander processes interrupts, and further to enter a second mode of operation where the expander processes interrupts for up to a predetermined time period before responding to at least one of Serial Management Protocol (SMP) commands and Serial SCSI Protocol (SSP) commands with a retry message.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: September 15, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael G. Myrah, Balaji Natrajan, Rodrigo Stoll Martins Machado
  • Patent number: 8965947
    Abstract: A control and communication system including a number of automation units which are adapted to process signals in function plans within the automation unit and which are connected in the same level to a common communication bus for providing a peer-to-peer communication between the automation units, further includes an engineering unit being connected to the communication bus and being adapted to provide functions allowing at least one automation unit to exchange signals to a function plan which is attributed to another automation unit.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: February 24, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andreas Drebinger, Jochen Zingraf
  • Patent number: 8793421
    Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 29, 2014
    Assignee: Apple Inc.
    Inventors: William V. Miller, Chameera R. Fernando
  • Patent number: 8769176
    Abstract: A system including a first communication module to transmit or receive data via an antenna in accordance with a first communication standard; a second communication module to transmit or receive data via the antenna in accordance with a second communication standard; and an arbitration module. The arbitration module outputs a first mutual grant where both the first communication module and the second communication module are able to simultaneously transmit data via the antenna; a second mutual grant where both the first communication module and the second communication module are able to simultaneously receive data via the antenna; a third mutual grant where the first communication module and the second communication module are able to simultaneously transmit and receive data, respectively, via the antenna; and a fourth mutual grant where the first communication module and the second communication module are able to simultaneously receive and transmit data, respectively, via the antenna.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Marvell International Ltd.
    Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung
  • Patent number: 8732369
    Abstract: An apparatus including a first register, a second register, and a control logic. The first register may be configured to store requests from a plurality of clients for a current cycle. The second register may be configured to store an indicator value indicating which of the plurality of clients received a grant in a previous cycle. The control logic may be configured to determine which of the plurality of clients having a request in the current cycle receives a grant based upon (i) a pointer value and (ii) the indicator value.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 20, 2014
    Assignee: Ambarella, Inc.
    Inventor: Chishein Ju
  • Patent number: 8732370
    Abstract: An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Timothy D Anderson, Amitabh Menon
  • Patent number: 8688881
    Abstract: An integrated circuit device (100) comprising a first plurality of components (102-112), a second plurality of buses (114-124, 140, 142) for transmitting transaction requests from said components (102-112) to a resource (138) shared by said components (102-112) and a third plurality of arbiters (132-136) arranged in at least two levels of arbitration. Each transaction request has attached priority value that is used by the arbiters to determine which of the components should be granted access to the resource (138).
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: April 1, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Rowan Nigel Naylor
  • Patent number: 8667199
    Abstract: A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 4, 2014
    Assignee: ARM Limited
    Inventors: David John Gwilt, Graeme Leslie Ingram
  • Patent number: 8645639
    Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 4, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Guhan Krishnan, Antonio Asaro, Don Cherepacha, Thomas R. Kunjan, Joerg Winkler, Ralf Flemming, Maurice B. Steinman, Jonathan Owen, John Kalamatianos
  • Patent number: 8619554
    Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: December 31, 2013
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Robin Hotchkiss
  • Patent number: 8612990
    Abstract: A storage system may include a set of storage devices; a controller; and a management device. The controller may arbitrate among operations for execution by the set of storage devices, where the operations are received from users that are associated with priority levels. The controller may maintain queues, corresponding to the users, to queue operations from the users. The controller may additionally include a scoring component and a scheduler. The scoring component may maintain a score for each queue. The scheduler may choose, from the queues and based on the score of each queue, one of the operations to service. The management device may receive usage updates, from the controller, reflecting usage of the set of storage devices; calculate a maximum allowed usage levels, based on the received usage updates, for each user; and transmit the calculated maximum usage levels to the controller.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 17, 2013
    Assignee: Google Inc.
    Inventors: Lawrence E. Greenfield, Alexander Khesin
  • Patent number: 8601192
    Abstract: Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: December 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Morimoto, Yoshiharu Watanabe, Takashi Yamada, Takashi Hashimoto, Koji Asai
  • Patent number: 8504750
    Abstract: Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plural functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 6, 2013
    Assignee: QLOGIC, Corporation
    Inventors: Bradley S. Sonksen, Richard S. Moore
  • Patent number: 8499299
    Abstract: Techniques for ensuring deterministic thread context switching in a virtual machine application program include, in one embodiment, providing a single application-level mutex that threads of the executing application program are forced to acquire to execute application code of the virtual machine application program. During a first recorded execution of the virtual machine application program, a record is created and stored in a computer that indicates the order in which threads acquire the application-level mutex.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: July 30, 2013
    Assignee: CA, Inc.
    Inventors: Arpad Jakab, Humberto Yeverino, Suman Cherukuri, Jeffrey Daudel, Jonathan Lindo
  • Patent number: 8484397
    Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: July 9, 2013
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Drew E. Wingard
  • Patent number: 8447905
    Abstract: An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Diana Lynn Orf, Robert J. Sonnelitter, III
  • Patent number: 8438512
    Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 7, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Cross, Eric Nequist
  • Patent number: 8321872
    Abstract: Hardware resources sharing for a computer system running software tasks. A controller stores records including a mutex ID tag and a waiter flag in a cache. Lock and unlock registers are readable by the controller and loadable by the tasks with a mutex ID specifying a hardware resource. The controller monitors whether the lock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it sets the record's waiter flag. If not, it adds a record having a tag corresponding with the mutex ID. The controller also monitors whether the unlock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it determines whether that record's waiter flag is set and, if so, it clears that record from the cache.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 27, 2012
    Assignee: Nvidia Corporation
    Inventor: James R. Terrell, II
  • Patent number: 8274972
    Abstract: A communication system is provided, including a first master device to operate as a master of a communication according to a first protocol, a second master device to operate as a master of a communication according to a second protocol, a common slave device to operate as a slave of the communication according to the first protocol and the second protocol with respect to the first master device and the second master device, and a switch to control a connection between the common slave device and the first master device and between the common slave device and the second master device for a communication between the common slave device and one of the first master device to and the second master device. Thus, embodiments of the present invention provide a communication system that minimizes cost increases and improves communication speed in a system in which a plurality of master devices communicate with a slave device performing the same function as the master devices.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong-kee Park
  • Patent number: 8270316
    Abstract: An on-chip Radio Frequency (RF) Interconnect (RF-I) for communication between internal circuit nodes of an integrated circuit is provided. In one embodiment, an integrated circuit is provided that includes an on-chip transmission line, a first circuit node associated with an RF transmitter connected to the transmission line, and a second circuit node associated with an RF receiver connected to the transmission line. In order to transmit data from the first circuit node to the second circuit node, the RF transmitter associated with the first circuit node modulates the data onto an RF carrier frequency to provide a modulated RF signal and transmits the modulated RF signal over the transmission line. The RF receiver associated with the second circuit node receives the modulated RF signal from the transmission line and demodulates the modulated RF signal to recover the data for the second circuit node.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 18, 2012
    Assignee: The Regents of the University of California
    Inventors: Mau-Chung F. Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam, Chunyue Liu
  • Patent number: 8266389
    Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 11, 2012
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guhan Krishnan, Antonio Asaro, Don Cherepacha, Thomas R. Kunjan, Joerg Winkler, Ralf Flemming, Maurice B. Steinman, Jonathan Owen, John Kalamatianos
  • Patent number: 8260993
    Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 4, 2012
    Assignee: Thomson Licensing
    Inventors: Shuyou Chen, Thomas Edward Horlander
  • Patent number: 8244944
    Abstract: A wireless network device including an antenna, a first communication module, and a second communication module. The first communication module is configured to transmit or receive packets of data in accordance with a first communication standard, and the second communication module is configured to transmit or receive packets of data in accordance with a second communication standard. The wireless network device further includes an arbitration module configured to grant access of each of the first communication module and the second communication module to the antenna so that the first communication module and the second communication module can respectively transmit or receive data packets in accordance with the first communication protocol and the second communication protocol.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: August 14, 2012
    Assignee: Marvell International Ltd.
    Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung
  • Patent number: 8238911
    Abstract: Methods, apparatus, and computer-readable media for management and arbitration of dedicated mobile communication resources for mobile applications are provided. Mobile applications can be given a priority level that establishes an importance with respect to one or more other mobile applications and at least one mobile resource. If competing applications attempt to access the mobile resource concurrently, access can be provided to an application having higher priority level. Furthermore, control of a resource can be taken away from an application having lower priority in order to affect control of such resource for a higher priority application. In one aspect, a privilege code of an application can be verified prior to establishing control of the resource for the application, to mitigate a likelihood of inappropriate transfer of resources.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: August 7, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Tianyu Li D'Amore, Uppinder Singh Babbar, David C. Park, Srinivasan Balasubramanian
  • Patent number: 8209689
    Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Patent number: 8200874
    Abstract: A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: June 12, 2012
    Assignee: Xilinx, Inc.
    Inventors: Wayne E. Wennekamp, Adam Elkins, Schuyler E. Shimanek, Thomas H. Strader, Steven E. McNeil
  • Patent number: 8190804
    Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: May 29, 2012
    Assignee: Sonics, Inc.
    Inventors: Krishnan Srinivasan, Drew E. Wingard
  • Patent number: 8180941
    Abstract: Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wen-Tzer T. Chen, Charles R. Johns, Ram Raghavan, Andrew H. Wottreng
  • Patent number: 8156273
    Abstract: A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: April 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christine E. Moran, Matthew D. Akers, Annette Pagan
  • Patent number: 8140729
    Abstract: A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: March 20, 2012
    Assignee: Apple Inc.
    Inventor: Michael D. Johas Teener
  • Patent number: 8140728
    Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: March 20, 2012
    Assignee: EMC Corporation
    Inventor: Almir Davis
  • Patent number: 8117616
    Abstract: A deadlock prevention mode indicator is provided, wherein the deadlock prevention mode indicator is a lock that can be held in a shared mode or in an exclusive mode by one or more of a plurality of threads, and wherein the plurality of threads can cause deadlocks while acquiring a plurality of data locks. An execution of the plurality of threads is serialized by allowing a data lock to be acquired by a thread in response to the thread holding the deadlock prevention mode indicator, wherein serializing the plurality of threads avoids any deadlock from occurring.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventor: Russell Lee Lewis
  • Patent number: 8099539
    Abstract: A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: January 17, 2012
    Assignee: LSI Corporation
    Inventors: Rajendra Sadanand Marulkar, Gurvinder Pal Singh
  • Patent number: 8024810
    Abstract: A method and an apparatus ensuring protection of digital data are provided. In addition to re-encrypting the data using an unchangeable key, the data is double re-encrypted using a changeable key. The changeable key is used first and the unchangeable key is then used, or in another case, the unchangeable key is used first, and the changeable key is then used. In the aspect of embodiments, there is a case adopting a software, a case adopting a hardware, or a case adopting the software and the hardware in combination. The hardware using the unchangeable key developed for digital video is available. In adopting the software, encryption/decryption is performed in a region below the kernel which cannot be handled by the user to ensure the security for the program and for the key used. More concretely, encryption/decryption is performed with RTOS using a HAL and a device driver, i.e., a filter driver, a disk driver and a network driver, in an I/O manager.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: September 20, 2011
    Assignee: Intarsia Software LLC
    Inventor: Makoto Saito
  • Patent number: 7996583
    Abstract: Various embodiments provide methods and systems operable to receive a work queue pair from one of a plurality of host nodes, to scan the work queue pair for known data formats corresponding to one of a plurality of transport protocols, to optionally convert the work queue pair to produce a standard work queue pair data format, to add the work queue pair to a scheduler queue for a virtual host channel adapter (HCA) scheduler, and to update a context associated with the work queue pair.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: August 9, 2011
    Assignee: Cisco Technology, Inc.
    Inventor: Keith Iain Wilkinson
  • Patent number: 7979615
    Abstract: An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator is defined to consider a different portion of the multiple requestors when selecting a requestor to be serviced by the master to which the arbitrator is assigned. Each arbitrator is further defined to select a requestor from the different portion of the multiple requestors, such that selection of a particular requestor is not duplicated among the plurality of arbitrators. Additionally, requestor selection by each of the plurality of arbitrators is performed in a same clock cycle.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: July 12, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventor: Marc Spitzer
  • Patent number: 7975086
    Abstract: A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined to select a different one of the multiple requestors to be serviced by the master to which the arbitrator is assigned. Also, the plurality of arbitrators is defined to make their requestor selections in the same clock cycle. Additionally, the plurality of arbitrators is defined to make their requestor selections such that selection of a particular requestor is not duplicated among the plurality of arbitrators.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: July 5, 2011
    Assignee: PMC-Sierra US, Inc.
    Inventor: Marc Spitzer
  • Patent number: 7949812
    Abstract: A wireless network device includes a first communication module to communicate with at least one of first devices and a second communication module to communicate with at least one of second devices. An arbitration module receives a request for communication from the first communication module, detects when the second communication module is communicating in a locked mode, and denies request for communication from the first communication module when the second communication module is communicating in the locked mode. Transmission or reception of a packet in the locked mode is not interrupted to avoid loss of the packet. The arbitration module grants the request for communication from the first communication module when the second communication module is communicating in the locked mode and when granting the request for communication from the first communication module does not require stopping the second communication module from communicating in the locked mode.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: May 24, 2011
    Assignee: Marvell International Ltd.
    Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung
  • Patent number: 7950014
    Abstract: Aspects of the subject matter described herein relate to detecting the ready state of a user interface element. In aspects, a synchronization object is created to indicate when a user interface element is ready. Data is then loaded into the user interface element. After the data is loaded, an indication is made via the synchronization object that the user interface element is ready. After this occurs, a thread waiting on the synchronization object may interact with the user interface element with confidence that the user interface element is ready.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 24, 2011
    Assignee: Microsoft Corporation
    Inventor: Ronald R. Martinsen
  • Patent number: 7930456
    Abstract: A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data transfers are routed through the system based on arbitration logic that prioritizes by function in a primary arbitration stage and by client in a subsequent arbitration stage.
    Type: Grant
    Filed: December 23, 2006
    Date of Patent: April 19, 2011
    Assignee: EMC Corporation
    Inventor: Almir Davis
  • Patent number: 7917908
    Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr., Wesley Erich Queen, Michael Steven Siegel
  • Patent number: 7865914
    Abstract: Loading and unloading a plurality of libraries on a computing device having a loader lock and internal and external counts for each library in the plurality of libraries is disclosed. The libraries assume an initialize state, followed by an initialized state, a pending unload state, and an unload state according to when the internal and external counts are incremented and decremented. When in the pending unload state, the functions of a library that include functions that require acquiring the loader lock exit, the internal count is decremented by one, and the loader lock is released. Prior to entering the pending unload state, a library may be placed into a reloadable state. A library in the reloadable state may be reloaded upon request until a timer times out. When the timer times out, the library in the reloadable state transitions into the pending unload state.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 4, 2011
    Assignee: Microsoft Corporation
    Inventors: Kenneth M. Jung, Arun Kishan, Neill M. Clift, Dragos C. Sambotin
  • Patent number: 7865633
    Abstract: Various embodiments provide methods and systems operable to receive a work queue pair from the host application, to add the work queue pair to a scheduler queue for a virtual HCA scheduler, to update a context associated with the work queue pair, to create at least one data packet corresponding to the work queue pair, and to send the at least one data packet to at least one of a plurality of target nodes via at least one of a plurality of data channel ports.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: January 4, 2011
    Assignee: Cisco Technology, Inc.
    Inventor: Keith Iain Wilkinson
  • Patent number: 7836235
    Abstract: An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: November 16, 2010
    Assignee: Panasonic Corpoation
    Inventors: Yoshiharu Watanabe, Seiji Horii, Daisuke Murakami, Yuji Takai
  • Patent number: 7802041
    Abstract: According to an aspect of an embodiment, an apparatus has a pair of first system boards, each of the first system boards including a processor and being adapted for sending duplicate requests, in parallel, respectively, a second system board including a processor and being adapted for sending requests, a first transfer device for transferring requests, having a first arbiter for selecting and outputting one of the duplicate requests sent from each of the first system boards, and a second arbiter for selecting and outputting one of the requests sent from the second system board and a second transfer device for transferring requests, having a third arbiter for selecting one of the duplicate requests sent from each of the first system boards and outputting the selected request in synchronization with the selected request outputted by the first arbiter, the second transfer device having a forth arbiter.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Limited
    Inventors: Takayuki Kinoshita, Junji Ichimiya
  • Patent number: 7797468
    Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: September 14, 2010
    Assignee: Hewlett-Packard Development Company
    Inventors: George Shin, Rajiv K. Grover, Santosh Ananth Rao
  • Patent number: 7797476
    Abstract: The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using switched resources in the form of configurable crossbar switches.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: September 14, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Ajit Deepak Gupte, Gregory R. Shurtz