Abstract: The invention relates to a signal processing apparatus comprising plural memories in an LSI and plural memory access blocks for accessing these memories, in which the cause can be analyzed easily in the event of a fault. The signal processing apparatus 100 comprises a first arbitration block 150 for arbitrating the access right of a third memory access block 130 to a first built-in memory 160, a second arbitration block 180 for arbitrating to store the memory access history of the third memory access block 130 in a second built-in memory 190 which is not the same memory as the first built-in memory 160 executing the access of the third memory access block 130, and a trace control block 170 for controlling.

Abstract: A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a “None_odd” message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a “None_even” message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.

Abstract: A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than the others and including a peripheral device. Each master may request control of the shared bus and is adapted to perform short transfers and long burst transfers on the shared bus between a resource and the master. A shared bus arbiter is utilized for dynamically determining the highest priority request between a number of shared bus requests, and granting control of the shared bus to the highest priority requesting bus master.

Abstract: The present invention provides a multiple bus control device and others which can also be applied to access control by a signal having a directional propagation property for implementing various communication between/among modules. Each of plural modules makes a request for communication to a multiple bus control device by sending communication request information for specifying one or more communication partner modules to the multiple bus control device. The multiple bus control device checks an idle state of a module to be communicated and an idle channel in a multiple bus based upon received communication request information and permits communication between a module which sends communication request information using the idle channel and a communication partner module specified in the communication request information.

Abstract: A signal processing apparatus in which an LSI includes a memory and a plurality of blocks for making access to the memory is provided with a trace control block 170 for tracing in a specific region of the memory the history of access by a required memory access block based on a setting by a microcomputer 110 so as to allow easy analysis of the cause in the event a trouble. Also, a quasi mediation block 180 is provided in a mediation block 150, which accepts a memory use request signal from other memory access block while tracing of access history is being performed and sends back a memory use approval signal without actually making access to an internal memory 160. In the event of a trouble, an analysis of the cause can be easily made by reading a specific tracing region of the internal memory 160 out from outside.

Abstract: A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A method and system for priority arbitration in a computer environment having a shared resource capable of servicing a plurality of devices. In one embodiment, the present invention assigns an initial priority order to the plurality of devices such that those devices have priorities which are distinct. The present invention then identifies those of the plurality of devices which have issued service requests to the shared resource in a first clock cycle as requesting devices. Provided that there are more than one requesting device in the first clock cycle, the present invention selects one of the requesting devices to be serviced by the shared resource in a second clock cycle following the first clock cycle, where the selected device has the highest of the priorities among the requesting devices based on the initial priority order. The present invention also reassigns the priorities among the plurality of devices such that the selected device is assigned the lowest one of the priorities.

Abstract: A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater contains a first arbiter that arbitrates transactions between the first repeater and the second repeater and also arbitrates transactions between the first repeater and the third repeater. The second repeater receives transactions from the first repeater and contains a second arbiter that predicts receipt of transactions from the first repeater to the second repeater.

Abstract: A method of synchronizing arbiters. The method is performed by a computer system that has a first repeater, a second repeater that is coupled to the first repeater, and a third repeater that is coupled to the first repeater. The method includes: instructing the second repeater to cease issuing transactions to the first repeater; synchronizing an arbiter within the second repeater with an arbiter within the third repeater; instructing the second repeater to begin issuing transactions to the first repeater; and instructing the third repeater to begin issuing transactions to the first repeater.

Abstract: An arbitration system and method provides self-arbitration among a plurality of processors or other entities vying for access to the bus or other shared resource. The entities vying for access to the shared resource present their respective priority values to an evaluation medium. The evaluation medium determines the highest priority value of those values presented, and provides this “winning” value to the competing entities. The entities compare the received “winning” value to their respective presented values. If an entity makes a positive comparison, that entity won the arbitration and is granted access to the shared resource.

Abstract: The method of the present invention includes maintaining a first tier 101 and a second tier 102 of devices 30 that have access to a secondary bus 42 that a PCI to PCI bridge 38 services. Each device 30 that has access to secondary PCI bus 42 is categorized into either first tier 101 or a second tier 102. The devices 30 in first tier 101 are provided more frequent opportunities to gain access to secondary PCI bus 42 than devices in low tier 102. Next, a pending transaction is recognized when an initiating device 30 that has been categorized into second tier 102 accesses secondary PCI bus 42 and attempts a transaction that crosses PCI to PCI bridge 38 to primary PCI bus 26. However, PCI to PCI bridge 38 is unable to complete the transaction on primary PCI bus 26. Therefore, PCI to PCI bridge 38 is unable to provide access to any other device 30 on secondary bus 42 until the pending transaction completes.

Abstract: A computer system, method, and controller bus agent for control access to a computer bus. The computer system includes a parallel architecture in which plural bus agents are directly coupled to the computer bus. Each bus agent includes plural bus requester ports each coupled to a different bus requester. As such, the computer system employs a relatively flat, parallel architecture that handles bus requests from the bus requesters in parallel. The controller bus agent includes an internal arbiter and an external arbiter. The internal arbiter arbitrates between bus requests received from the plural bus requesters coupled to the controller bus agent. The external arbiter arbitrates between the bus requests received from other bus agents and from the internal arbiter.

Abstract: A method and mechanism to enforce reduced access via restricted access tokens. Restricted access tokens are based on an existing token, and have less access than that existing token. A process is associated with a restricted token, and when the restricted process attempts to perform an action on a resource, a security mechanism compares the access token information with security information associated with the resource to grant or deny access. Application programs may have restriction information stored in association therewith, such that when launched, a restricted token is created for that application based on the restriction information thereby automatically reducing that application's access. Applications may be divided into different access levels such as privileged and non-privileged portions, thereby automatically restricting the actions a user can perform via that application.

Abstract: The method of the present invention includes maintaining a first tier 101 and a second tier 102 of devices 30 that have access to a secondary bus 42 that a PCI to PCI bridge 38 services. Each device 30 that has access to secondary PCI bus 42 is categorized into either first tier 101 or a second tier 102. The devices 30 in first tier 101 are provided more frequent opportunities to gain access to secondary PCI bus 42 than devices in low tier 102. Next, a pending transaction is recognized when an initiating device 30 that has been categorized into second tier 102 accesses secondary PCI bus 42 and attempts a transaction that crosses PCI to PCI bridge 38 to primary PCI bus 26. However, PCI to PCI bridge 38 is unable to complete the transaction on primary PCI bus 26. Therefore, PCI to PCI bridge 38 is unable to provide access to any other device 30 on secondary bus 42 until the pending transaction completes.

Abstract: A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.

Abstract: A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registers are programmed during boot-up of the computer system by assigning a subset of peripheral devices, bus agents, requesters, or bus masters to either a high priority ring or a low priority ring, if two levels of arbitration are used. The status of a low priority device can be elevated to equal priority with a high priority device by assigning the low priority device to a high priority port within the high priority ring if certain circumstances occur. Namely, if data transfers to or from the low priority device are terminated, then the low priority device will be promoted to a high priority device so that it need not wait until after the all high priority device requests have been polled.

Abstract: A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal.

Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus.

Abstract: A priority decision circuit decides priorities of a plurality of slots on the basis of access frequencies or the like. In conformity with these priorities, a bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to the upper hierarchical bus whereas it performs mapping allowing a slot having a lower priority to be connected to the lower hierarchical bus.

Abstract: A priority encoder circuit (10, 60) is provided. The priority encoder circuit (10, 60) includes a plurality of inputs (38, 90) and outputs (40, 92). The number of inputs (38, 90) equals the number of outputs (40, 92), and each input (38, 90) corresponds to one output. Each input (38, 90) receives a signal that indicates whether the input (38, 90) has been selected. The priority encoder circuit (10, 60) also includes circuitry (50, 100) that generates a signal at the output (40, 92) corresponding to the input (38, 90) having the highest priority that receives the selection signal.

Abstract: Low-latency arbitration is provided for a super-priority communications device such as modems and ISDN/DSL routers, LAN switches and routers. Phantom arbitration slots are inserted between each pair of permanent slots. When a request from the super-priority agent is received, the next phantom slot is used to service the request. The initial latency is just one slot period rather than the whole arbitration loop. Other phantom slots are skipped until the same phantom slot is again activated at the same point in the arbitration loop during subsequent rounds of arbitration. Thus only the initial latency is reduced; subsequent requests from the super-priority agent are handled just once for each arbitration cycle. The low initial latency allows the communications device to quickly respond to an incoming call. Other real-time agents are assigned a fixed slot in a round-robin arbitration. The last arbitration slot is used by all non-real-time agents.

Abstract: A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a plurality of slow data port interfaces configured to transmit data at a first data rate between a slow data port and the buffer memory and a plurality of fast data port interfaces configured to transmit data at a second data rate between a fast data port and the buffer memory. A first level arbiter is coupled to the plurality of slow data port interfaces. The first level arbiter chooses an access request of one the slow data ports and outputs the access request. A second level arbiter is coupled to the plurality of fast data port interfaces and to the output of the first level arbiter. The second level arbiter chooses an access request from among a plurality access requests from the fast data port interfaces and the access request from the first level arbiter, and forwards the chosen access request to the memory.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1)log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: A configurable weighted round robin arbitration mechanism adapted to receive as input a vector of order N, wherein each bit in the vector represents the eligibility of a queue or other source of data to participate in the arbitration process. A bit set to `1` in the vector indicates that the corresponding queue is eligible to participate in the arbitration process. Conversely, a bit set to `0` in the vector indicates that the corresponding queue is not eligible to participate. The arbitration process of the present invention enables a user to assign each queue (which corresponds to one of the bits in the vector) an individual weight. This results in a modified vector that represents the incoming vector after being handled by the weighting process. By giving each bit in the vector a weight, the user can control the probability of each bit, i.e., queue, being selected in the arbitration process.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.

Abstract: The present invention comprises a priority arbitration system for interfacing a plurality of PCI agents coupled to a peripheral component interconnect (PCI) bus such that high priority PCI agents are satisfied without starving low priority PCI agents. The system of the present includes a PCI bus adapted to transmit data signals. At least one high priority PCI agent is coupled to the PCI bus. At least one low priority PCI agent is coupled to the PCI bus. An arbiter is coupled to the high priority PCI agent and the low priority PCI agent via the PCI bus. The arbiter grants ownership of the PCI bus to the high priority PCI agent prior to granting ownership to the low priority PCI agent. After being granted ownership, the high priority PCI agent becomes an interim low priority PCI agent. The low priority PCI agent is accorded a higher priority by the arbiter than the interim low priority PCI agent.

Abstract: The present invention is directed to providing a computer system which arbitrates control of a shared bus among plural devices included in the computer system. In accordance with the present invention, at least one of the devices is afforded a higher priority than the remaining devices, yet none of the remaining devices are effectively denied system bus access or control for extended periods of time. The present invention can therefore increase operating efficiency even as the number of devices included in the computer system is increased to achieve enhanced processing power. In addition, the present invention can provide sophisticated multimedia features, including real time signal processing, without sacrificing overall operating efficiency.