Abstract: A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.

Abstract: A system for a secured communication between a computer and peripheral devices includes a fiber isolator transmitter coupled to a computer and one or more fiber-optic pairs; a fiber isolator receiver coupled to one or more peripheral devices and the one or more fiber-optic pairs; and the one or more fiber-optic pairs configured to transfer optical data signals between the fiber isolator transmitter and the fiber isolator receiver. The fiber isolator transmitter and the fiber isolator receiver are configured so corresponding video data and audio data flows from the computer to a corresponding display device(s) and/or speaker(s), respectively, of the one or more peripheral devices via one optical fiber of a corresponding fiber optic pair of the one or more fiber-optic pairs and USB data flow from the one or more peripheral devices to the corresponding computer via a particular optical fiber of the one or more fiber optic pairs.

Abstract: Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.

Abstract: Various implementations relate to receiving, by a non-volatile memory device from a host, a host command include device context information of non-volatile memory devices. The device context includes an address of a buffer of each non-volatile memory device. In response to receiving the host command, portions of host data are divided among the non-volatile memory devices. The non-volatile memory device sends to the host a transfer request indicating transfer of each portion of the host data to a respective one of the non-volatile memory devices. The non-volatile memory device sends to another non-volatile memory device a peer command based on the device context information.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.

Abstract: In some examples, a wireless card reader detects insertion of a chip card at a chip card reader interface that includes electrical contacts positioned in the wireless card reader to contact contacts of the chip card when inserted into the wireless card reader. The wireless card reader may send, to a mobile computing device, a wireless communication request to send a PIN to the card reader. The card reader may receive, from the mobile computing device, a wireless communication including the PIN entered by a user on the mobile computing device. The card reader may send the PIN for authentication of the PIN. The card reader may receive a confirmation that the PIN has been authenticated. The card reader may send, to the mobile computing device, via the communication component, an indication of the confirmation that the PIN has been authenticated.

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

Abstract: An information handling system includes a service module that may detect an action performed on a passthrough device, invoke an application programming interface on a hypervisor, receive a response to the action on the passthrough device from the hypervisor, and push management information to a management controller. The hypervisor may detect the passthrough device, proxy an operating system call associated with the action to a guest operating system of the virtual machine over the application programming interface, and transmit the response received from the guest operating system to the service module. The guest operating system may echo the operating system call on a virtual machine, and proxy the response to the operating system call to the hypervisor.

Abstract: A virtual machine (VM) has direct access to an I/O device having physical and virtual functions and a mailbox register, and includes a guest driver for controlling the virtual functions. The VM runs on system software that includes a physical driver for controlling the physical function (PF) and maintains VM page tables, which include an entry that references a memory space into which the mailbox register is mapped. The system software registers a callback function with the physical driver, which the physical driver invokes upon receiving a trigger for communication with the guest driver. In response, the system software alters the page tables so that access to the mailbox register causes a PF intercept, and the callback function handles the communication with the guest driver. After completion of the communication, the system software alters the page tables so that access to the mailbox register does not cause a PF intercept.

Abstract: A direct memory access (DMA) engine can be used to multicast data from system memory to a target memory for loading into an array. The DMA engine may include a controller that is configured to receive a data transfer request, and generate a set of write operations for the output interface. The set of write operations can include, for each of multiple partitions of the target memory, a write operation to write usable data from the multicast data to an address offset in the corresponding partition, and an additional write operation to write filler data from the multicast data to a null device address.

Abstract: An information processing apparatus coupled to a storage device via a network includes a processor configured to: acquire a host physical address over a physical storage region in which information regarding an access to the storage device from a guest OS is stored from a first packet stored in the physical storage region storing a packet obtained by encapsulating the information regarding the access; convert the acquired host physical address into a guest physical address recognized by the guest OS; create a data structure of a block device; store the guest physical address in a data address region of the data structure; specify the host physical address corresponding to the guest physical address while referring to the memory when reading from the data address region is detected; read data from the specified host physical address over the physical storage region; and transfer the read data to the guest OS.

Abstract: Techniques for maintaining and synchronizing data is a processing pipeline data between multiple processing units to improve a system latency are described herein. For example, the techniques may include determining, in response to an invocation of vision processing on first vision data stored in a first memory range in a first memory associated with a central processing unit (CPU), that second vision data stored in a second memory range in a second memory associated with a graphic processing unit (GPU) is a modified copy of the first vision data. The second vision data may be obtained using a non-blocking operation from the second memory range. The first vision data stored in the first memory range may be replaced with the second vision data obtained from the second memory range. The vision processing may then be performed using the second vision data stored in the first memory.

Abstract: In some examples, a control device includes a controller to receive, from a requester device that is separate from the control device, a request to access a first memory region of a memory. The controller is to determine, based on occurrence of a systems initialization event and according to permissions information that identifies access permissions for respective memory regions of the memory, whether access of content in the first memory region is allowed.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a DMA command for a plurality of data sectors to be moved from a source memory region to a destination memory region, the source memory region comprises a plurality of noncontiguous memory addresses and the DMA command comprises a source value referencing the plurality of noncontiguous memory addresses. The processing device further retrieves the plurality of noncontiguous memory addresses from a location identified by the source value. The processing device then reads the plurality of data sectors from the plurality of noncontiguous memory addresses. The processing device also writes the plurality of data sectors to the destination memory region.

Abstract: A wide hash key, that exceeds the word size of a GPU memory, is used to perform a key-value mapping by using paired hash tables configured in a multi-level tree configuration. The wide hash key is partitioned into segments, where each segment is used as a key into a respective paired hash table. The paired hash table has one hash table that stores an upper portion of an address and another hash table that stores the lower portion of the address. The upper and lower portions are combined to generate either an address to a paired hash table at the next level in the multi-level tree configuration or the address to the location of the value associated with the wide hash key.

Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

Abstract: A processing device, operatively coupled with a plurality of memory devices, is configured to receive a direct memory access (DMA) command for moving a plurality of data sectors from a source memory region to a destination memory region, the DMA command comprising a priority value. The processing device further assigns the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command, each priority queue has a corresponding set of priority values. The processing device also determines an execution rate for each priority queue of the plurality of priority queues. The processing device then executes a plurality of DMA commands from the plurality of priority queues according to the corresponding execution rate of each priority queue.

Abstract: Devices, methods, and systems for distributed gather and scatter operations in a network of memory nodes. A responding memory node includes a memory; a communications interface having circuitry configured to communicate with at least one other memory node; and a controller. The controller includes circuitry configured to receive a request message from a requesting node via the communications interface. The request message indicates a gather or scatter operation, and instructs the responding node to retrieve data elements from a source memory data structure and store the data elements to a destination memory data structure. The controller further includes circuitry configured to transmit a response message to the requesting node via the communications interface. The response message indicates that the data elements have been stored into the destination memory data structure.

Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes a graphics subsystem including one or more of a first logic for processing of memory read-return data for single-instruction-multiple-data instructions; a second logic for assembly of memory read-return data for media block instructions into shader register format; or a third logic to remap scatter or gather instructions to untyped surface instruction types. An embodiment of an apparatus includes a graphics subsystem including a translation lookaside buffer (TLB) and a data port controller to control the TLB, the data port controller including an incoming request pipeline to receive an incoming request with virtual address and generate a response, an incoming response pipeline to receive the response and generate a cache request, and an invalidation flow pipeline.

Abstract: A method, an apparatus, and a system for accessing a storage device. The method includes: acquiring, by an I/O adapter, an access request from a virtual machine, where the access request carries virtual address information of a to-be-accessed storage area; generating an access instruction according to the access request, where the access instruction carries the virtual address information and an identifier of a virtual channel of the virtual machine, where the virtual channel corresponds to the virtual machine on a one-to-one basis and is used to connect the corresponding virtual machine to a storage device target, and the storage device target is configured to manage access to the storage device; and sending the access instruction to the storage device target.

Abstract: In various embodiments, an organization may be required to comply with one or more legal or industry requirements related to the storage of personal data (e.g., which may, for example, include personally identifiable information) even when responding to and fulfilling Data Subject Access Requests. In particular, when responding to a DSAR, the system may compile one or more pieces of personal data for provision to a data subject. The system may store this compilation of personal data at least temporarily in order to provide access to the data to the data subject. As such, the system may be configured to implement one or more data retention rules in order to ensure compliance with any legal or industry requirements related to the temporary storage of the collected data while still fulfilling any requirements related to providing the data to data subjects that request it, deleting the data upon request, etc.

Abstract: According to one embodiment, a memory device includes a memory and a controller circuit. The memory holds first data and second data. The first data and the second data are results of monitoring state of the memory device. The first data and the second data include values indicating results of monitoring attributes common between these data. The values are updated according to operation status of the memory device. The controller circuit switches an object to be read from the memory between the first data and the second data.

Abstract: Window based mapping is used to reduce the usage of volatile memory for storing the mapping of logical to physical addresses for accesses to data in a flash drive. Two separate mapping tables for translation of logical addresses to physical addresses (L2P), e.g., an L2P front map and an L2P back map, are used where the L2P front map acts as a window to the L2P back map. The L2P front map has smaller granularity for data accesses than the L2P back map. The data accessed using the L2P front map can allow the flash drive to function with relatively same performance as a fully mapped drive with a single mapping table.

Abstract: A system and method for safe physical function passthrough using virtual machine functions includes sending, by a guest on a virtual machine, an access request for a host device to a virtual machine function on the virtual machine. The method also includes determining, by the virtual machine function, whether the access request is valid responsive to receiving the access request. Responsive to determining that the access request is valid, the virtual machine function sends the access request to a virtual device on the virtual machine. The method further includes preventing, by a hypervisor executing on one or more processors, the guest from accessing the virtual device when not executing the virtual machine function.

Abstract: A data transferring device and a data transfer method. The data transferring device for transferring an audio-visual stream stored in a first medium to a second medium, includes: a reader comprising reading circuitry configured to read the audio-visual stream from the first medium; and a controller configured to: extract an audio packet and a video packet from the audio-visual stream; write the audio packet and video packet to the second medium; and store, in a memory, first location information indicating locations at which the audio packet and the video packet are written in the second medium, and second location information indicating locations at which the audio packet and the video packet are read from the first medium.

Abstract: A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Abstract: Systems and methods for redundant write transfer detection are described. In one embodiment, the systems and methods may include identifying a starting logical block address (LBA) associated with a request to write a first data set to the storage device, storing the first data set on a storage medium of the storage device, storing the identified starting LBA of the first data set in a memory associated with the storage device, identifying a starting LBA associated with a request to write a second data set to the storage device, comparing the starting LBA of the second data set to the starting LBA of the first data set stored in the memory, and upon identifying a match between the starting LBA of the second data set and the starting LBA of the first data set, suspending the request to write the second data set to the storage device.

Abstract: A method of transferring memory from an active to a standby memory in an FT Server system. The method includes the steps of: reserving a portion of memory using BIOS; loading and initializing an FT Kernel Mode Driver; loading and initializing an FT Virtual Machine Manager (FTVMM) including the Second Level Address Translation table SLAT into the reserved memory. In another embodiment, the method includes tracking memory accesses using the FTVMM's SLAT in Reserved Memory and tracking “L2” Guest memory accesses by tracking the current Guest's SLAT and intercepting the Hypervisor's writes to the SLAT. In yet another embodiment, the method includes entering Brownout by collecting the D-Bits; invalidating the processor's cached SLAT translation entries, and copying the dirtied pages from the active memory to memory in the second Subsystem. In one embodiment, the method includes entering Blackout and moving the final dirty pages from active to the mirror memory.

Abstract: Techniques for enabling live migration of VMs with passthrough PCI devices are provided. In one set of embodiments, a hypervisor of a host system can create a copy of a DMA buffer used by a VM of the host system and a passthrough PCI device of the VM. The hypervisor can further designate one of the DMA buffer or the copy of the DMA buffer as a vCPU buffer that is accessible by the VM, and designate the other of the DMA buffer or the copy of the DMA buffer as a device buffer that is accessible by the passthrough PCI device. The hypervisor can then synchronize the vCPU buffer and the device buffer with each other as the VM and passthrough PCI device interact with their respective buffers, and as part of the synchronization can intercept DMA work requests submitted by the VM/completed by the passthrough PCI device.

Abstract: A system and method for managing data in a storage system are provided. A system and method may include receiving a data block and a logical address and identifying, in a set of address sequence range (ASR) objects, an ASR object having an address sequence range that is close to the logical address. A system and method may include storing the data block in the storage system, and updating the ASR object to include the logical address.

Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.

Abstract: A late load technique deploys a virtualization layer underneath an operating system executing on a node of a network environment to enable the virtualization layer to control the operating system. Binary executable files (binaries) for the virtualization layer may be included in a ring 0 driver loaded in memory of the node with the highest privilege level (e.g., host mode ring 0) needed to control the guest operating system. The ring 0 driver may request allocation of physical memory from the guest operating system for the virtualization layer and thereafter suspend the guest operating system and hardware resources of the node in a deterministic manner. The ring 0 driver may capture architectural states of those resources, which are used to create a virtual machine and virtual devices having initial states that are substantially identical to the states of the operating system and hardware resources at the time of suspension.

Abstract: A method of initializing a storage device includes; resetting an interface chip in response to a reset signal generated by the memory controller, loading a boot loader from a nonvolatile memory device via the interface chip in response to a nonvolatile memory initialization signal generated by the memory controller, and initializing a plurality of nonvolatile memory devices by executing the boot loader in the memory controller.

Abstract: Methods, systems, and computer readable media can be operable to facilitate the remote signing of images created at a signing client. An image can be output from a signing client to a remote signing server, and the signing server can identify, from information carried by the image, one or more signatures needed by the image and/or encoding algorithm(s) to be applied to the image. The signing server can encode the image using the requested encoding algorithm(s) and/or can add requested signature(s) to the image, and the signing server can output the signed image to one or more designated targets.

Abstract: A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.

Abstract: A system for building virtual servers via non-structured strings is disclosed according to an embodiment. The system comprises a build server that is configured by execution of an application on a processor to obtain, from a ticketing system, server design data having non-structured strings. The system determines that the server design data does not designate a primary virtual network interface controller based on the non-structured strings, and isolates, via the non-structured strings, an interface type parameter and an interface alias parameter for each of a plurality of virtual network interface controllers. Responsive to the determination, the system generates an interface metric for each of a plurality of virtual network interface controllers. The primary network interface is automatically determined by the system based on one of the interface metrics corresponding to one of the plurality of virtual network interface controllers.

Abstract: A disclosed method includes obtaining a physical address corresponding to a virtual address responsive to detecting a virtual address associated with a memory access instruction and, responsive to identifying a memory page associated with the physical address as a sensitive memory page, evaluating sensitive access information associated with the memory page. If the sensitive access information satisfies a sensitive access criteria, invoking a sensitive access handler to control execution of the memory access instruction.

Abstract: Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilizes an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.

Abstract: In a computer system with a disk array that has physical storage devices arranged as logical storage units and is capable of carrying out hardware storage operations on a per logical storage unit basis, data movement operations can be carried out on a per-file basis. A data mover software component for use in a computer or storage system enables cloning and initialization of data to provide high data throughput without moving the data between the kernel and application levels.

Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.

Abstract: A converter member connects between an electronic device and a load media for transmitting data. The converter member includes a first plug and a second plug electrically connected with the first plug. The first plug is detachably connected to the electronic device, and the second plug is detachably connected to the load media. The first plug and the second plug are two different type plugs. The data from the load media is transmitted to the electronic device through the second plug and the first plug orderly.

Abstract: A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a host physical memory address translated from a guest physical memory address in the address space of a virtual machine to which an I/O device has been assigned. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the host physical memory address, emulate a first message signaled interrupt identifying the host physical memory address.

Abstract: A backbone channel transmits first through third channel packets among Advanced eXtensible Interface (AXI) 5 channel packets. The backbone channel is managed by dividing the backbone channel into a first sub-channel and a second sub-channel, transmitting the first channel packet through the first sub-channel, transmitting the second channel packet through the second sub-channel, and transmitting the third channel packet through both the first sub-channel and the second sub-channel.

Abstract: A plurality of logical volumes are stored at a plurality of sites. A command to execute an operation on a logical volume is received. A determination is made as to whether a rule associated with the logical volume permits execution of the operation on the logical volume. In response to determining that the rule associated with the logical volume permits execution of the operation on the logical volume, the operation is executed on the logical volume.

Abstract: A plurality of logical volumes are stored at a plurality of sites. A command to execute an operation on a logical volume is received. A determination is made as to whether a rule associated with the logical volume permits execution of the operation on the logical volume. In response to determining that the rule associated with the logical volume permits execution of the operation on the logical volume, the operation is executed on the logical volume.

Abstract: Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.

Abstract: A method, system, and computer program product for planning relational database joins in systems with multiple parallel computational units. The computer implemented method compiles an execution plan for dissemination to a plurality of execution units where the plan combines a smaller left-side table with a portion of a larger right-side object to reduce system overhead. Upon receiving a request for a join operation comprising left-side table data and right-side table data where the left-side table data is much smaller than the right-side table data, then the method compiles a plan to apportion an entirety of the left-side table data and only a portion of the right-side object to a plurality of computational units. The method continues by sending distribution instructions to respective computational units where the distribution instructions include retrieval of the entirety of the left-side table data with the retrieval of only a portion of the right-side object.