Abstract: A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device.

Abstract: An aspect includes a method for providing direct communication between a server and a network switch in a cell-based fabric. A host channel adapter of a cell fabric hardware accelerator is configured to provide the server with direct access to memory within the network switch. A plurality of data packets having a fixed size is received at the host channel adapter from the server. The host channel adapter is coupled to a bus of the server. A direct transmission is performed from the cell fabric hardware accelerator to the memory within the network switch on an interconnect bus to write the data packets directly into the memory.

Abstract: A method and apparatus for monitor and mwait in a distributed cache architecture is disclosed. One embodiment includes an execution thread sending a MONITOR request for an address to a portion of a distributed cache that stores the data corresponding to that address. At the distributed cache portion the MONITOR request and an associated speculative state is recorded locally for the execution thread. The execution thread then issues an MWAIT instruction for the address. At the distributed cache portion the MWAIT and an associated wait-to-trigger state are recorded for the execution thread. When a write request matching the address is received at the distributed cache portion, a monitor-wake event is then sent to the execution thread and the associated monitor state at the distributed cache portion for that execution thread can be reset to idle.

Abstract: Methods and systems for DMA operations are provided. A plurality of control blocks are stored at a memory of a receive module of a device coupled to a computing device, where the control blocks store information regarding data packets stored at a receive buffer accessible to the receive module. At least a first control block and a second control block are retrieved from the memory; and a first DMA register set is assigned to the first control block and a second DMA register set is assigned to the second control block. The first control block and the second control block are simultaneously pre-processed to configure the first DMA register set and the second DMA register set.

Abstract: An aspect includes providing direct communication between a server and a network switch in a cell-based fabric. A host channel adapter of a cell fabric hardware accelerator is configured to provide the server with direct access to memory within the network switch. A plurality of data packets having a fixed size is received at the host channel adapter from the server. The host channel adapter is coupled to a bus of the server. A direct transmission is performed from the cell fabric hardware accelerator to the memory within the network switch on an interconnect bus to write the data packets directly into the memory.

Abstract: A memory storage scheme specially adapted for wear leveling (or other reorganization of logical memory space). Memory space includes a logical memory space of M addressable blocks of data, stored as rows or pages, and N substitute rows or pages. Data is periodically shuffled by copying data from one of the M addressable blocks to a substitute row, with the donating row then becoming part of substitute memory space, available for ensuing wear leveling operations, using a stride address. The disclosed techniques enable equation-based address translation, obviating need for an address translation table. An embodiment performs address translation entirely in hardware, for example, integrated with a memory device to perform wear leveling or data scrambling, in a manner entirely transparent to a memory controller. In addition, the stride address can represent an offset greater than one (e.g., greater than one row) and can be dynamically varied.

Abstract: A device supports the processing of multiple active applications in a processor through a mapping system that securely identifies and differentiates commands issued by clients. An entity selection signal is generated by the mapping system to signal the processor to process an algorithm and provide services for a specific client using the commands identified for that client and data permitted by a client tracking system for that client. Other data accesses and commands identified for other clients are restricted when processing the algorithm.

Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

Abstract: A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

Abstract: Methods and structure for improved shipping of I/O requests among multiple storage controllers of a clustered storage system. Minimal processing of a received I/O request is performed in a first controller to determine whether the I/O request is directed to a logical volume that is owned by the first controller or to a logical volume owned by another controller. For requests to logical volumes owned by another controller, the original I/O request is modified to indicate the target device address of the other controller. The first controller then ships the request to the other controller and configures DMA capabilities of the first controller to exchange data associated with the shipped request between the other controller and memory of the host system.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

Abstract: A method for transmitting data between an information processing device and a storage device, in which the storage device includes a buffer memory and flash chips, includes: receiving a first write request including data to be written and an address used for the flash chip of the storage device; allocating a first memory unit in the information processing device for the first write request; sending a write command including data, the address used for the flash chip of the storage device and address used for the buffer memory, to the storage device, in which the address used for the buffer memory corresponds to the first memory unit; receiving a message indicating the performing of the write command by the storage device has been completed, from the storage device; and releasing the first memory unit.

Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.

Abstract: A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

Abstract: A method that includes creating a DMA group, adding a first I/O device to the DMA group, and adding a second I/O device to the DMA group. The method further includes instructing an I/O MMU to create a shared virtual DMA address, mapping a memory location to the shared virtual DMA address in the DMA group translation table, and providing the shared virtual DMA address to the device drivers. The method further includes determining that the first I/O device has received DMA group data, instructing a first DMA controller to transfer the DMA group data from the first I/O device to the shared virtual DMA address, determining that the shared virtual DMA address has received the DMA group data, and instructing a second DMA controller to transfer the DMA group data from the memory location corresponding to the shared virtual DMA address to the second I/O device.

Abstract: In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

Abstract: According to embodiments of the invention, methods, computer readable storage medium, and a computer system for determining a mapping mode for a DMA data transfer are disclosed. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode.

Abstract: According to embodiments of the invention, methods, computer readable storage medium, and a computer system for determining a mapping mode for a DMA data transfer are disclosed. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode.

Abstract: A method and system for managing direct memory access (DMA) in a computer system without a host input/output memory management unit (IOMMU). The computer system hosts virtual machines and allows memory overcommit. The computer receives, from a guest operating system that runs on a virtual machine, a request for mapping a guest address to a bus address. The computer translates the guest address to a host address and pins a memory page containing the host address to keep the memory page in host memory. The host address is then returned to the guest operating system to allow a device to use the host address as the bus address for direct memory access (DMA) to a buffer managed by the guest operating system.

Abstract: A direct memory access controller for efficiently detecting a character string within memory, the direct memory access controller generating signatures of character strings stored within the memory and comparing the generated signatures with the signature of the character string for which detection is desired.

Abstract: A direct memory access circuit includes a buffer handler configured to store received data within a buffer in a buffer memory coupled to the direct memory access circuit and to generate a descriptor for the buffer. The direct memory access circuit further includes a descriptor handler coupled to the buffer handler. The descriptor handler is configured to determine a descriptor address for the descriptor and to store the descriptor at the determined address within a descriptor memory coupled to the direct memory access circuit.

Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Abstract: A method includes processing a direct memory access (DMA) descriptor in a DMA controller. The method includes storing first data of the DMA descriptor at an address that is identified by second data of the DMA descriptor.

Abstract: Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.

Abstract: Described herein are embodiments of methods and systems of using a timer based memory buffer for metrology. One embodiment of the method comprises receiving metrology data from one or more metrology sensors; writing at least part of the metrology data to a volatile memory; incrementing a write pointer to indicate the metrology data contained within the volatile memory; and repeating the above until a timer expires, then reading at least a portion of the metrology data from the volatile memory.

Abstract: A system and method operable to manage misaligned direct memory access (DMA) data transfers is provided. This method involves determining a delta between N bytes of data to be copied from within a local side buffer (source location) to a remote buffer (destination location). After the delta is determined a tail of the same length is copied to temporary storage. Then the N bytes of data on the local side buffer minus the tail will be shifted to align the N bytes of data to be copied from within the local side buffer to the starting address of the destination location in the remote buffer. The pre-shifted N bytes of data within the local side buffer may be DMA transferred to the remote buffer. The tail transferred to temporary storage may then be copied from temporary storage to the remote buffer.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral devices share the page table and perform a DMA (Direct Memory Access) operation on the system memory unit using the page table, where each of the peripheral devices includes a memory management unit having a translation lookaside buffer. The control unit divides a total virtual address space corresponding to the page table into sub virtual address spaces, assigns the sub virtual address spaces to the peripheral devices, respectively, allocates and releases a DMA buffer in the system memory unit, and updates the page table, where at least two of the sub virtual address spaces have different sizes from each other. The CPU controls the peripheral devices and the control unit. The application processor reduces memory consumption.

Abstract: Methods and apparatus for packing received Serial Attached SCSI (SAS) frames in buffers for transmission to a host system memory. SAS frames are received from another SAS device and stored in a frame buffer memory. User data in the received frames has appended SCSI Data Integrity Fields (DIF information) to enhance reliability. Features and aspects hereof use the DIF information to validate the user data and then strip the DIF information to densely pack the validated user data in a DMA staging buffer for transmission to a host's system buffer memory using DMA features of the SAS device. The DMA circuit is programmed and started when the staging buffer is filled to at least a threshold amount of data to thereby improve efficacy of the DMA transfer performance. Other criteria may also be employed to determine when to start the DMA circuit.

Abstract: One embodiment relates to an integrated circuit configured to communicate a low-latency word category over a multi-lane link. A transmitter controller is configured to transmit words belonging to the low-latency word category only over a designated lane of the multi-lane link and to transmit words belonging to non-low-latency word categories over any available lane of the multi-lane link. A receiver controller may be configured to determine a word category of a word received over the designated lane and, if the word category is determined to be the low-latency word category, then read the word from the designated lane before lane-to-lane deskew is completed. Other embodiments, aspects, and features of the invention are also disclosed.

Abstract: Methods and systems for latency optimized ATS usage are disclosed. Aspects of one method may include communicating a memory access request using an untranslated address and also an address translation request using the same untranslated address, where the translation request may be sent without waiting for a result of the memory access request. The memory access request and the address translation request may be made in either order. A translation agent may be used to translate the untranslated address, and the translated address may be communicated to the device that made the memory access request. The translated address may also be used to make the memory access. Accordingly, by communicating the translated address without having to wait for completion of the memory access, or vice versa, the requesting device may reduce latency for memory accesses when using untranslated addresses.

Abstract: A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer.

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing, in a first memory, data to be transmitted. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to retrieve, for transmission, first data from a first buffer indexed by a first descriptor in the ring of descriptors and before second data is determined to be ready for transmission, the first address translation being associated with a second DMA operation for retrieving the second data from the first memory.

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing received data in a first memory. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to store first received data in a first buffer indexed by a first descriptor in the ring of descriptors and before second received data to be stored in the first memory is received, the first address translation being associated with a second DMA operation for storing the second received data in the first memory.

Abstract: A spa node comprising a spa controller, a power sense adapter configured to compute power being drawn by selected spa components; a spa network adapter, and a home network adapter, each of the three adapters including a wireless transceiver wherein the spa network adapter is configured to receive power data transmitted over a wireless link by the power sense adapter and to further receive status/performance data from the spa controller. The home network adapter is configured to receive power and status data transmitted by the spa network adapter over a wireless link and to convert that data to a form suitable for transmission to an Internet access point. The home network adapter is further linkable over the Internet to a central server, a dealer computer and a spa owner or user computer.

Abstract: A system for controlling a storage device. A semiconductor chip of the storage device, includes a first memory. The first memory corresponds to a first type of memory, is configured to perform random access memory functions, and is not configured to perform direct memory access functions. A second memory external to the semiconductor chip is configured to interface with the semiconductor chip. The second memory corresponds to a second type of memory that is different than the first type of memory, is configured to perform direct memory access functions, and is not configured to perform random access memory function. The second memory includes a memory cell and an interface configured to interface between components of the second memory including the memory cell and the semiconductor chip.

Abstract: A system and method can support different message queues in a transactional middleware machine environment. The transactional middleware machine environment includes an advertized table that comprises a first queue table and a second queue table, with the first queue table storing address information for a first message queue and the second queue table storing address information for a second message queue. The advertized table is further adaptive to be used by a first transactional client to locate a transactional service provided by a transactional server. The first transactional client operates to look up the first queue table for a key that indicates the address information of the transactional service that is stored in the second queue table.

Abstract: A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unifed address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from the client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: Disclosed is an operating method of a direct memory access (DMA) controller having first and second DMA channels. The operating method includes iteratively performing a DMA transfer operation of the first DMA channel based upon loop information and transfer information of the first DMA channel; iteratively performing a DMA transfer operation of the second DMA channel based upon loop information and transfer information of the second DMA channel; reconfiguring the transfer and loop information of the first and second DMA channels; and again performing the iteratively performing a DMA transfer operation of the first DMA channel and the iteratively performing a DMA transfer operation of the first DMA channel based upon the reconfigured transfer and loop information of the first and second DMA channels.

Abstract: An input/output (I/O) device includes a memory buffer and off-loading hardware. The off-loading hardware is configured to accept from a host a scatter/gather list including one or more entries. The entries include at least a pattern-type entry that specifies a period of a periodic pattern of addresses that are to be accessed in a memory of the host. The off-loading hardware is configured to transfer data between the memory buffer of the I/O device and the memory of the host by accessing the addresses in the memory of the host in accordance with the periodic pattern at intervals indicated in the period.

Abstract: A memory device includes a data read/write block configured to store data in memory cells and read data from the memory cells; an input/output buffer block configured to buffer input data inputted through data pads and control signals inputted through control signal pads, and provide buffered input data and control signals to the data read/write block, and buffer read data read out through the data read/write block, and output buffered read data to an external device through the data pads, and a control logic configured to activate or deactivate the input/output buffer block based on an address which is inputted from the external device.

Abstract: A storage device includes a control unit that carries out a communication process with a host device that is connected via a bus; a storage unit into which data from the host device is written; and a storage control unit that controls access to the storage unit. The control unit returns an acknowledgment to the host device in the case where the control u has received acknowledgment return request information broadcasted from the host device to a plurality of storage devices connected to the bus after the end of a period in which data is written into the plurality of storage devices by the host device, and the data has been successfully written into the storage unit of the storage device to which the control unit belongs.

Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.

Abstract: According to embodiments of the invention, methods, computer readable storage medium, and a computer system for determining a mapping mode for a DMA data transfer are disclosed. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode.

Abstract: According to embodiments of the invention, methods, computer readable storage medium, and a computer system for determining a mapping mode for a DMA data transfer are disclosed. The method may include receiving a request for a DMA data transfer within a computer system. The method may also include determining a mapping mode for the DMA data transfer based on available system profile data in response to receiving the request. The method may also include mapping the memory using the determined mapping mode.

Abstract: A verification method is executed by an information processing apparatus to verify priority control of transfer devices. The verification method includes: firstly generating pieces of data having different data amounts; secondly generating addresses in which a value is shifted; firstly associating the generated addresses in an ascending order of value of address with the generated pieces of data in a descending order of data amount; secondly associating device information indicating the transfer devices in a descending order of the degree of priority allocated to the transfer devices with the generated pieces of data in the descending order of data amount; instructing transfer of a generated piece of data to the address associated with the data, to the transfer device indicated by the device information associated with the data; and verifying the degree of priority according to a result of the transfer of the data.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.