Abstract: The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller (10) includes a main processor (12), a memory (14), a device interface (18) adapted to interface a peripheral component (28-32), such as a RAID storage device, with the storage system controller, and an operations sequencer (24). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.

Abstract: A data processing device (302) used in a serial communication system, in which a communication is carried out with a host computer (300) via a serial interface includes: a central processing unit (310) for executing a process operation with respect to a bus event; an interrupt mode setting unit (308) for previously setting any one of a first interrupt mode and a second interrupt mode every bus event; and a process executing unit (308) for executing either a process made of the first interrupt mode or a process made of the second interrupt mode based upon a content previously set by the interrupt mode setting unit when a bus event occurs.

Abstract: In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.

Abstract: A interrupt controller includes specialized interfaces and controls for ARM7TDMI-type microcontroller cores. Such sends interrupt vectors and IRQ or FIQ interrupt requests to the processor depending on particular interrupts received. Wherein, THUMB program execution is more economical with program code space, and an interrupt service routine preamble is coded in ARM program code to cause a switch to THUMB program execution. The interrupt service routine preamble is shared amongst all the interrupt service routines to further economize on program code space.

Abstract: A local area computer network provides distributed parallel processing. The network comprises a plurality of workstations or personal computers, each having preemptive multitasking for the interactive execution of a local task in the foreground concurrently with a remote network subtask in the background. A large compute-intensive task may be partitioned into a plurality of parallel subtasks executed simultaneously with each subtask executed in the background by a respective workstations without substantial interference with the local task being executed concurrently in the foreground. The computer time and processing power which would otherwise be wasted while waiting for slow input/output operations is instead utilized to provide a powerful parallel multiprocessor system for handling compute-intensive tasks too large for an individual workstations.

Abstract: Apparatus for testing a data storage system. The system includes an interface adapted for disposition between a host computer and a disk drives. The interface has a controller and an addressable memory interconnected through a bus. The system operates asynchronously in transferring data between the controller and the memory. The testing apparatus includes a generator for injecting an electrical disturbance into a predetermined point in the interface during a selected state when data is transferred between the memory and the controller. The disturbance is initiated in response to an actuation signal. A storage medium is provided for storing the state. A comparator is provided for monitoring current operating state of the interface and the selected state stored in the storage medium and for producing the activation signal when the current operating state of the system and the selected operating state have a predetermined relationship.

Abstract: A reception indicator circuit is provided for use in an apparatus, wherein the apparatus enables a host system to receive information packets from a medium. The reception indicator circuit has a delay calculator, a byte count comparator and a signal asserter. The delay calculator selects and reads a reference delay value in one of N number of length-delay data storage elements. A reference length value contained in the one of N number of length-delay data storage elements corresponds to a length value of an information packet being received by the apparatus. The length value of the information packet is determined based on data in the information packet. The byte count comparator detects when the reference delay value number of bytes in the information packet have been received by the apparatus. The signal asserter asserts a reception indication signal when the byte count comparator detects that the reference delay value number of bytes in the information packet have been received by the apparatus.

Abstract: An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt vector register is included in the computer CPU. The interrupt vector register does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register by the programmable software, triggers the hardware logic. Once triggered, this logic performs certain control tasks, the end result of which is returning to the programmable software, a vector corresponding to the interrupt having highest priority. The programmable software can implement various software policies, in addition to the hardware policy implemented by the hardware logic.

Abstract: A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order to execute the interrupt service routine. Instead of using the interrupt acknowledge cycles normally used to locate an interrupt vector, and then using the interrupt vector to locate an interrupt descriptor, the interrupt descriptor is stored in an RTI register coupled to the RTI control unit. In one embodiment, the CPU is configured not to save processor context upon initiation of a real time interrupt. Instead, as register resources are needed by the real time service routine, these resources are allocated. Registers allocated for real time use are indicated in the RTI register. In yet another embodiment, the CPU is configured with lockable cache lines in the instruction and data caches.

Abstract: When a BIOS driver call request is generated in an environment of an OS operating in a protect mode, an IN or OUT instruction is executed to cause an I/O trap SMI generator to generate an I/O trap SMI. The mode of a CPU is switched from the protect mode to an SMM in accordance with the I/O trap SMI. In the SMM, the BIOS driver is executed. When the process of the BIOS driver is completed, the mode of the CPU is returned from the SMM to the protect mode, thereby shifting control to the OS. The BIOS can be directly called in the protect mode without building a routine for switching the CPU operating mode in the OS or application program operating in the protect mode.

Abstract: A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple potentially interrupting devices and determining whether a pending interrupt request exists based on a status of the shared interrupt request flag. In the event that a pending interrupt request exists, a notification of the pending interrupt request is provided to an interrupt service routine. In the event that a pending interrupt request does not exist the circuitry that is reading or polling the shared interrupt request flag delays for a polling interval and then repeats reading or polling the shared interrupt request flag and determining whether a pending interrupt request exists.

Abstract: A RISC type microprocessor for implementing multi-stage pipeline processing. The RISC type microprocessor includes mode allocating means, interrupt controlling means and a jump instruction table. The mode allocating means is used for allocating a first mode for cyclically executing processes corresponding to a plurality of interrupts at predetermined intervals or a second mode for successively executing the processes corresponding to the interrupts. The interrupt controlling means is used for controlling the interrupts corresponding to the mode allocated by the mode allocating means, and is operable to save particular information to a stack upon occurrence of an interrupt and to fetch the particular information from the stack upon completion of the interrupt process. The jump instruction table is used in processing interrupts without stopping the multi-stage pipeline processing.

Abstract: A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt request from an interrupting device is logged, all previous transactions from the interrupting device is allowed to complete while no further transactions from the interrupting device is allowed. All other devices operates normally during this time. Once the interrupt request is serviced, the interrupting device is allowed to resume normal operation. By providing a storage area to store the interrupt requests from devices on a subordinate bus, the unprocessed transactions in the bridge device and transactions from all other devices can be processed in an orderly manner.

Abstract: Each node of multinode computer system includes an interrupt controller, a pair of send and receive queues, and a state machine for communicating interrupts between nodes. The communication among the interrupt controller, the state machine, and the queues is coordinated by a queue manager. For sending an interrupt, the interrupt controller accepts an interrupt placed on a bus within the node and intended for another node and stores it in the send queue. The controller then notifies the interrupt source that the interrupt has been accepted before it is transmitted to other node. The interrupt has a first form suitable for transmission on the bus. A state machine within the node takes the interrupt from the send queue and puts the interrupt into a second form suitable for transmission across a network connecting the multiple nodes.

Abstract: In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special consideration to the interrupt of the microinstructions translated from a macroinstruction using two control bit data, accelerate the reaction time to interrupts, and expand the time frame within which to process interrupts while maintaining a precise interrupt. When a macroinstruction is decoded into microinstructions at the decoder stage in a pipelined data processor, a control bit called the atomic bit provides the system with the information about the boundary of the precise interrupt, and another control bit called the LOCK bit decides when an external interrupt can be processed and masks an interrupt when the system state does not allow any interrupt to be processed.

Abstract: A system and method for preventing a program from being run under a debugger utility program. The method is part of a routine which is stored along with a software program on a hard drive of a computer system. The computer system has a processor for running both the software program and the routine and is capable of operating in a debug mode. The routine prevents unauthorized access to the software program, such as when the processor is running in the debug mode. When the processor is running the software program, the program can initiate execution of the routine. Once initiated, the routine checks a certain registers of the processor to determine if it is operating in the debug mode and if so, stops the processor from continuing to run the software program.

Abstract: Referred to is a flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag. As a result thereof, it is determined whether or no the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern n the interrupt activation condition flag storing unit. As a result of the determination, an interrupt process is performed in accordance with an operational description storing unit which stores a process corresponding to the flag pattern if the pattern exits. Thereafter, bit for the flag corresponding to the executed process is cleared out.

Abstract: In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto.

Abstract: In a method for switching between multiple system hosts (154,164,174,184) on a CompactPCI bus (110,120), a hot swap controller (166,186) provides to a special arbiter (820) a high priority request signal and the special arbiter (820) provides to the hot swap controller a grant signal only when the CompactPCI bus is idle. The hot swap controller (166,186) provides to the special arbiter (820) a float signal causing the special arbiter (820) to disable the system host signals, which include one or more grant signals for granting bus access to devices on the CompactPCI bus (110,120), one or more reset signals for resetting the devices, one or more interrupts and one or more clock signals provided to devices. The hot swap controller (166,186) transfers control of the CompactPCI bus (110,120) to a standby system host 154,164,174,184).

Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods.

Abstract: Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge trigger mode interrupt request output. The edge trigger mode interrupt request remains asserted until an End of Interrupt input is asserted, indicating that the CPU has completed servicing the prior interrupt. The edge trigger mode interrupt request is then deasserted.

Abstract: A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the method includes executing a first SMI handler routine in response to receiving a first SMI from a first SM requester. In response to receiving a second SMI asserted by a second SM requester, the method determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the method interrupts executing the first SMI handler routine and executes a second SMI handler routine corresponding to the second SMI request. Otherwise, the method completes executing the first SMI handler routine and then executes the second SMI handler routine.

Abstract: During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication to central processing units (CPUs). According to the invention, these IRQs are detected by a Secondary Interrupt Mapping (SIM) device which transports the signals according to a 2 bit bus protocol over a wired-"OR" bus structure to a Primary Interrupt Mapping (PIM) device located on the compatibility PCI bus. The PIM and SIM transport IRQs over the bus structure utilizing a timing sequence and 2-bit bus protocol. The PIM serves as the master device of the timing sequence and at appropriately designated sequence slots receives bus command signals from the SIM which map to particular interrupt signals that the PIM forwards to the interrupt controller on the compatibility PCI bus for transportation to the CPUs.

Abstract: An interrupt processing system and method for an information processing system of pipeline control type are disclosed. The occurrence of an exception is detected for each plurality of instructions to be processed in parallel. The occurrences of exceptions, when detected for a plurality of the instructions to be processed in parallel, are reported collectively according to each cause of the exceptions. In the case where the occurrences of exceptions are reported for a plurality of the instructions to be processed in parallel by an exception reporting unit, an interrupt request is issued. In response to the interrupt request, the pipeline processing is restored by an instruction control unit to the state before execution of the leading one of the plurality of the instructions to be processed in parallel for which the occurrences of exceptions are detected, and the instructions are reexecuted one by one sequentially from the leading one of the plurality of instructions through the instruction control unit.

Abstract: A volume control handler allows users to dynamically alter the volume level of an audio device when the device is under control of a DOS mode application. The dynamic volume adjustment is performed without pausing or halting the DOS mode application. A system incorporating the volume control handler allows users of DOS mode applications to control a device's volume output in a manner similar to that provided by WINDOWS-compliant applications.

Abstract: A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mechanism, which includes one or more timers and/or one or more counters. Interrupts are generated, for example, after a predetermined time has elapsed after a DMA completion or after a certain number of packets are counted.

Abstract: A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: Multiple nodes can concurrently gain membership in a cluster of nodes of a distributed computer system by broadcasting reconfiguration messages to all nodes of the distributed computer system. In response to a reconfiguration request resulting from a node petitioning to join a cluster or a node leaving the cluster, each node determines to which nodes of the distributed computer system the node is connected, i.e., which are sending reconfiguration messages which the node receives. In addition, if multiple nodes fail substantially simultaneously, each node which continues to operate does not receive a reconfiguration message from each of the failed nodes and the failed nodes are omitted from the proposed new cluster. Thus, multiple simultaneous failures are processed in a single reconfiguration. Each of the member nodes of the proposed cluster determine the membership of the proposed cluster and broadcast a reconfiguration message to all proposed member nodes and collects similar messages.

Abstract: An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine.

Abstract: A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an appropriate one of a second plurality of registers and indicate which interrupts are masked. The second plurality of registers are arranged in a predetermined priority and each contains the starting address of an appropriate interrupt service routine for the corresponding interrupt. The interrupt signals are mapped to the outputs of a plurality of logical "OR" gates according to the contents of the first plurality of registers by a plurality of de-multiplexers coupled to the inputs of the plurality of logical "OR" gates. Each logical "OR" gate corresponds to one of the second plurality of registers.

Abstract: A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.

Abstract: A system and method for debugging and tuning a process control network having distributed control functions implemented by a set of field devices communicatively linked over a bus includes an operational scheduler that schedules the execution of each of a number of process control functions and communication functions performed by the field devices to define a process control scheme and an indicator that indicates one or more process control scheme locations at which the process control scheme is to be automatically or conditionally interrupted to thereby enable debugging and/or tuning of the process control network. A controller interrupts execution of the process control scheme at the indicated flow locations, communicates process data to a user to display the current or a past state of the process to a user and waits for user input before continuing with operation of the process control scheme.

Abstract: In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction.

Abstract: In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor.

Abstract: Each of microcodes 1 has an interrupt prohibit bit 10 that specifies acceptance or nonacceptance of an interrupt request. Upon occurrence of an interrupt request, a processor refers to a value set in the interrupt prohibit bit 10 of the microcode 1 being currently executed. When "0" is set to the interrupt prohibit bit 10, the processor accepts the interrupt request, and when "1" is set to the interrupt prohibit bit 10, the processor rejects the interrupt request and starts executing a succeeding microcode. This allows the processor to safely execute certain instructions without interruption, as indicated by the interrupt prohibit bit 10 contained in the microcode 1 being currently executed.

Abstract: A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes within the system to a very accurate global time clock such that all the nodes running the application stop and restart running the application at the same time. Within the time period bounded by the stop and restart time, all the performance monitoring data is transferred from performance monitoring data buffers to a secondary memory.

Abstract: A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a timer. The stop grant state is an intermediate power consumption state between the sleep mode and the normal state. The timer may include a software system management interrupt timer. The system may also include processing to determine the cause of the switch from the stop grant state to the normal state.

Abstract: A method and apparatus for processing interrupts for a plurality of components connected to and sharing an interrupt line in a data processing system in which interrupts are level sensitive interrupts. The components are connected to the interrupt line by interrupt connections, such as a pin. An interrupt is detected when the interrupt line is in a first state, while an interrupt is absent when the interrupt line is in a second state. Other interrupts cannot be processed while the interrupt line is in a first state. In response to detecting one or more interrupts, the connection associated with the component, for which one or more interrupts are generated, is disabled until all of the interrupts are processed. Disabling the interrupt connection allows the interrupt line to return to the first state and for additional interrupts for other components connected to the interrupt line to be detected and processed.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.

Abstract: Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer system. Initiation of generation of the inter-processor interrupt is requested by a peripheral component device, such as a PCI bus controller, not directly connected to an APIC bus extending to interrupt controllers associated with each of the processors of the multi-processor computer system. The interrupt permitted to be initiated by the peripheral component device includes, inter alia, a remote read request.

Abstract: The invention is a computer system with a button array on the computer chassis for simulating the operation of common consumer electronic devices. Each button of the array of buttons is hardwired to the system processor. Upon activation of one of these buttons, an interrupt signal is sent to the system processor. The system processor halts whatever it is doing, and subsequently identifies the activated button. A signal generator attached to the buttons then sends the system processor a second interrupt signal, such that upon exiting the handling of the first interrupt, the system processor is presented with a second interrupt. The system processor then handles the second interrupt. While handling this second interrupt, the system processor executes whatever function corresponds to the activated button. The system processor then exits the handling of the second interrupt and resumes whatever activity it was engaged in before the activation of the button.

Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To this end, interrupt-time data structures and representations are precomputed and represented. The taxonomy of real time data types is organized. It is preferable to include isochronous media, together with supporting algorithms and heuristics.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.

Abstract: I/O systems of computers typically utilize multiple layered drivers to process I/O requests. I/O requests are passed from one driver to another in a defined sequence with each driver performing its processing in turn. The present invention provides a system and method for interrupting the normal sequence of processing and for allowing drivers that would not normally process an I/O request to intervene and assume control for processing the I/O request. The system and method provides a flexible and extensible way to define special types of files or directories that require special processing by a particular driver. The present invention adds a "reparse point" attribute to a file or directory. The reparse point attribute preferably contains a tag which identifies a particular driver as the owner of the reparse point and a data value which can be used by the owner driver to store any information necessary or useful in processing an I/O request.