Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: Embodiments of apparatuses, methods, and systems for interrupt remapping based on requestor identification are disclosed. In one embodiment, an apparatus includes look-up logic, and comparison logic. The look-up logic is to look-up an entry associated with an interrupt request in a data structure. The comparison logic is to compare an identifier of the requestor to a source value in the entry.

Abstract: A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.

Abstract: A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are made known and predictable greatly simplify the task of coordinating quiesce responses within the system. When latencies are not fixed and topologies such as open or closed bus architectures are be used a more dynamic approach is required to ensure system serialization. Adaptive quiesce logic on each node's SCE can dynamically identify the role of the node within the system and automatically configure itself to guarantee that no enabled processor within the entire system receives a quiesce indication before all processors have reached the stopped state. This is also true for systems where nodes are being concurrently added or removed during system operation. Bus states process quiesce requests.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.

Abstract: A method and apparatus for optimization of multiprocessor synchronization and allocation of system management memory space is herein described. When a system management interrupt (SMI) is received, a first processor checks the state of a second processor, which may be done by checking a storage medium storing values representative of the second processor's state. The first processor handles the SMI or waits for the second processor dependent on the state of the second processor. Furthermore, system management memory is allocated where a first system management memory space assigned to a first processor overlaps a second system management memory space assigned to a second processor, leaving first and second non-overlapping region.

Abstract: A computer system and a control method thereof are provided. The computer system includes an interrupt generator which responds to a system management event to generate an interrupt; a processor which stores a state of an operating system (OS) which is being executed, and enters a system managing mode if the interrupt is input when executing an order of an operating system (OS); and at least one IO device which receives the interrupt from the interrupt generator, and conducts a predetermined system management operation corresponding to the interrupt. Thus, the present invention provides a computer system and a control method thereof improving reliability and stability of system management, and improving system performance.

Abstract: An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a processor. The interrupt handler executes, upon expiration of a time period, to determine if a threshold error rate associated with the device has been equaled or exceeded.

Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status indicating signal received through an interrupt status indicating pin of a north bridge module or by the triggering of a peripheral device coupled to the south bridge chip, the PIC sends an interrupt signal to the CPU via an interrupt request signal pin when the computer system is in a PIC mode. The APIC is disabled when the computer system is in the PIC mode, and enabled when the computer system is in an APIC mode to generate a memory write cycle message to the CPU in response to the triggering of the peripheral device. The power management unit is optionally triggered with the interrupt signal or the interrupt status indicating signal to awake the CPU.

Abstract: In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.

Abstract: Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a corresponding registered signal function with said receiving computer program; sending a communication including a request signal identifier by said sending computer program to said receiving computer program; receiving said communication sent at (B) by said receiving computer program; and performing said corresponding registered signal function without context switching of said receiving computer program if said request signal identifier received is coupled with said registered signal identifier. A system, router, computer program and computer program product are also disclosed.

Abstract: A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.

Abstract: A computer device, an input/output (“I/O”) communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications between a device controller and a coprocessor. Advantageously, the various embodiments of the invention obviate a requirement for specialized circuitry on a motherboard to establish peer-to-peer communications. In one embodiment, an I/O communication subsystem includes a bus interface for coupling the I/O communication subsystem to a general-purpose bus. It also includes a device controller being configured to generate an interrupt as an interrupt message packet for a coprocessor, which, in turn, interrupts processing functions that otherwise are performed by the host processor. The device controller can reside either internal or external to the I/O communication subsystem.

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the power and configuration management system of the computer system.

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

Abstract: A method of testing the priority levels of the interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when enabled, each interrupt source having a default priority level and an associated memory, the interrupt sources having a service order in which they are to be serviced, the method comprising the steps of: (a) sorting the interrupt sources in descending service order; (b) determining an array of priority levels to be assigned in a pre-arranged sequence to selections of interrupts in descending service order; (c) incrementing a global counter; (d) assigning the array of priority levels to a selected group of interrupts, the remainder of the interrupts assuming their pre-assigned priority level; (e) enabling all interrupts simultaneously except the interrupt source having the highest priority level so that the interrupt having the second highest priority level executes its interrupt service routine; (f) transferring the value

Abstract: An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system and interrupt resources of a second type which are not managed by the operating system. Regarding an interrupt generated by an interrupt resource of the first type, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of the first type, based on the address information of the interrupt vector register. At the same time, with regard to an interrupt generated by an interrupt resource of the second type, the interrupt control apparatus in the present invention launches an extended interrupt entry function which is not subject to the aforementioned scheduling process, based on the address information held in the interrupt vector register.

Abstract: Platform independent alert detection and management. A software-based intermediary referred to herein as an alert proxy is used to transform binary, device-specific event or alert data into user-friendly plain text explanations of the event. A management device containing the alert proxy is able to return a contextually correct description of the event to an administrator or other interested party based upon the characteristics of the specific device initiating the event. Event data may be generated by alert software executing on an alert-enabled managed client or by alert hardware embodied within an alert-enabled managed client.

Abstract: A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to case and counts of selected performance monitoring events. A timestamp may be associated with each event. In one embodiment, the pre and post handler is used with trap on branch to log trace records prior to and immediate after taking a branch. In another embodiment, a pre handler is enabled to log trace records that occur prior to executing interrupt service routines. A post handler is enabled to log trace records that occur after the interrupt service routines is executed and prior to returning to normal execution. Resulting low-level performance trace data may be collected by the user at a later time for more structured performance analysis.

Abstract: There is disclosed a computer entity having a trusted component which compiles an event log for events occurring on a computer platform. The event log contains event data of types which are pre-specified by a user by inputting details through a dialogue display generated by the trusted component. Items which can be monitored include data files, applications drivers and the like. The trusted component operates through a monitoring agent which may be launched onto the computer platform. The monitoring agent may be periodically interrogated to make sure that it is operating correctly and responding to interrogations by the trusted component.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: An invention is provided for a synchronous transfer of control. An asynchronous interrupt exception is received, and in response, the value of a reference counter is determined. The value of the reference counter is based on the execution of synchronized code. Generally, the reference counter is initialized to a predetermined number, and altered based on the execution of synchronized code. When the asynchronous interrupt exception is received, the method is asynchronously interrupted when the value of the reference counter is equal to the predetermined number.

Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Abstract: A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception.

Abstract: A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared program memory and a plurality of processor subsystems coupled to the shared program memory to concurrently execute program instructions stored in the shared program memory. The host system is capable of independently debugging each subsystem. During debugging, the host device inserts breakpoints into the shared program memory and tracks the debug breakpoints to determine which subsystems are associated with the breakpoints. When a subsystem executes a breakpoint associated with that subsystem, the subsystem halts until the host gathers necessary debug information from the subsystem. However, when a subsystem executes a breakpoint that is not associated with that subsystem, the host system causes the subsystem to execute the original program instructions and proceed as directed.

Abstract: Client software stores an identifier corresponding to memory configuration data of interest and causes a software interrupt that requests a memory configuration read function. An interrupt read function handler then reads the data of interest responsive to the identifier and returns the data of interest. The client software may include, for example, BIOS firmware or application software executing in real or protected mode. The memory configuration information may be stored in a hidden I/O or MMIO register device. In such an embodiment, the interrupt handler may enable access to the hidden I/O or MMIO register device prior to reading the data of interest and disable access to the hidden I/O or MMIO register device afterwards.

Abstract: Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

Abstract: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

Abstract: A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcontroller also has a control circuit that, by storing the next few program instructions internally before placing the memory in standby, or by delaying the interrupt signal, provides extra time for memory operation to stabilize on exit from the standby mode. Malfunctions on recovery from standby are thereby prevented, and the microcontroller can conserve power by placing the memory in a deep standby mode with a comparatively long recovery time.

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: System and method for external bus device support. The system comprises a processor, a memory, one or more external bus controllers and a basic input-output system (BIOS). The BIOS contains an external bus support component to cause a periodic interrupt to be generated and to provide support for external bus enabled devices responsive to the periodic interrupt. The method comprises obtaining a portion of the memory to be used to maintain a plurality of external bus device data; causing an interrupt to be periodically generated; and handling input produced by external bus enabled devices using the portion of the memory. The interrupt may be a system management interrupt (SMI) of the 32-bit Intel Architecture (IA-32). The external bus controller may be a Universal Serial Bus (USB) host controller, the external bus devices may be USB devices, and the external bus support component may be a USB support component.

Abstract: Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform).

Abstract: A system and method for implementing hardware event driven soft real-time interrupts on a serial bus. In one embodiment, the serial bus comprises a universal serial bus. One embodiment of the presently described system includes a client device coupled to a host device. In one embodiment, the host places the client device in an interrupt mode by causing the client device to enter a suspend state. While in the interrupt mode, the client device sends an interrupt request signal to indicate it has interrupt data. In one embodiment, the host device indicates to the client device to enter the interrupt mode by sending a set interrupt mode signal. In response, the client device enters the interrupt mode and sends an interrupt request signal to the host to indicate it has interrupt data.

Abstract: An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the processor is in a low power state when it asserts the interrupt pending signal, then the power management device causes the processor to enter a high power state to allow the processor to service the pending interrupt.

Abstract: Provided are a method, system and article of manufacture for adjusting interrupt levels. A current system interrupt rate at a computational device is determined, wherein the current system interrupt rate is a sum of interrupt rates from a plurality of interrupt generating agents. The current system interrupt rate is compared with at least one threshold interrupt rate associated with the computational device. Based on the comparison, an interrupt moderation level is adjusted at an interrupt generating agent of the plurality of interrupt generating agents.

Abstract: Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract: In an digital video disk player the timely acquisition of specific data types is particularly important during trick mode operation. During trick modes a controller can provide enhanced control capability by employing interrupt requests having priorities that differ from those used during normal play mode operation. A method for controlling a microcontroller in digital disk apparatus having at least two reproducing modes. The method comprises the steps of prioritizing the microcontroller interrupts during a first reproducing mode, and in a second reproducing mode reordering the microcontroller interrupt priorities.

Abstract: A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

Abstract: The present invention comprises a method and system for configuring the language of a BIOS of a computer system. The method and system comprise providing a plurality of BIOS images in the computer system, each of the plurality of BIOS images being related to a particular language, selecting one of the pluralities of BIOS images based on the language supported by the computer system and utilizing the selected BIOS to configure the computer system. Through the use of the method and system in accordance with the present invention, the language being supported by the computer system is determined when the computer system is booted up as opposed to when the computer system is being built. This results in an increase in manufacturing productivity since original equipment manufacturers can build computer systems without having to worry about language restrictions.

Abstract: In one aspect, a method is disclosed. The method includes trapping initializing data of a first interrupt type to a first interrupt controller, re-routing the initializing data of the first interrupt type to a second interrupt controller, and configuring the second interrupt controller to manage interrupt of the first interrupt type.

Abstract: In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal processor sends a data packet to a target digital signal processor. Upon arrival at the target digital signal processor, its receiver drives the arriving request packet into an I/O memory and triggers a transmitter interrupt. Next, the pull interrupt causes the transmitter to execute on a next packet boundary the pull request packet. Finally, the execution of the pull request causes the transmitter to pull a portion of the local I/O memory and send it back to the requester digital signal processor. The same physical portion of the I/O memory is overlaid with two logical uses, a receiver channel and a transmitter code block.

Abstract: An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, implement interrupt processing in an efficient, parallel manner that reduces average interrupt latency. In one embodiment, the apparatus may include an interrupt receiver coupled to a plurality of interrupt handlers which respond to uniquely identified interrupting events. Responses may occur in an overlapping fashion in a multi-threaded environment. The system may include a processor coupled to a local memory and an interrupt receiver. Interrupt handlers, which may be coupled to the interrupt receiver, process uniquely identified interrupts. The method may include receiving multiple interrupts and executing corresponding interrupt handlers scheduled in response to receipt of the interrupts, with each handler being uniquely adapted to service a particular interrupting event.