Interrupt Processing Patents (Class 710/260)
  • Patent number: 11119814
    Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jesse Arroyo, Prathima Kommineni, Timothy J. Schimke, Shyama Venugopal
  • Patent number: 11119691
    Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 14, 2021
    Assignee: Seagate Technology LLC
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, Chris Randall Stone, Charles Edward Peet, Allen Vestal, Siddharth Krishna Kumar
  • Patent number: 11113215
    Abstract: An electronic device which schedules a plurality of tasks, and an operating method thereof. The electronic device includes a processor and a memory operatively connected to the processor, and when being executed, the memory stores instructions that cause the processor to: detect occurrence of an interrupt requesting performance of a second task while performing a first task; obtain reference values according to a time of the first task, and reference values according to a time of the second task; schedule the first task and the second task based on a reference value of the first task and a reference value of the second task which correspond to a time at which the interrupt occurs; and process the first task and the second task based on a result of the scheduling. Other embodiments are possible.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Oh, Kibeom Kim, Sangho Lee, Yeona Hong, Gajin Song
  • Patent number: 11113216
    Abstract: A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Sen-Yu Cheng, Yan-Ting Chen, Po-Kai Chi
  • Patent number: 11113190
    Abstract: A computing device implemented method for building a mutable type is disclosed. A data structure is generated in a contiguous section of memory. The data structure includes an element portion and an over-allocation portion. The element portion stores elements accessible with an index. A gap object is inserted into the over-allocation portion. The gap object is garbage collected.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John J. Duffy, Krzysztof J. Cwalina, Matthew G. Ellis
  • Patent number: 11106457
    Abstract: A computing device includes a processor, a volatile memory, and a non-volatile memory. The computing device receives a firmware update that includes updated firmware runtime components, such as updated runtime interrupt handlers (e.g. SMI handlers). The computing device stores the updated firmware runtime components in the volatile memory (e.g. RAM) of the device. The computing device also causes the updated firmware runtime components stored in the volatile memory to be used during the runtime of the computing device instead of one or more other firmware runtime components previously stored in the volatile memory. For example, the contents of one or more interrupt routing tables can be adjusted such that updated runtime interrupt handlers stored in volatile memory are used instead of previously installed and potentially insecure runtime interrupt handlers. On a subsequent reboot of the computing device, updated firmware runtime components stored in the non-volatile memory will be utilized.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 31, 2021
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Senthamizhsey Subramanian, Srinivasan N. Rao, Feliks Polyudov, Bejean David Mosher
  • Patent number: 11093150
    Abstract: An image processing apparatus includes a block output unit, an arithmetic processing circuit, a data reading circuit, and a block descriptor generation unit. The block output unit outputs a block image based on an input block descriptor. The data reading circuit reads the block image after image processing from the arithmetic processing circuit based on an output block descriptor and outputs the block image after the image processing. The arithmetic processing circuit executes the image processing on block images for one band in accordance with an input band request. The data reading circuit outputs block images for one band in accordance with an output band request. The block descriptor generation unit stores input block descriptors and output block descriptors for at least one band in the predetermined memory in line with timing of the input band request or the output band request.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 17, 2021
    Assignee: KYOCERA DOCUMENT SOLUTIONS INC.
    Inventor: Seiki Satomi
  • Patent number: 11086384
    Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 10, 2021
    Assignee: INTEL CORPORATION
    Inventor: Christopher Lake
  • Patent number: 11086797
    Abstract: A method for restricting write access to a non-volatile memory. The method includes receiving a request to write to a protected location in the non-volatile memory and determining whether the protected location is in a write-protected state. If the protected location is not in a write-protected state, the method includes writing data indicated by the request to the protected location. If the protected location is in a write-protected state, the method includes rejecting the request. The protected location stores a validation key to validate the contents of another portion of the non-volatile memory.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: August 10, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Joseph E. Foster, David Plaquin, James M. Mann
  • Patent number: 11074204
    Abstract: A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventor: Sarathy Jayakumar
  • Patent number: 11068422
    Abstract: Described herein are embodiments that adaptively reduce the number of interrupts that occur between a device controller and a computer system. Device commands are submitted to the controller by an operating system on behalf of an application. The device performs the received commands and indicates command completions to the controller. A counter counts completions, and if the count exceeds a threshold number, the controller generates an interrupt to the computer system. If the count is greater than zero and the timeout interval has expired, then the controller generates an interrupt to the computer system. In some embodiments, the application attaches flags to one of the commands indicating that an interrupt relating to completion of the flagged command should be generated as soon as possible or that an interrupt relating to completion of all commands prior to and including the flagged command should be generated as soon as possible.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 20, 2021
    Assignee: VMware, Inc.
    Inventors: Amy Tai, Igor Smolyar, Dan Tsafrir, Michael Wei, Nadav Amit
  • Patent number: 11063850
    Abstract: A reporting device communicates with a master device by a first component and a daisy-chained second component. The reporting device receives a signal from the master device via the first component. The signal triggers the reporting device to transmit synchronously a telemetry data packet on the daisy-chained second component when a downstream device is coupled to the second component. The reporting device receives a first header packet having an address of the reporting device, transmits the telemetry data packet to the downstream device, and transmits a second header packet having an address of the downstream device.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 13, 2021
    Assignee: ATI TECHNOLOGIES ULS
    Inventors: Eric D. Meyer, Nima Osqueizadeh
  • Patent number: 11056159
    Abstract: A data acquisition method of acquiring and latching data with a timing based on an input signal supplied to an input port, the method including: acquiring and retaining the data with a timing of when an edge of the input signal is detected, and starting a timer; and at the time of expiration of the timer, if the level of the input signal is a first level that is unchanged from start of the timer, latching the retained data and if the level of the input signal is a second level that is changed from the start of the timer, discarding the retained data.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 6, 2021
    Assignee: OMRON Corporation
    Inventor: Kotaro Asaba
  • Patent number: 11036662
    Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 15, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kyohei Yamaguchi, Daisuke Kawakami, Hiroyuki Hamasaki
  • Patent number: 11036541
    Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 15, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aditya Bhandari, Bruce J. Sherwin, Jr., Xin David Zhang
  • Patent number: 11029996
    Abstract: A computer system comprising a plurality of processor units, resources for executing a harmonic set of tasks, and a task interrupt switch device having inputs for receiving a common time base and the task interrupts, outputs each connected to a respective one of the processor units, registers each corresponding a to respective one of the outputs, reinitializable counters each corresponding to a respective one of the outputs, and a control unit arranged to distribute the task interrupts between the outputs as a function of the values of the registers and of the counters.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 8, 2021
    Assignee: Safran Electronics & Defense
    Inventors: Céline Liu, Christian Valpard
  • Patent number: 11023398
    Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Sascha Junghans, Peter Dana Driever
  • Patent number: 11012915
    Abstract: Methods, systems, and devices for wireless communications are described. In some wireless systems, a base station centralized unit (CU) may communicate with a user equipment (UE) through a multi-hop backhaul architecture. This multi-hop backhaul connection may include a donor base station and any number of relay base stations connected via backhaul links. In some cases, the relay base stations or the UE may experience data congestion in a logical channel-specific buffer. The relay base stations or UE may implement backpressure signaling (e.g., in the medium access control (MAC) layer) to mitigate the congestion. A wireless device operating as a mobile termination (MT) endpoint may transmit a backpressure report message to a wireless device operating as a base station distributed unit (DU) endpoint for the logical channel. The base station DU may adjust a scheduling rate for data unit transmissions over the indicated logical channel based on the backpressure report.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 18, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Karl Georg Hampel, Junyi Li, Hong Cheng, Navid Abedini, Muhammad Nazmul Islam, Jianghong Luo
  • Patent number: 10999223
    Abstract: Approaches, techniques, and mechanisms are disclosed for reutilizing discarded link data in a buffer space for buffering data units in a network device. Rather than wasting resources on garbage collection of such link data when a data unit is dropped, the link data is used as a free list that indicates buffer entries in which new data may be stored. In an embodiment, operations of the buffer may further be enhanced by re-using the discarded link data as link data for a new data unit. The link data for a formerly buffered data unit may be assigned exclusively to a new data unit, which uses the discarded link data to determine where to store its constituent data. As a consequence, the discarded link data actually serves as valid link data for the new data unit, and new link data need not be generated for the new data unit.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Innovium, Inc.
    Inventors: Ajit Kumar Jain, Mohammad Kamel Issa
  • Patent number: 10996897
    Abstract: Storage virtualization techniques allow directories to be stored remotely, for example, by a cloud storage provider, but in a manner that appears to a user or application running on a local computing device as if the directories are stored locally—even though the data of those directories may not be resident on the local computing device. That is, the contents of directories that may exist in the cloud look and behave as if they were stored locally on a computing device.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 4, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Neal R. Christiansen, Ravisankar V Pudipeddi, Scott A. Brender, Sarosh C. Havewala, Ping Xie, Craig Ashley Barkhouse, Lei Shi
  • Patent number: 10997090
    Abstract: Techniques are disclosed for enabling an integrated sensor hub of a main computer to access a detachable peripheral device. In an embodiment, a system includes a main unit having a peripheral interface, an embedded controller, and a device controller. The peripheral interface is configured to be detachably coupled to a peripheral. The peripheral includes a control unit and an input/output device. The embedded controller is configured to communicate with the control unit of the peripheral via the peripheral interface while the peripheral is attached to the peripheral interface. The embedded controller includes at least one data register, and in some embodiments, a set of data registers, configured to store data relating to the peripheral and to the corresponding input/output device. The device controller is configured to read data from the data register(s) of the embedded controller, write data to the data register(s) of the embedded controller, or both.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Guangyu Ren, Kun-Feng Lin, Ke Han
  • Patent number: 10990682
    Abstract: A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 27, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Ilan Margalit
  • Patent number: 10990407
    Abstract: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventor: Peter P. Waskiewicz, Jr.
  • Patent number: 10969858
    Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Daniel U. Becker, Aditya Kesiraju, Srikanth Balasubramanian, Venkatram Krishnaswamy, Boris S. Alvarez-Heredia
  • Patent number: 10970242
    Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 6, 2021
    Assignee: VMware, Inc.
    Inventors: Mallik Mahalingam, Michael Nelson
  • Patent number: 10963351
    Abstract: A data backup system can be implemented in a data storage enclosure that houses a backup controller. The backup controller may be connected to a storage media and a backup media via a switch. The backup media can be resassigned from an unavailable condition to an available condition by the backup controller in response to predicted degradation in the storage media. The backup media may be connected to a root complex of the backup controller via a backup partition and selection feature.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 30, 2021
    Assignee: Seagate Technology LLC
    Inventors: Lalitha Kameswar Mallela, Sumanranjan Mitra, AppaRao Puli, Siva Prakash Rajaram
  • Patent number: 10949212
    Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Siegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Patent number: 10942739
    Abstract: A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. When the at least one runtime processor state configuration value does not match the processor state check value an exception is generated. Improved security of the data processing apparatus is thus provided.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: March 9, 2021
    Assignee: ARM Limited
    Inventor: Jason Parker
  • Patent number: 10942820
    Abstract: Embodiments are described for performing an uninterrupted restore in a storage system in view of one or more abort events. A restore agent receives writes one or more data blocks to a conditional construction container. A parent interrupt service routine (ISR) polls for abort events. In response to an abort event, an intermediate interrupt is generated that spawns a child processes for each process of the restore. The intermediate ISR logs each child ISR, the process it is responsible for, and the intermediate interrupt, for later restoration of the restore state. After a recovery of the above event, then each child ISR can be called to restore its state. After restoring the state, the restore agent resumes the restore from where the abort event was detected. The child ISRs are re-entrant. If another abort event is detected, the restore state can again be saved and later resumed from that state.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 9, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mahesh Reddy A V, Battal Chetan, Mahantesh Ambaljeri, Swaroop Shankar D H
  • Patent number: 10936313
    Abstract: An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Yogesh Deshpande, Pandurang V. Deshpande
  • Patent number: 10922024
    Abstract: This disclosure describes performing a pre-activate check of reader nodes prior to deploying a new serialization format at writer nodes in a service provider network. Prior to activating a new serialization format on writer nodes, writer nodes query a metrics service within the service provider network for an aggregated serialization format version metric value for reader nodes, where the aggregated serialization format version metric value corresponds to a percentile of reader nodes that do not currently de-serialize objects using the newest deserialization format, e.g., the percentile of reader nodes that are not configured to recognize serialized objects serialized in the newest serialization format. The aggregated serialization format version metric values are based on a metric indicating the most recent serialization format version that a reader node is configured to de-serialize, which are emitted as reader nodes read serialized objects from a data store of the service provider network.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 16, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Peter L. Thomas
  • Patent number: 10922111
    Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. In addition, the bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: February 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christoph Raisch, Marco Kraemer, Bernd Nerz, Donald William Schmidt, Peter Dana Driever
  • Patent number: 10909246
    Abstract: The present disclosure provides trusted kernel-based anti-attack data processors. One exemplary processor comprises: a trusted kernel exception vector table configured to provide a handling entry for kernel switching; a trusted kernel stack pointer register storing a trusted kernel stack pointer that points to a trusted kernel stack space; and a trusted zone in the trusted kernel stack space, the trusted zone including a program status register storing a flag bit of a starting kernel for the kernel switching, a program pointer, and a general register. When the data processor performs kernel switching from a non-trusted kernel to a trusted kernel, the trusted kernel locates the handling entry for the kernel switching and performs the switching. An underlying software protection mechanism can be provided for switching entries of a trusted kernel. Therefore, security during switching processes between a trusted kernel and a non-trusted kernel can be improved.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 2, 2021
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventors: Xiaoxia Cui, Chunqiang Li, Guangen Hou, Li Chen
  • Patent number: 10908909
    Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: February 2, 2021
    Assignee: Optimum Semiconductor Technologies Inc.
    Inventors: Mayan Moudgill, Gary Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan
  • Patent number: 10866833
    Abstract: Provided is a method and apparatus for implementing microkernel architecture of industrial server. The method includes calculation of dependency of control programs according to a microkernel task type weight and a microkernel task priority weight and/or a control program running time weight prior to startup of a system, and determination of the number of the control programs running on each physical core and each control program running on multiple physical cores according to the dependency.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 15, 2020
    Assignee: KYLAND TECHNOLOGY CO., LTD.
    Inventors: Ping Li, Zhiwei Yan, Qiyun Jiang, Xueqiang Qiu, Xingpei Tang
  • Patent number: 10853228
    Abstract: A device receives test parameters associated with testing an application that utilizes source data, and causes source containers, for the source data, to be temporarily created in a cloud computing environment, based on the test parameters. The device provides the source data to the source containers in the cloud computing environment, and causes other containers, for the application, to be temporarily created in the cloud computing environment, based on the test parameters. The device creates a file for testing the application with the source containers and the other containers, based on the test parameters, and causes the application to be executed with the source containers and the other containers, based on the file. The device receives results associated with executing the application with the source containers and the other containers.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 1, 2020
    Assignee: Capital One Services, LLC
    Inventors: Raveender Kommera, Anoop Kunjuramanpillai, Karthik Gunapati, Sahithya Javvaji, Leonardo Gomide, Daniel Tresnak, Anilkumar Baddula, Nathan Gloier
  • Patent number: 10846223
    Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 24, 2020
    Assignee: LENOVO Enterprise Solutions (Singapore) PTE. LTD
    Inventors: Makoto Ono, Jonathan R. Hinkle, William G. Holland, Randolph S. Kolvick
  • Patent number: 10831483
    Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Bryan R. White, Ankur N. Shah, Altug Koker, David Puffer, Aditya Navale
  • Patent number: 10827043
    Abstract: The invention is a method and device for normalizing communication. The method includes receiving on a first device a first message via a first protocol from a second device; transmitting a second message to a third device via a second protocol, wherein the second message is transmitted using a first spreading factor; initiating a delay timer upon transmitting the second message, wherein a duration of the delay timer is based on a second spreading factor, wherein the second spreading factor is greater than or equal to the first spreading factor; receiving a third message from the third device via the second protocol, wherein the third message is transmitted using the first spreading factor, and wherein the third message is in response to the second message; and upon the expiration of the delay timer, sending a fourth message to the second device via the first protocol. The device includes the hardware and instructions to perform the method.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: November 3, 2020
    Assignee: Hall Labs LLC
    Inventors: Mark Hall, Craig Boswell, John Robinson, Taylor Robbins, David R. Hall
  • Patent number: 10817433
    Abstract: Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Altug Koker, Ankur Shah, Murali Ramadoss, Niranjan Cooray
  • Patent number: 10802900
    Abstract: A compute node, a failure detection method thereof and a cloud data processing system are provided. The method is adapted to the cloud data processing system having a plurality of compute nodes and at least one management node, and includes following steps: performing a self-inspection on operating statuses of services being provided and resource usage statuses, and reporting an inspection result to the management node by each compute node; dynamically adjusting a time interval of a next report and informing the management node of the time interval by the compute node; and checking a report condition of the inspection result according to the time interval by the management node, so as to determine whether the compute node fails.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 13, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Chieh Huang, Tzu-Chia Wang
  • Patent number: 10802764
    Abstract: Storage virtualization techniques allow directories to be stored remotely, for example, by a cloud storage provider, but in a manner that appears to a user or application running on a local computing device as if the directories are stored locally—even though the data of those directories may not be resident on the local computing device. That is, the contents of directories that may exist in the cloud look and behave as if they were stored locally on a computing device.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: October 13, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Neal R. Christiansen, Ravisankar V Pudipeddi, Scott A. Brender, Sarosh C. Havewala, Ping Xie, Craig Ashley Barkhouse, Lei Shi
  • Patent number: 10795829
    Abstract: Techniques and mechanisms for configuring services which variously facilitate data protection. In an embodiment, circuitry coupled to a memory comprises both a first circuit which calculates integrity information based on data, and a second circuit which evaluates data validity based on such integrity information. A configuration of the circuitry provides a combination of one or more services which is specific to a corresponding domain of the memory. With respect to accesses to the corresponding domain, the configuration prevents an access to the first circuit while an access to the second circuit is permitted. In another embodiment, a processor signals the circuitry to transition to another configuration which, with respect to accesses to the corresponding domain, permits access to both the first circuit and the second circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Vedvyas Shanbhogue
  • Patent number: 10790686
    Abstract: The present invention relates to a system for protecting a battery, and to a battery protecting system, which obtains state information of a battery through two different state obtaining units and diagnoses whether the battery has a problem based on the two elements of state information obtained through the two state obtaining units and reference state information, thereby more certainly diagnosing a state of the battery and stably protecting a load from the battery in the problem state.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 29, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Ki Young Lee, Jae Chan Lee
  • Patent number: 10768960
    Abstract: The present invention discloses a method for affinity binding of interrupt of a virtual network interface card, and a computer device. The method includes: receiving a request message sent by an IaaS resource management system, where the request message carries an interrupt affinity policy parameter of a virtual network interface card; performing one-to-one correspondence affinity binding between multiple virtual central processing units VCPUs and multiple physical central processing units PCPUs; performing affinity binding between a virtual interrupt of the virtual network interface card and a VCPU; and performing affinity binding between a physical interrupt of the virtual network interface card and a corresponding PCPU according to the affinity policy parameter.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 8, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Hai Xia
  • Patent number: 10761846
    Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Oracle International Corporation
    Inventor: Subhra Mazumdar
  • Patent number: 10754967
    Abstract: Systems, methods, and other embodiments associated with handling secure interrupts between security zones are described. According to one embodiment, an apparatus includes a memory divided between a secure zone and a non-secure zone and storing a plurality of applications. The secure zone provides exclusive access to secure assets of the apparatus. A processor with an interface module configured to, in response to receiving an interrupt request from a requesting application that executes on the processor in the non-secure zone, tunnel the interrupt request into the secure zone of the processor. The non-secure zone and the secure zone are configured as operating environments of the processor with separate security controls. The processor includes a monitor module configured to issue the secure interrupt to a trusted application that is one of the plurality of applications in the secure zone, wherein the trusted application is registered to handle the secure interrupt.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 25, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Gaurav Arora, Yongsen Chen, Adil Jagmag, Pontus Lidman, Haobo Yu, Yongbing Chen, Ailing Du
  • Patent number: 10742737
    Abstract: An electronic device includes a storage device including a plurality of doorbell registers; a host configured to perform a first interface operation with the storage device using a first command queue managed by a first doorbell register from among the plurality of doorbell registers; and a third-party device configured to perform a second interface operation with the storage device using a second command queue managed by a second doorbell register from among the plurality of doorbell registers, without an intervention of the host, wherein at least the second doorbell register is allocated as one of one or more dedicated registers for use only with operations of the third-party device.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younggeun Choi, Jaehong Min
  • Patent number: 10725835
    Abstract: Systems and methods for speculative execution of commands using a controller memory buffer are disclosed. Non-Volatile Memory Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on a host device placing commands into the submission queue and thereafter notifying a memory device of the commands placed in the submission queue. The submission queue may be resident in the memory device, such as in the controller buffer memory. Prior to notice by the host device, the memory device may determine that the commands have been placed in the submission queue and may speculatively execute the commands. Determining whether to begin processing a command prior to the host device notifying the memory device that the command is posted to the submission queue may be based on a type of command, such as a read or write command. The host device may override a command, such as a flush command, posted to the submission queue, and processing of the command canceled.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 10725756
    Abstract: The present invention involves systems and methods for replacement of function calls. In one embodiment, a function call is intercepted and modified to enforce a policy on a client device. The function call is intercepted by scanning code loaded for a launch of an application. The function call includes a first pointer value. The function call is modified by changing a first pointer value to a second pointer value. The second pointer value points to a customized function.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 28, 2020
    Assignee: VMWARE, INC.
    Inventors: Manish Jawa, Haim Tebeka, Craig Newell