Interrupt Processing Patents (Class 710/260)
  • Patent number: 10768960
    Abstract: The present invention discloses a method for affinity binding of interrupt of a virtual network interface card, and a computer device. The method includes: receiving a request message sent by an IaaS resource management system, where the request message carries an interrupt affinity policy parameter of a virtual network interface card; performing one-to-one correspondence affinity binding between multiple virtual central processing units VCPUs and multiple physical central processing units PCPUs; performing affinity binding between a virtual interrupt of the virtual network interface card and a VCPU; and performing affinity binding between a physical interrupt of the virtual network interface card and a corresponding PCPU according to the affinity policy parameter.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 8, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Hai Xia
  • Patent number: 10761846
    Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Oracle International Corporation
    Inventor: Subhra Mazumdar
  • Patent number: 10754967
    Abstract: Systems, methods, and other embodiments associated with handling secure interrupts between security zones are described. According to one embodiment, an apparatus includes a memory divided between a secure zone and a non-secure zone and storing a plurality of applications. The secure zone provides exclusive access to secure assets of the apparatus. A processor with an interface module configured to, in response to receiving an interrupt request from a requesting application that executes on the processor in the non-secure zone, tunnel the interrupt request into the secure zone of the processor. The non-secure zone and the secure zone are configured as operating environments of the processor with separate security controls. The processor includes a monitor module configured to issue the secure interrupt to a trusted application that is one of the plurality of applications in the secure zone, wherein the trusted application is registered to handle the secure interrupt.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 25, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Gaurav Arora, Yongsen Chen, Adil Jagmag, Pontus Lidman, Haobo Yu, Yongbing Chen, Ailing Du
  • Patent number: 10742737
    Abstract: An electronic device includes a storage device including a plurality of doorbell registers; a host configured to perform a first interface operation with the storage device using a first command queue managed by a first doorbell register from among the plurality of doorbell registers; and a third-party device configured to perform a second interface operation with the storage device using a second command queue managed by a second doorbell register from among the plurality of doorbell registers, without an intervention of the host, wherein at least the second doorbell register is allocated as one of one or more dedicated registers for use only with operations of the third-party device.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younggeun Choi, Jaehong Min
  • Patent number: 10725756
    Abstract: The present invention involves systems and methods for replacement of function calls. In one embodiment, a function call is intercepted and modified to enforce a policy on a client device. The function call is intercepted by scanning code loaded for a launch of an application. The function call includes a first pointer value. The function call is modified by changing a first pointer value to a second pointer value. The second pointer value points to a customized function.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 28, 2020
    Assignee: VMWARE, INC.
    Inventors: Manish Jawa, Haim Tebeka, Craig Newell
  • Patent number: 10725835
    Abstract: Systems and methods for speculative execution of commands using a controller memory buffer are disclosed. Non-Volatile Memory Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on a host device placing commands into the submission queue and thereafter notifying a memory device of the commands placed in the submission queue. The submission queue may be resident in the memory device, such as in the controller buffer memory. Prior to notice by the host device, the memory device may determine that the commands have been placed in the submission queue and may speculatively execute the commands. Determining whether to begin processing a command prior to the host device notifying the memory device that the command is posted to the submission queue may be based on a type of command, such as a read or write command. The host device may override a command, such as a flush command, posted to the submission queue, and processing of the command canceled.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 10713146
    Abstract: Dynamic binary instrumentation (DBI) or dynamic binary translation (DBT) of an examined process can be postponed until a point of interest is reached. Portions of the examined process can be run in native mode until the point of interest is reached. Upon reaching the point of interest, DBI and/or DBT can be performed.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 14, 2020
    Assignee: Avast Software s.r.o.
    Inventor: Martin Hron
  • Patent number: 10715279
    Abstract: Methods of guaranteed reception and of processing of a digital signal in an avionics system comprise a plurality of computers, each computer comprising processing electronics and a software layer, which, on receipt of an event, carries out the following steps: at a first instant, sending to each of the other computers of a first signal (ACK) of reception of the event; at a second instant termed “TimeOut ACK”, if the electronic computer has not received one of the first signals emanating from one of the other computers, sending of a second failure signal (FAIL) to each of the other computers; at a third instant termed “TimeOut GARANTEED”, if a second failure signal has been received by the computer, absence of taking into account of the event by the computer and if no failure signal has been received by the computer, taking into account of the event by the data processing electronics of the computer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 14, 2020
    Assignee: THALES
    Inventor: Stéphane Treuchot
  • Patent number: 10706065
    Abstract: Methods and system are disclosed that generate an execution schedule to optimize a transformation of business. In one aspect, from multiple tables residing in multiple databases and storing business data associate with multiple business management systems, dependencies between the tables may be determined based on attributes associated with the tables. When execution time for transforming business data exists, a decrease time algorithm or a critical path algorithm may be executed to generate execution schedule and to calculate processor idle times during the transformation of business data. Based on the calculated processor idle times, whether or not to execute a local optimization algorithm may be determined. Based on the determination, execution schedule that optimize the transformation of business data may be generated. The transformation of business data may be executed based to the generated execution schedule that optimizes a time consumed for transforming the business data in the tables.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 7, 2020
    Assignee: SAP SE
    Inventors: Yadesh Gupta, Sudhir Verma
  • Patent number: 10705936
    Abstract: Embodiments of the present disclosure provide a system, a computer program product and a method for detecting and handling errors in a bus structure by obtaining error information from a plurality of hardware registers associated with a bus; in response to determining that a number of the errors in one or more hardware registers of the plurality of hardware registers exceeds a predetermined threshold, detecting performance of hardware devices corresponding to the one or more hardware registers; and in response to determining performance deterioration of one hardware device in the hardware devices corresponding to the one or more hardware registers, determining that an error occurs in the hardware device.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: July 7, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Colin Yong Zou, Man Lv, Wenbo Wang, Long Wang
  • Patent number: 10691487
    Abstract: A method comprises receiving a non-privileged disable interrupts instruction from a user application executing in user space, the non-privileged disable interrupts instruction having an operand with a non-zero value; determining a value in a special purpose register associated with disabling interrupts; and in response to determining that the value in the special purpose register associated with disabling interrupts is zero, disabling interrupts and placing the non-zero value of the operand in the special purpose register associated with disabling interrupts.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventor: Kelvin D. Nilsen
  • Patent number: 10678437
    Abstract: Embodiments of the present disclosure relate to a method and a device of managing input/output of a storage device. The storage device at least includes a first I/O port and a second I/O port. The method comprises receiving a first I/O request for the storage device, and determining a type of the first I/O request. Based on the type of the first I/O request, the first I/O request is dispatched to the first I/O port or the second I/O port. If the first I/O request is a read request, the first I/O request may be dispatched to the first I/O port, and if the first I/O request is determined as a write request, the first I/O request may be dispatched to the second I/O port. The method may reuse at least one of the first I/O port or the second I/O port.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Tao Xu, Man Lv, Bing Liu, James Lei Ni
  • Patent number: 10678722
    Abstract: Systems, methods, and computer program products to perform an operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt, and responsive to the lightweight HDEC interrupt, initiating an asynchronous hardware operation on the shared processor prior to completion of the dispatch cycle.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stuart Z. Jacobs, David A. Larson, Michael J. Vance
  • Patent number: 10671382
    Abstract: The invention relates to a device for integrating software components of a distributed real-time software system, said components being run on target hardware and on a development system, wherein the target hardware comprises computing nodes, and the development system comprises one or more computers. The device is designed as an expanded development system in which the computing nodes of the target hardware are connected to the computers of the development system via one or more time-controlled distributor units, wherein the expanded development system has a sparse global time of known precision, and wherein the computing nodes of the target hardware are connected to the computers of the development system via the one or more time-controlled distributor units such that the data content of a TT message template of a TT platform of the target hardware can be provided both by a simulation process of the development system as well as by an operative process of the target hardware in a timely manner.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 2, 2020
    Assignee: TTTECH AUTO AG
    Inventors: Hermann Kopetz, Stefan Poledna
  • Patent number: 10642752
    Abstract: Apparatuses, systems and methods associated microprocessor segment registers are disclosed herein. More particularly, the present disclosure relates to providing an auxiliary segment register(s) and/or auxiliary segment descriptor table(s), and various ways for their use, for example, providing new instructions for their access, or remapping existing processor resources. A machine might provide isolated execution regions and/or protected memory by associating or exclusively reserving some or all of the auxiliary segment register(s)/table(s) with a specific task, program, instruction sequence, etc. In some embodiments, such as in Internet of Things (IoT) or wearable devices, auxiliary resources may be employed to isolate mutually-distrustful code regions to facilitate engaging unknown devices. Other embodiments are also described and/or claimed.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 5, 2020
    Assignee: INTEL CORPORATION
    Inventors: Michael Lemay, Steffen Schulz
  • Patent number: 10644989
    Abstract: The invention provides for a method for running a computer network and such a computer network. The computer network comprises a number of devices being arranged in a stable daisy-chained loop, wherein each device comprises a bridge having at least three ports, whereby during running the computer network each device can take different states to avoid a loop, and whereby in case of rebooting the ports of at least one of the devices keep their current port states.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: May 5, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Stephan van Tienen, Tom De Brouwer, Marcel Versteeg, Marc Smaak
  • Patent number: 10637911
    Abstract: Embodiments of the disclosed subject matter include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits, and other electronic components having, for example, different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate. Other devices, methods, and interfaces are disclosed.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey D. Hoffman, Allan R Bjerke
  • Patent number: 10621353
    Abstract: In an embodiment, a system includes a processor and a non-volatile storage device. The non-volatile storage device may include a stored firmware program and a firmware loader. The firmware loader may be executable by the processor to read a first instruction of the stored firmware program; and generate, based on the first instruction, a set of runtime instructions to be included in a runtime firmware program, where the stored firmware program and the runtime firmware program are composed in a same programming language. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10585781
    Abstract: The invention relates to a method for debugging software components of a distributed real-time software system, wherein the target hardware comprises computer nodes and the development system comprises one or more computers.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 10, 2020
    Assignee: TTTech Auto AG
    Inventors: Hermann Kopetz, Stefan Poledna
  • Patent number: 10585823
    Abstract: A method, system, and computer program product for IO leveling comprising receiving an IO, determining if there is a delay for processing IO because of pending IO, based on a positive determination there is a delay for processing IO, determining a priority for the IO, and based on the priority of IO determining whether to process the IO.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 10, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Arieh Don, Assaf Natanzon
  • Patent number: 10579524
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 3, 2020
    Assignee: Mellanox Technologies Ltd.
    Inventors: Matthew Mattina, Chyi-Chang Miao
  • Patent number: 10572265
    Abstract: Register restoration or register reloading is selected. A restoration request to restore a plurality of architected registers is obtained. A determination is made as to whether a snapshot associated with the plurality of architected registers is valid. The snapshot provides in-core values for the plurality of architected registers. Based on the snapshot being valid, a determination is made as to whether the snapshot is to be used to recover an individual architected register of the plurality of architected registers. Based on determining the snapshot is to be used, the snapshot is used to recover the individual architected register. Based on determining the snapshot is not to be used, memory is used to recover the individual architected register.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10572671
    Abstract: The present disclosure discloses a processor security checking method, system and checking device. The processor security checking method includes: acquiring recording information of data read and write operations between a processor and a peripheral device, where the data read and write operation is a data read and write operation initiated by the processor or a data read and write operation initiated by the peripheral; and determining whether the processor is secure according to the recording information of the data read and write operation and an analysis result on the data read and write operation by the checking device. The embodiments of the present disclosure may detect hardware vulnerabilities and improve the security of hardware usage.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: February 25, 2020
    Assignee: Tsinghua University
    Inventors: Leibo Liu, Ao Luo, Shaojun Wei
  • Patent number: 10565078
    Abstract: Embodiments of the invention are directed to computer-implemented methods, computer systems, and computer program products for testing hardware. The method includes reading a stream of test instructions. The method further includes determining if test instruction exceptions present in the stream of test instructions. The method further includes inserting an interrupt into the test instruction stream for each determined test instruction exception. The method further includes generating one or more error messages for each determined test instruction exception.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Louis P. Gomes
  • Patent number: 10552279
    Abstract: Embodiments of the invention are directed to computer-implemented methods, computer systems, and computer program products for testing hardware. The method includes reading a stream of test instructions. The method further includes determining if test instruction exceptions present in the stream of test instructions. The method further includes inserting an interrupt into the test instruction stream for each determined test instruction exception. The method further includes generating one or more error messages for each determined test instruction exception.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Louis P. Gomes
  • Patent number: 10540172
    Abstract: A method includes performing operations to swap a system from a first userspace to a third userspace. Operations of the method include: operating the system using the first userspace, loading a second userspace into an operating system memory space accessible to a kernel, and installing a custom init replacement. Operations of the method further include signaling an init system to execute the custom init replacement, thereby operating the system using a second userspace, loading the third userspace into a second memory location accessible to the kernel, and signaling the init system to execute the custom init replacement a second time, thereby operating the system using the third userspace.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 21, 2020
    Assignee: SevOne, Inc.
    Inventors: Kenan Kessler, Andre Marianiello, Ashish Samuel
  • Patent number: 10515216
    Abstract: Techniques for monitoring based on a memory layout of an application are disclosed. A memory layout may be received, obtained, and/or generated from an application executing on a computer. Based on one or more attributes of a plurality of memory regions of the memory layout a memory layout fingerprint is generated. Additionally, memory region fingerprints are generated based on the one or more attributes for respective memory regions. The memory layout fingerprint and the memory region fingerprints are compared to respective previous memory layout fingerprints and the memory region fingerprints in order to determine whether malicious code and/or application drifting has occurred.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 24, 2019
    Assignee: PayPal, Inc.
    Inventor: Shlomi Boutnaru
  • Patent number: 10503523
    Abstract: Technologies for optimization of a memory controller include a computing device having a memory manager, a memory trainer, and a platform firmware. The memory manager reserves a space in memory of the computing device that is inaccessible to an operating system of the computing device. The memory trainer utilizes the reserved space to perform a memory training to determine configuration settings of the memory controller. After the configuration settings of the memory controller have been determined, the platform firmware configures the memory controller with the determined configuration settings.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Ravi Poovalur Rangarajan, Xiang Ma, Vincent J. Zimmer
  • Patent number: 10496572
    Abstract: In an embodiment, processors may have associated special purpose registers (SPRs) such as model specific registers (MSRs), used to communicate IPIs between the processors. In an embodiment, several types of IPIs may be defined, such as one or more of an immediate type, a deferred type, a retract type, and/or a non-waking type. The immediate IPI may be delivered and may cause the target processor to interrupt in response to receipt of the IPI. The deferred IPI may be delivered within a defined time limit, and not necessarily on receipt by the target processor. The retract IPI may cause a previously transmitted IPI to be cancelled (if it has not already caused the target processor to interrupt). A non-waking IPI may not cause the target processor to wake if it is asleep, but may be delivered when the target processor is awakened for another reason.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: December 3, 2019
    Assignee: Apple Inc.
    Inventors: John H. Kelm, Bernard J. Semeria, Joshua P. de Cesare, Shih-Chieh Wen
  • Patent number: 10498867
    Abstract: A network interface device includes an interface configured to receive data packets for a host processing device and an engine supporting a network interface device component of an application that is provided on the host processing device. In response to receiving data packets for the application, the engine is configured to cause at least some of the data packets to be available to the component of the application, to cause the data packets to be delivered to a protocol stack of the host processing device, and to receive control information associated the data packets from the protocol stack of the host processing device. The interface is configured to output an acknowledgement message comprising the control information.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 3, 2019
    Assignee: SOLARFLARE COMMUNICATIONS, INC.
    Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
  • Patent number: 10490861
    Abstract: A method for preventing battery from expanding is applied to awake an embedded controller to measure variations of a temperature and a storage capacity of a battery module of an electric device at a preset frequency to timely control the battery module to discharge when the electric device is in an off-state, so as to prevent the battery module from expanding and deforming.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: November 26, 2019
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Chun-Chi Wang
  • Patent number: 10459747
    Abstract: A system and method of scheduling timer access includes a first physical processor with a first physical timer executing a first guest virtual machine. A hypervisor determines an interrupt time remaining before an interrupt is scheduled and determines the interrupt time is greater than a threshold time. Responsive to determining that the interrupt time is greater than the threshold time, the hypervisor designates a second physical processor as a control processor with a control timer and sends, to the second physical processor, an interval time, which is a specific time duration. The hypervisor grants, to the first guest virtual machine, access to the first physical timer. The second physical processor detects that the interval time expires. Responsive to detecting that the interval time expired, an inter-processor interrupt is sent from the second physical processor to the first physical processor, triggering the first guest virtual machine to exit to the hypervisor.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: October 29, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 10437230
    Abstract: A numerical controller performs analysis as to whether or not an input machining program is required to be read at high speed at the time of execution of the machining program, stores the machining program in any one of a storage unit which reads a program at high speed and a storage unit which reads a program at low speed in accordance with the analysis result, and updates information on a storage destination of the machining program. In this way, the storage destination of the input machining program can be automatically selected in accordance with the contents of the machining program.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 8, 2019
    Assignee: FANUC CORPORATION
    Inventor: Tetsuya Inoue
  • Patent number: 10437755
    Abstract: A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies an event target number, a number of bits to ignore, an event source number, and an event priority. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10437308
    Abstract: A system and method for predictive virtual machine halt includes a memory, a host central processing unit (CPU) in communication with the memory, a hypervisor executing on the host CPU, and a virtual machine executing on the hypervisor. The virtual machine includes a virtual central processing unit (VCPU) and a guest. In an example, the hypervisor starts executing the VCPU on the host CPU. When the hypervisor detects a request to stop executing the VCPU from the guest, the hypervisor starts a timer associated with the host CPU. A predetermined amount of time is set in the timer. Then, the hypervisor stops executing the VCPU and starts executing a task on the host CPU while the timer is running. When the hypervisor detects an expiration of the timer, the hypervisor stops executing the task on the host CPU and restarts executing the VCPU on the host CPU.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 8, 2019
    Assignee: RED HAT, INC.
    Inventor: Michael Tsirkin
  • Patent number: 10430245
    Abstract: Systems and methods which provide low latency optimization configured to perform from the hardware layer across the operating system to an application. Low latency operation implemented in accordance with embodiments is optimized for a specific application, which interfaces with specific hardware, executing on a host processor-based system configured for low latency optimization according to the concepts herein. For example, a low latency optimization implementation may comprise various modules implemented in both the user space and Kernel space, wherein the modules cooperate to obtain information regarding the services and hardware utilized by an application and to provide such information for facilitating low latency operation with respect to the application.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 1, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventor: Chun Chung Lo
  • Patent number: 10416943
    Abstract: Provided is an image formation system including a plurality of image formation devices, for example, two image formation devices. The image formation devices each include a human body detector that detects whether human bodies are present in the vicinity of respective image formation devices. The image formation system stores information based on the result of human body detection by the human body detector and manages the tendency of persons in the vicinity of the image formation devices in accordance with the stored information.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 17, 2019
    Assignee: Konica Minolta, Inc.
    Inventor: Toshiyuki Maeshima
  • Patent number: 10402353
    Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Dragos Davidescu, Sandrine Lendre, Olivier Ferrand
  • Patent number: 10394730
    Abstract: Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 27, 2019
    Assignee: Cavium, LLC
    Inventors: Bryan W. Chin, Wu Ye, Yoganand Chillarige, Paul G. Scrobohaci, Scott Lurndal
  • Patent number: 10394571
    Abstract: A system and method are provided for passing a data file from a software utility to a service processor. The method includes loading, using a processor, an interrupt handler and runtime code during initialization of a computer before booting an operating system; requesting, using a processor, that the operating system transfer a data file via an interface; and transferring, using a processor, the data file to an area accessible to the runtime code. The method further includes requesting, using a processor, that the interrupt handler pass the data file to a service processor. Still further, the method includes passing, using a processor, the data file from the accessible area to the service processor via a memory-mapped input/output window of the service processor, wherein the data file is transferred to the service processor without waiting for a system reboot.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 27, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Scott N. Dunham, Sumeet Kochar
  • Patent number: 10366018
    Abstract: In a control apparatus which uses a CPU which does not have hardware for memory protection, a function is realized to detect unauthorized writing from a non-safety-related unit program in units of bits, for a safety-related unit data area of a RAM, a safety-related unit register area of an external integrated circuit, and a built-in peripheral I/O register of the CPU. A memory access monitoring unit requests an interrupt process upon detection of a write access of the safety-related unit program permitted to access a safety-related unit region. The interrupt process realizes a function to detect write access from a non-safety-related unit program area by using a program counter of a write access origin retracted to a stack area to judge whether the write access origin is a safety-related unit program or the non-safety-related unit program area, and judge, in units of bits, whether or not there is a change to a safety-related unit region.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: July 30, 2019
    Assignee: OKUMA CORPORATION
    Inventor: Yoshimasa Egi
  • Patent number: 10362568
    Abstract: Certain features relate to optimizing the processing of downlink data in a telecommunications system by capturing a downlink data stream and transferring the downlink data to a memory device in parallel. A processing device can capture a first set of downlink data blocks from a base station and store the first set of downlink data blocks to a memory device. Once a sufficient number of downlink data blocks are written to the memory device, the first set of data blocks can be transferred to a digital signal processor. A second set of data blocks can be captured substantially simultaneous to the first set of data blocks being transferred to the digital signal processor. In additional aspects, the second set of data blocks can be processed by the digital signal processor substantially simultaneous to additional data blocks being captured and stored in the memory device.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 23, 2019
    Assignee: CommScope Technologies LLC
    Inventors: Zhen Guo, Zhao Li, Roger Doles, Jr.
  • Patent number: 10352998
    Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 16, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Stephen Bowling, Igor Wojewoda, Dereck Fernandes, Manivannan Balu, Yong Yuenyongsgool, Timothy Phoenix, Steve Bradley
  • Patent number: 10356762
    Abstract: A method for multiple point communications includes configuring a set of first communications system resources to form a plurality of first communications system resource groups, each first communications system resource group including a plurality of channels, and configuring a set of second communications system resources for each one of the plurality of first communications system resource groups, the set of second communications system resources used to convey a feedback transmission. The method also includes signaling information about the plurality of first communications system resource groups to a first user equipment, and signaling information about the sets of second communications system resources associated with the plurality of first communications system resource groups to the first user equipment.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 16, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Bingyu Qu, Weimin Xiao, Jialing Liu
  • Patent number: 10346175
    Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Patent number: 10346328
    Abstract: An interrupt mechanism is disclosed. In one embodiment an integrated circuit (IC) is coupled to a number of peripheral devices, via a bus, and includes an interface controller. The interface controller includes a bus engine circuit coupled to receive data from the various ones of the peripheral devices, wherein the data may include various requests. The bus engine circuit also includes decoding circuitry configured to decode the data to determine the nature of the requests. Responsive to determining that interrupt information is stored in one or more of the requests, the interrupt information may be written to one of a number of interrupt registers. An interrupt controller may read the interrupt registers to determine the presence of interrupts, and thus initiate the process to see that they are serviced.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 9, 2019
    Assignee: Apple Inc.
    Inventors: James D. Ramsay, Inder Sodhi
  • Patent number: 10331881
    Abstract: Techniques are described herein for loading a user-mode component of a security agent based on an asynchronous procedure call (APC) built by a kernel-mode component of the security agent. The APC is executed while a process loads, causing the process to load the user-mode component. The user-mode component then identifies slack space of the process, stores instructions in the slack space, and hooks function(s) of the process, including modifying instruction(s) of the function(s) to call the instructions stored in the slack space. When those modified instruction(s) call the stored instructions, the stored instructions invoke the user-mode component, which receives data from the hooked function(s). Also, the security agent may bypass a control-flow protection mechanism of the operating system by setting a pointer of the control-flow protection mechanism to point to an alternate verification function.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 25, 2019
    Assignee: CrowdStrike, Inc.
    Inventors: Ion-Alexandru Ionescu, Loren C. Robinson
  • Patent number: 10331589
    Abstract: Methods, systems, and computer program products for using a stored interrupt location to provide fast interrupt register access in hypervisors are presented. A computer-implemented method may include maintaining an area of memory in a hypervisor to track a location of an interrupt vector corresponding to an asserted interrupt in a virtual machine, storing the location of the interrupt vector in the area of memory when responding to the asserted interrupt, and examining the area of memory to determine when an interrupt is present in the virtual machine.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 25, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Ronen Hod
  • Patent number: 10318454
    Abstract: Disclosed are an interrupt processing method and an interrupt controller. Before a CPU writes interrupt processing completion identification information of a current interrupt into an interrupt controller, interrupt source clear information of the interrupt is stored into the interrupt controller; and then when the interrupt controller receives a request, sent by the CPU, for writing the interrupt processing completion identification information, an interrupt source of the interrupt is directly cleared according to the interrupt source clear information stored in the interrupt controller, the CPU does not need to firstly access an interrupt clear register of a corresponding peripheral through a plurality of bus converter bridges to acquire information needed for clearing the interrupt source and then perform clearance.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: June 11, 2019
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventor: Zhiguo Xu
  • Patent number: 10318174
    Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-San Kim, Kyung Ho Kim, Seokhwan Kim, Seunguk Shin, Jihyun Lim