Interrupt Processing Patents (Class 710/260)
  • Patent number: 10366018
    Abstract: In a control apparatus which uses a CPU which does not have hardware for memory protection, a function is realized to detect unauthorized writing from a non-safety-related unit program in units of bits, for a safety-related unit data area of a RAM, a safety-related unit register area of an external integrated circuit, and a built-in peripheral I/O register of the CPU. A memory access monitoring unit requests an interrupt process upon detection of a write access of the safety-related unit program permitted to access a safety-related unit region. The interrupt process realizes a function to detect write access from a non-safety-related unit program area by using a program counter of a write access origin retracted to a stack area to judge whether the write access origin is a safety-related unit program or the non-safety-related unit program area, and judge, in units of bits, whether or not there is a change to a safety-related unit region.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: July 30, 2019
    Assignee: OKUMA CORPORATION
    Inventor: Yoshimasa Egi
  • Patent number: 10362568
    Abstract: Certain features relate to optimizing the processing of downlink data in a telecommunications system by capturing a downlink data stream and transferring the downlink data to a memory device in parallel. A processing device can capture a first set of downlink data blocks from a base station and store the first set of downlink data blocks to a memory device. Once a sufficient number of downlink data blocks are written to the memory device, the first set of data blocks can be transferred to a digital signal processor. A second set of data blocks can be captured substantially simultaneous to the first set of data blocks being transferred to the digital signal processor. In additional aspects, the second set of data blocks can be processed by the digital signal processor substantially simultaneous to additional data blocks being captured and stored in the memory device.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 23, 2019
    Assignee: CommScope Technologies LLC
    Inventors: Zhen Guo, Zhao Li, Roger Doles, Jr.
  • Patent number: 10352998
    Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 16, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Stephen Bowling, Igor Wojewoda, Dereck Fernandes, Manivannan Balu, Yong Yuenyongsgool, Timothy Phoenix, Steve Bradley
  • Patent number: 10356762
    Abstract: A method for multiple point communications includes configuring a set of first communications system resources to form a plurality of first communications system resource groups, each first communications system resource group including a plurality of channels, and configuring a set of second communications system resources for each one of the plurality of first communications system resource groups, the set of second communications system resources used to convey a feedback transmission. The method also includes signaling information about the plurality of first communications system resource groups to a first user equipment, and signaling information about the sets of second communications system resources associated with the plurality of first communications system resource groups to the first user equipment.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: July 16, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Bingyu Qu, Weimin Xiao, Jialing Liu
  • Patent number: 10346175
    Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Ben-Zion Friedman
  • Patent number: 10346328
    Abstract: An interrupt mechanism is disclosed. In one embodiment an integrated circuit (IC) is coupled to a number of peripheral devices, via a bus, and includes an interface controller. The interface controller includes a bus engine circuit coupled to receive data from the various ones of the peripheral devices, wherein the data may include various requests. The bus engine circuit also includes decoding circuitry configured to decode the data to determine the nature of the requests. Responsive to determining that interrupt information is stored in one or more of the requests, the interrupt information may be written to one of a number of interrupt registers. An interrupt controller may read the interrupt registers to determine the presence of interrupts, and thus initiate the process to see that they are serviced.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 9, 2019
    Assignee: Apple Inc.
    Inventors: James D. Ramsay, Inder Sodhi
  • Patent number: 10331881
    Abstract: Techniques are described herein for loading a user-mode component of a security agent based on an asynchronous procedure call (APC) built by a kernel-mode component of the security agent. The APC is executed while a process loads, causing the process to load the user-mode component. The user-mode component then identifies slack space of the process, stores instructions in the slack space, and hooks function(s) of the process, including modifying instruction(s) of the function(s) to call the instructions stored in the slack space. When those modified instruction(s) call the stored instructions, the stored instructions invoke the user-mode component, which receives data from the hooked function(s). Also, the security agent may bypass a control-flow protection mechanism of the operating system by setting a pointer of the control-flow protection mechanism to point to an alternate verification function.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 25, 2019
    Assignee: CrowdStrike, Inc.
    Inventors: Ion-Alexandru Ionescu, Loren C. Robinson
  • Patent number: 10331589
    Abstract: Methods, systems, and computer program products for using a stored interrupt location to provide fast interrupt register access in hypervisors are presented. A computer-implemented method may include maintaining an area of memory in a hypervisor to track a location of an interrupt vector corresponding to an asserted interrupt in a virtual machine, storing the location of the interrupt vector in the area of memory when responding to the asserted interrupt, and examining the area of memory to determine when an interrupt is present in the virtual machine.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 25, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Ronen Hod
  • Patent number: 10318454
    Abstract: Disclosed are an interrupt processing method and an interrupt controller. Before a CPU writes interrupt processing completion identification information of a current interrupt into an interrupt controller, interrupt source clear information of the interrupt is stored into the interrupt controller; and then when the interrupt controller receives a request, sent by the CPU, for writing the interrupt processing completion identification information, an interrupt source of the interrupt is directly cleared according to the interrupt source clear information stored in the interrupt controller, the CPU does not need to firstly access an interrupt clear register of a corresponding peripheral through a plurality of bus converter bridges to acquire information needed for clearing the interrupt source and then perform clearance.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: June 11, 2019
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventor: Zhiguo Xu
  • Patent number: 10318174
    Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-San Kim, Kyung Ho Kim, Seokhwan Kim, Seunguk Shin, Jihyun Lim
  • Patent number: 10318452
    Abstract: A processor and a control method thereof are processed. The processor includes an instruction fetch module configured to receive a first instruction of an interrupt service routine without backup of data stored in a register in response to processing of the interrupt service routine being requested, a detecting module configured to analyze the received first instruction to determine whether the data stored in the register needs to be changed, an instruction generating module configured to generate a second instruction for storing data in a temporary memory when the stored data is initially changed, an instruction selecting module configured to sequentially select the generated second instruction and first instruction; and a control module configured to perform the second instruction and the first instruction.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae-seok Im, Dong-kwan Suh, Suk-jin Kim, Seung-won Lee
  • Patent number: 10311233
    Abstract: By hooking application programming interfaces in an execution environment, the return address for hooked application programming interface calls can be logged and used to determine when a packed binary has been unpacked. In one approach, memory allocations are detected and the return address is checked against the memory regions allocated. In another approach, the contents of memory at the return address in a pre-execution copy of the executable binary is compared with the contents of memory at the return address in the executing copy of the binary. This allows efficient detection of the completion of unpacking without knowledge of the unpacking technique. The unpacked binary may then be analyzed for possible malware.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 4, 2019
    Assignee: McAfee, LLC
    Inventors: Amit Malik, Vikas Taneja, Benjamin Cruz
  • Patent number: 10310584
    Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and/or the determined access to the second device.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 4, 2019
    Assignee: Infineon Technologies AG
    Inventor: Prakash Kalanjeri Balasubramanian
  • Patent number: 10313432
    Abstract: A multi-microcontroller system, comprising a master microcontroller and a plurality of slave microcontrollers; wherein the master microcontroller is connected with the slave microcontrollers respectively via a network bridge; the network bridge forms a first communication part with a first memory interface and a first SPI interface, the plurality of first communication parts are connected with the master microcontroller and the slave microcontrollers, respectively; the network bridge is primarily responsible for processing transmission of control signals and data between the master microcontroller and the slave microcontrollers, and serves as a temporary storage area for common memory such that the states of the slave microcontrollers are put under automated management, the addresses of the slave microcontrollers are designated, and memory blocks are allocated.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 4, 2019
    Assignee: National Central University
    Inventors: Ching-Han Chen, Jhong-Ci Liou
  • Patent number: 10306099
    Abstract: In a system constructed by a plurality of integrated circuits, interrupt control can be performed in the case where an interrupt has occurred in an integrated circuit in which the function of a CPU is suspended. An interrupt unit of a second integrated circuit outputs an interrupt to at least one of the plurality of image processing units of the second integrated circuit, an image processing unit of the second integrated circuit, to which the interrupt is input, outputs an interrupt to a first integrated circuit, an image processing unit of the first integrated circuit, to which an interrupt from the second integrated circuit is input, outputs an interrupt to an interrupt unit of the first integrated circuit, and the interrupt unit of the first integrated circuit outputs an interrupt to an control unit of the first integrated circuit in accordance with the interrupt being input.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 28, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshihisa Nomura
  • Patent number: 10296606
    Abstract: At a client-side component of a storage group, a read descriptor generated in response to a read request directed to a first data store is received. The read descriptor includes a state transition indicator corresponding to a write that has been applied at the first data store. A write descriptor indicative of a write that depends on a result of the read request is generated at the client-side component. The read descriptor and the write descriptor are included in a commit request for a candidate transaction at the client-side component, and transmitted to a transaction manager.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Allan Henry Vermeulen, Timothy Andrew Rath, Timothy Daniel Cole, Kiran-Kumar Muniswamy-Reddy
  • Patent number: 10289415
    Abstract: Method and system for restoring results to a register file of a processing unit is provided. An instruction is dispatched in a processing slice of the processing unit, targeting a register file, wherein the processing unit includes two or more processing slices, each processing slice including a corresponding history buffer and at least a portion of a register file. The processing unit evicts previous result data from the register file entry to a history buffer corresponding to the processing slice, by writing new result data into the register file entry, in response to the instruction. The processing unit detects a trigger condition relating to a rollback of the processing unit to a previous state, and restores the previous result data from the history buffer to the register file entry, in response to the trigger.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10289332
    Abstract: An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 14, 2019
    Assignee: ARM Limited
    Inventors: Xabier Iturbe, Emre Özer, Balaji Venu, Antony John Penton
  • Patent number: 10275348
    Abstract: In an example, an apparatus includes a memory controller. The memory controller may be configured to communicate a request to a computer program for a resource, to initialize a memory, and to perform operations on the memory as instructed. The computer program may be configured to make resources available in response to requests for the resources. The memory controller may be further configured to use the resource in response to an indication from the computer program that the resource is available.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Varkey K. Varghese, Diyanesh B. Vidyapoornachary
  • Patent number: 10275299
    Abstract: A mechanism is provided in a data processing system for transferring failure data from a processing unit to a management device. In response to detecting a failure of the processing unit, a computing device within the data processing system gathers failure information from machine check registers of the processing unit. The computing device generates a time stamp command communicating a time and date of the failure information and sends the time stamp command to the management device. The computing device generates at least one error data command communicating error data derived from the failure information and sends the at least one error data command to the management device.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Haseeb A. Bhutta, Brent W. Yardley
  • Patent number: 10268576
    Abstract: An object of the present invention is to provide a semiconductor device and a control method thereof that can suppress a circuit scale from being increased while maintaining a high interruption response performance.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueki, Eiji Koeta
  • Patent number: 10261925
    Abstract: Enhanced techniques for detecting programming errors in device drivers are provided. The techniques disclosed herein enable a system to measure a number of aspects of IRPs including, but not limited to, data identifying processed IRPs, data indicating concurrent IRPs, data identifying a stack location associated with a status of an IRP, and individual status values, which may indicate whether IRPs have failed, succeeded or pended. The disclosed techniques enable a system to determine when and where IRPs were sent or not sent to a stack of device objects and/or to individual device objects. The disclosed techniques enable the system to measure the processing of concurrent IRPs. By the use of filters that are positioned in predetermined locations within a stack, disclosed techniques can test and monitor drivers without imposing unduly burdensome loads on the system.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Conal McGarvey, Andrew D. Mikesell
  • Patent number: 10223110
    Abstract: There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group. A control unit allows the arithmetic unit to perform arithmetic processing corresponding to an incorporated instruction. At this time, the control unit allows the arithmetic unit to perform arithmetic processing using the irrelevant data during a first one-clock cycle.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Minoru Saeki
  • Patent number: 10223269
    Abstract: A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Sub Kim, Tai-song Jin, Do-hyung Kim, Seung-won Lee
  • Patent number: 10216663
    Abstract: A processing system includes a general purpose instruction based data processor, an input configured to receive a command written by the data processor, a timer manager controller configured to receive the command and to execute the command, and a debug interrupt timer controller (DITC) configured to determine that the command is directed to the DITC and to store configuration information that associates the command with an element of the processing system that is a source of the command, where the configuration information is included in the command.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 26, 2019
    Assignee: NXP USA, INC.
    Inventors: Amir D. Modan, Ron Michael Bar, Thomas Riesenberg
  • Patent number: 10210069
    Abstract: Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 19, 2019
    Assignee: Total Phase, Inc.
    Inventors: Kumaran Santhanam, Leonid Vaynberg
  • Patent number: 10185569
    Abstract: Interrupt handling on a multiprocessor computer executing multiple computational operations in parallel is provided by establishing a total ordering of the multiple computational operations and defining an architectural state at the time of the interrupt as if the computational operations executed in the total ordering.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 22, 2019
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Gagan Gupta, Gurindar S. Sohi
  • Patent number: 10180908
    Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: January 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yanru Li, Subbarao Palacharla, Moinul Khan, Alain Artieri, Azzedine Touzni
  • Patent number: 10175985
    Abstract: A processor core includes an instruction-sequencing unit (ISU). The ISU includes a general register file (GRF) composed of multiple hardware general purpose registers (GPRs), an exception register (XER), and a reservation station (RS). The execution unit(s) load an address of data in a data GPR, and load a first portion of the data in a first data GPR and a second portion of the data in a second data GPR in the GRF, where loading the portions of the data generate intermediate data condition codes that are loaded in the XER. The execution unit(s) generate a cumulative data condition code, which is loaded into a history buffer within the ISU. The intermediate data condition codes are loaded into a reservation station (RS) within the ISU. Upon flushing the GRF and the XER, the ISU repopulates the GRF from a history buffer and the XER from the RS.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen
  • Patent number: 10169106
    Abstract: According to one or more embodiments, a system and computer implemented method for managing critical section processing are provided. The method includes generating, using a processor, a transaction scope for a process in response to processing in a critical section, collecting data related to the process, generating, using the processor, a request using the collected data, storing the request and data as a pending item in a private storage during critical section processing, and processing, using the processor, the request based on the transaction scope.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong L. Dos Reis, Christopher D. Filachek, Mei Hui Wang
  • Patent number: 10169567
    Abstract: Systems and methods for performing behavioral authentication of Universal Serial Bus (USB) devices are described. These methods may capture one or more behavioral characteristics of a specific USB device and may generate a device fingerprint based on the captured characteristics. When the USB device is plugged in again in the host device, the behavioral characteristics of the USB device may be re-captured and may be compared to those of the device fingerprint. If it is determined that such behavioral characteristics substantially match, authorization may be granted. In one example, timing characteristics may be used as behavioral characteristics, in which the timing of a series of transactions is sensed by the host device. A timing characteristic may include, for example, the time it takes the USB device to complete a transaction. The transactions are part of an enumeration process in some embodiments.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: January 1, 2019
    Assignee: Lockheed Martin Corporation
    Inventors: Andrew L. Pentz, Chris K. Cockrum, William W. Moldenhauer, Robert Willson, John W. Hebeler
  • Patent number: 10169270
    Abstract: A technique for handling queued interrupts includes determining, by an interrupt presentation controller (IPC), whether a received memory mapped input/output (MMIO) store is associated with preempting a virtual processor (VP) thread. In response to determining the MIMO store is associated with preempting the VP thread, the IPC writes interrupt context information of the VP thread to a specified location in memory.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10165026
    Abstract: There is provided a method and system for generating and distributing an encoded content transport stream. The method comprises obtaining metadata and at least one unique identifier that identifies content elements, generating a recipient specific list using the metadata and at least one of the unique identifiers, creating a content transport stream using the recipient specific list including the metadata and the identified content elements, encoding the content transport stream to generate the encoded content transport stream, and distributing the encoded content transport stream through at least one network path. The metadata may include destination points and priority information of the encoded content transport stream, which may take the form of sections of television programming or block of commercial advertisements.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 25, 2018
    Assignee: Disney Enterprises, Inc.
    Inventors: Michael V. Chiarulli, Todd Christiansen, David A. Dreispan, Joseph P. Kenny, Jerry A. Rapella
  • Patent number: 10152480
    Abstract: Raw data in distributed servers is divided into groups of data called buckets containing raw data that have timestamps that fall within a specific time range. When a bucket becomes inactive a server can archive the bucket to an external storage system. The external storage system containing archived data may be specified in a search query. Archived data from the external storage system is obtained, processed, and a search performed on the processed archived data using the search query.
    Type: Grant
    Filed: January 31, 2015
    Date of Patent: December 11, 2018
    Assignee: SPLUNK INC.
    Inventors: Clint Sharp, Petter Eriksson, Ledion Bitincka, Jason Szeto, Elizabeth Lin, Nima Haddadkaveh
  • Patent number: 10140204
    Abstract: Embodiments of the present invention provide systems and methods for generating a set of test cases using a base test program. The base test program may be used as both a functional drive and as a performance measuring test case. From the base test program, additional key and value pairs may be added to the base test program to force specific test scenarios.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Deborah A. Furman, Anthony T. Sofia
  • Patent number: 10127137
    Abstract: Embodiments herein disclose a debugging framework that employs a mode in the processor (for example, a processor using x86 architecture), to transparently study armored malware. Embodiments herein perform stealthy debugging by leveraging System Management Mode (SMM) to transparently debug software on bare-metal.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 13, 2018
    Inventors: Fengwei Zhang, Kevin Leach, Angelos Stavrou, Haining Wang
  • Patent number: 10110489
    Abstract: The apparatus (SW) has a plurality of input/output ports (P1, P2, P3, P4, P5) for receiving and transmitting data packets, and comprises a data packets handling circuitry (DPL) arranged to forward data packets between the input/output ports (P1, P2, P3, P4, P5) and an internal apparatus controller (CPL) arranged to control the data packet handling circuitry (DPL); the apparatus (SW) has a control port (PC) for communication between the internal apparatus controller (CPL) and an external network controller (NWC); the apparatus controller (CPL) is arranged to store (MEM) at least one state transition table (TT) to be used for controlling the forwarding of data packets by the data packets handling circuitry (DPL); the apparatus controller (DPL) is arranged to use said at least one state transition table (TT) for implementing at least one finite state machine (FSM); the apparatus controller (DPL) is arranged to use said at least one state transition table (TT) for handling separately distinct incoming data packet
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 23, 2018
    Inventors: Giuseppe Bianchi, Antonio Capone, Marco Bonola, Carmelo Cascone
  • Patent number: 10101996
    Abstract: An arithmetic processing apparatus includes multiple selection circuits that are connected in series, wherein at least one selection circuit, the at least one selection circuit being served as a first selection circuit, includes a selection unit that selects a first input unit from two or more input units each receiving, from a source or a selection circuit in a previous stage, data and an identifier of a sender of the data; based on the two or more identifiers, and priority information indicating respective priorities for multiple sources connected to: a selection circuit upstream to the first selection circuit; and the first selection circuit; an update unit that updates, in the priority information, a priority for a first source indicated by a first identifier being received by the first input unit; and a transfer unit that transfers data and the first identifier passed through the first input unit, to a destination.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 16, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yasuhiro Kitamura
  • Patent number: 10099705
    Abstract: An autonomous-capable vehicle which can be operated in a transitional state from manual vehicle operation to autonomous vehicle operation. In the transitional state, the vehicle operates autonomously and overrides manual interaction of the user. To maintain the transitional state, the driver performs a continuous action, such as providing a continuous interaction with a switching mechanism.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 16, 2018
    Assignee: Uber Technologies, Inc.
    Inventors: Nicholas Letwin, Morgan Jones, Michael Sergi-Curfman
  • Patent number: 10102380
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Francis X. McKeen, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Patent number: 10102007
    Abstract: Status indicators are provided. An operation is performed in a current operating mode of the processor, in which the current operating mode is dynamically selectable from a plurality of supported operating modes. A first set of status indicators is set, based on performing the operation in the current operating mode. A second set of status indicators is set, based on performing the operation in the current operating mode, but the setting is to reflect at least one status condition for another operating mode supported by the processor. At least one of the first set of status indicators or the second set of status indicators is used in further processing.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 10089339
    Abstract: Apparatus and a corresponding method for processing received datagram fragments are provided. Fragments are considered in fragments lists, which comprise a linked list of fragments. The fragments lists are referenced by corresponding entries stored in fragment list storage, where all received fragments from a given datagram will form part of the same fragment list, but a given fragment list can comprise fragments from multiple datagrams. An accumulated size of the payloads for a linked list of fragments is maintained and allows a determination to be made of whether it appears that sufficient fragments have been received that reassembly of a datagram may be possible. Access to a selected fragment list entry is made atomically, wherein the existing entry is first read and then if a datagram reassembly is to be attempted a write access sets the selected fragment list entry to a null entry before that datagram reassembly is attempted.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 2, 2018
    Assignee: ARM Limited
    Inventors: Eric Ola Harald Liljedahl, Mario Torrecillas Rodriguez
  • Patent number: 10089265
    Abstract: Systems, methods, and computer readable medium are provided that improve the management of interrupt requests in multiple processor computer systems. Interrupt requests can be classified into three categories and the structure of the categories provide for specifying a list that needs to be migrated. The list can contain only those interrupt requests that can be handled by some of the processors that will never unplug or based on affinity. When a processor is about to unplug, the computer system can migrate that list. The system can also manage the other interrupt requests.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: October 2, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Hsu, Shun-Chih Yu, Sen-Yu Cheng
  • Patent number: 10089264
    Abstract: A mechanism is described for facilitating callback interrupt handling for multi-threaded applications in computing environments. A method of embodiments, as described herein, includes detecting a task issued by a thread associated with an application processor, where the task is to be processed by a graphics processor at the apparatus. The method may further include scheduling the task at the graphics processor, and emulating an interrupt to the application processor, where the emulated interrupt disables one or more graphics interrupts while the task is being processed by the graphics processor. The method may further include facilitating an interrupt handler to communicate a signal to the application processor to wake up the thread, where the thread is facilitated to perform one or more tasks independent of the task being processed by the graphics processor.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: October 2, 2018
    Assignee: INTEL CORPORATION
    Inventor: Yen Hsiang Chew
  • Patent number: 10073699
    Abstract: Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: September 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10042798
    Abstract: A system is described that comprises: a master device and a slave device. The slave device comprises: a first die comprising an interface comprising a decoder configured to support a MIPI™ RFFE slave protocol; at least one second die comprising a simplified address decoder, operably coupled to the first die; and a shared control bus that is configured to support at least a clock signal and a data signal shared between the master device and the at least one second die on the slave device. The interface of the first die is configured to generate at least one circuit enable signal, routed to the at least one second die. The simplified address decoder is configured to process the clock signal and the data signal in response to the at least one circuit enable signal.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 7, 2018
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Bernard Mark Tenbroek, David Stephen Ivory
  • Patent number: 10042794
    Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 7, 2018
    Assignee: APPLE INC.
    Inventors: Karan Sanghi, Vladislav Petkov, Radha Kumar Pulyala, Saurabh Garg, Haining Zhang
  • Patent number: 10037226
    Abstract: An electronic device includes a plurality of processes, an interrupt waiting unit for each of the processes, and an interrupt handler. The interrupt handler processes the interrupt. The interrupt waiting unit sets an interrupt waiting flag to wait for an occurrence of the interrupt. The interrupt handler, when the interrupt occurred, sets an interrupt style of the occurred interrupt and releases the interrupt waiting flag from the set state. The interrupt waiting unit, when the interrupt waiting flag was released from the set state, sets the interrupt waiting flag if the interrupt style set by the interrupt handler is not an interrupt style matched with the process, and operates the process if the interrupt style set by the interrupt hander is the interrupt style matched with the one of the processes. The interrupt waiting flag is located to each of the processes.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 31, 2018
    Assignee: KYOCERA Document Solutions, Inc.
    Inventor: Shuntaro Tsuji
  • Patent number: 10037292
    Abstract: Systems and methods for sharing message-signaled interrupt vectors in multi-processor computer systems. An example method may comprise: associating an interrupt vector with a first device component; associating the interrupt vector with the second device component; creating, in a first interrupt descriptor table (IDT) associated with a first processor, a first interrupt descriptor to reference a first interrupt service routine to process a first interrupt triggered by the first device component; and creating, in a second IDT associated with a second processor, a second interrupt descriptor to reference a second interrupt service routine to process a second interrupt triggered by the second device component, wherein the first interrupt descriptor and the second interrupt descriptor reference the interrupt vector.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 31, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Paolo Bonzini, Michael Tsirkin
  • Patent number: 10031697
    Abstract: Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Tushar Kumar, Aravind Natarajan, Dario Suarez Gracia