Interrupt Processing Patents (Class 710/260)
  • Patent number: 11900127
    Abstract: Cryptographically-secured deferral tickets provided by a minting process that runs in a secure enclave on a computing device reset an authenticated watchdog timer that reboots the device from a hardware-protected recovery operating system to re-image the device into a known good state if the timer expires. The deferral tickets are written to a secure channel using a symmetric key that is provisioned by repurposing an existing Intel SGX (Software Guard Extension) Versioning Support protocol that enables migration of secrets between enclaves that have the same author. In an illustrative embodiment, the deferral ticket minting process and authenticated watchdog timer execute locally to enable automated recovery of the computing device when utilized in far edge infrastructure of a fifth generation (5G) network such as a distributed unit (DU) of a radio access network (RAN).
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 13, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Stefan Saroiu, Varun Gandhi, Alastair Wolman, Landon Prentice Cox
  • Patent number: 11870673
    Abstract: Various methods and systems for facilitating network traffic monitoring in association with an application running on a client device are provided. In this regard, aspects of the invention facilitate monitoring network traffic being transmitted to and/or from a client device, such as a mobile device, so that network performance can be analyzed. In various implementations, one or more default classes associated with an application on a device are replaced with one or more custom monitoring classes designed to facilitate monitoring data packets being communicated to or from the application. The custom monitoring classes can then be utilized to facilitate monitoring a plurality of data packets communicated to or from the application.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: January 9, 2024
    Assignee: Splunk Inc.
    Inventor: Konstantinos Polychronis
  • Patent number: 11868175
    Abstract: Systems and methods for clock synchronization in accordance with embodiments of the invention are illustrated. One embodiment includes a clock synchronization system includes a reference device including a clock circuitry, and a transmitter configured to transmit a synchronization signal based on a clock signal using the clock circuitry, and a receiving device including a processor configured to operate by a general-purpose operating system (GPOS), a coprocessor configured to operate by a real-time operating system (RTOS), a memory utilized by the processor, where the coprocessor has direct memory access to the memory, and a receiver configured to receive the signal, where the RTOS directs the coprocessor to trigger an interrupt upon reception of the signal, sample a GPOS clock time stored in the memory in response to the interrupt, generate a clock time based on the signal and the sampled GPOS clock time, and provide the GPOS with the clock time.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: January 9, 2024
    Assignee: SYNG, Inc.
    Inventors: Jay Sterling Coggin, Marc Carino, Fabian Renn-Giles, Mark Rakes, Afrooz Family
  • Patent number: 11847366
    Abstract: The disclosure discloses methods and systems for reserving a tray for a user for special media printing. The method includes receiving one or more special media sheets as loaded by the user in the tray. Based on the loaded special media sheets, a tray ID of the tray is automatically identified. A user interface is provided to the user to input loaded media details such as media size, type, and color. Then, it is checked with the user whether to reserve the identified tray for the user for special media printing. Based on the check, a user interface is further provided to the user to input a user ID. Finally, the identified tray is automatically reserved for the user using the user ID and the tray ID, for printing a document later received from the user on the one or more special media sheets as loaded in the identified/reserved tray.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: December 19, 2023
    Assignee: XEROX CORPORATION
    Inventors: Purushothaman Jayakumar, Ponnovian Parthasarathy, Duraimurugan Krishnasamy, Nisha Mohan
  • Patent number: 11831492
    Abstract: Example methods are provided for network management entity to perform group-based network event notification in a network environment that includes the network management entity and a notification consumer. The method may comprise: in response to detection of a first network event associated with a group, withholding notification of the first network event to the notification consumer; and in response to detection of a second network event associated with the group, withholding notification of the second network event to the notification consumer. The method may further comprise generating a group notification associated with the group, wherein the group notification is an aggregate notification to report the detection of at least the first network event and second network event; and sending the group notification to the notification consumer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 28, 2023
    Assignee: NICIRA, INC.
    Inventors: Vaibhav Bhandari, Naveen Ramaswamy
  • Patent number: 11792264
    Abstract: The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 17, 2023
    Assignee: Camgian Microsystems Corp.
    Inventors: Gary Butler, Derrick J. Savage, David Lindley, Muthukumar Nagarajan, Jeffery Hunt
  • Patent number: 11778112
    Abstract: The disclosure discloses methods and systems for allowing a user to reserve a tray for special media printing while submitting a document for printing, the method is implemented at a print driver application running on a computing device. The method includes receiving a print request for the document through the print driver application. A user interface is provided to the user including one or more print attributes, wherein at least one print attribute includes special media option. Upon selection of the special media option, a list of one or more trays available at at least one multi-function device for special media printing is displayed. Thereafter, the user is allowed to select a tray from the displayed tray list for reservation for special media printing at the at least one multi-function device.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: October 3, 2023
    Assignee: Xerox Corporation
    Inventors: Nisha Mohan, Ponnovian Parthasarathy, Purushothaman Jayakumar, Duraimurugan Krishnasamy, Narayan Kesavan
  • Patent number: 11755512
    Abstract: An example method may include allocating, on a host computer system, a memory page in a memory of an input/output (I/O) device, mapping the memory page into a memory space of a virtual machine associated with a first virtual processor, creating a first entry in an interrupt mapping table in the memory of the I/O device, where the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and creating a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, where the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: September 12, 2023
    Assignee: Red Hat, Inc.
    Inventors: Amnon Ilan, Michael Tsirkin
  • Patent number: 11740902
    Abstract: An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Yogesh Deshpande, Pandurang V. Deshpande
  • Patent number: 11698672
    Abstract: A hardware architecture for an artificial neural network ANN. The ANN includes a consecutive series made up of an input layer, multiple processing layers, and an output layer. Each layer maps a set of input variables onto a set of output variables, and output variables of the input layer and of each processing layer are input variables of the particular layer that follows in the series. The hardware architecture includes a plurality of processing units. The implementation of each layer is split among at least two of the processing units, and at least one resettable switch-off device is provided via which at least one processing unit is selectively deactivatable, independently of the input variables supplied to it, in such a way that at least one further processing unit remains activated in all layers whose implementation is contributed to by this processing unit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 11, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Juergen Schirmer, Andre Guntoro, Armin Runge, Christoph Schorn, Jaroslaw Topp, Sebastian Vogel
  • Patent number: 11698806
    Abstract: Systems and methods for accelerating hypercalls for nested virtual machines. An example method may comprise executing, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine (VM). The Level 0 hypervisor receives a first function component from a Level 2 hypervisor managing a Level 3 VM, where the first function component performs a first functionality associated with a hypercall issued by the Level 3 VM; stores the first function component in a memory space associated with the Level 0 hypervisor; detects the hypercall issued by the Level 3 VM; and responsive to detecting the hypercall, executes the first function component to modify a VM context for the Level 3 VM.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: July 11, 2023
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Karen Noel
  • Patent number: 11669339
    Abstract: The present invention provides a hardware setting device and hardware setting method thereof. The hardware setting device is configured to: boot an operating system; retrieve at least one hardware setting corresponding to a peripheral device from a pre-boot memory; and configure the peripheral device according to the at least one hardware setting.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: June 6, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun Hao Lin, Tsunghan Tsai, Zhen-Ting Huang
  • Patent number: 11663114
    Abstract: A method for facilitating automated testing of event-driven microservices is provided. The method includes receiving a scenario that includes a set of instructions to test a microservice; automatically generating, based on the scenario, a production event relating to an action to be performed and a consumption event relating to a record of the performed action; automatically generating a first test event using the production event; outputting the first test event to the microservice; automatically retrieving a first result relating to the execution of the first test event by the microservice by using the consumption event; and validating the first result based on the scenario. The method further includes displaying the first result and a notification on a graphical user interface based on an outcome of the validating.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: May 30, 2023
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: Amol R. Katdare, Michael Tinker
  • Patent number: 11650881
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: determining, by a host system, that a failure affects a storage capacity of a memory sub-system, wherein the memory sub-system comprises stored data of a storage structure; instructing, by the host system, the memory sub-system to operate at a reduced capacity and to retain the stored data of the storage structure; receiving, by the host system, a set of storage units of the memory sub-system that are affected by the failure; and recovering, by the host system, data that was in the set of storage units affected by the failure.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11630667
    Abstract: A processor includes a plurality of vector sub-processors (VSPs) and a plurality of memory banks dedicated to respective VSPs. A first memory bank corresponding to a first VSP includes a first plurality of high vector general purpose register (VGPR) banks and a first plurality of low VGPR banks corresponding to the first plurality of high VGPR banks. The first memory bank further includes a plurality of operand gathering components that store operands from respective high VGPR banks and low VGPR banks. The operand gathering components are assigned to individual threads while the threads are executed by the first VSP.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 18, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jiasheng Chen, Bin He, Jian Huang, Michael Mantor
  • Patent number: 11627468
    Abstract: During the boot process, a secure wireless display connect module of the BIOS can authenticate a wireless display and determine whether the wireless display can comply with the HDCP. When the secure wireless display connect module determines that the wireless display is HDCP compliant, the secure wireless display connect module can create an ACPI secure blob in which is stored a shared session key generated as part of determining that the wireless display is HDCP compliant. A video authentication session module of the BIOS can then retrieve this shared session key from the ACPI secure blob and use it to encrypt video frames that are to be sent to the wireless display. The video authentication session module may additionally embed a session ID and a timeout into each video frame which the wireless display can employ to detect when the video frame should no longer be displayed.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 11, 2023
    Assignee: Dell Products L.P.
    Inventors: Shekar Babu Suryanarayana, Sumanth Vidyadhara
  • Patent number: 11550619
    Abstract: According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 10, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Mikio Hashimoto, Masami Aizawa, Satoru Suzuki, Tsuneki Sasaki
  • Patent number: 11552892
    Abstract: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 10, 2023
    Assignee: ATI Technologies ULC
    Inventor: Alexander S. Duenas
  • Patent number: 11520679
    Abstract: An overall access rating for each user in a plurality of users for accessing a computing resource of a set of computing resources is generated. Reduced performance of the computing resource is identified. Access metrics associated with each user in the plurality of users who are accessing the computing resource during the reduced performance of the computing resource are determined. The generated overall access ratings based on the determined access metrics are modified. Access to the computing resource is granted based on a ranking of the modified overall access ratings.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: December 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Zachary A. Silverstein, Jacob Ryan Jepperson, Spencer Thomas Reynolds, Jeremy R. Fox
  • Patent number: 11513835
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 29, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Qing Liang, Jonathan S. Parry, Kulachet Tanpairoj, Stephen Hanna
  • Patent number: 11500633
    Abstract: An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Yogesh Deshpande, Pandurang V. Deshpande
  • Patent number: 11500809
    Abstract: A single-wire two-way communication circuit includes two chips and a data transmission line coupled between the two chips. Each chip includes a random access memory, a data control module, a data line control module, and a data line monitoring module. The random access memory stores data. The data control module obtains data of a first address from the random access memory and stores data of a second address received from the other chip into a second address of the random access memory. The data line control module sends the obtained data of the first address to the other chip through the data transmission line to perform a write operation. The data line monitoring module receives the data of the second address sent by the other chip through the data transmission line to perform a read operation.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 15, 2022
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Xiao-Long Zhou
  • Patent number: 11495121
    Abstract: Systems and methods that may be implemented to employ a programmable integrated circuit within a smart battery pack to detect and/or log occurrence of chassis intrusion and/or tampering events in a battery-powered information handling system within which the smart battery pack is installed. A battery management unit (BMU) or other programmable integrated circuit of the installed smart battery pack may be utilized to detect occurrence of a tampering and/or intrusion event into the chassis of the host information handling system based on a current state of a system present (Sys_Pres) signal at the battery pack that indicates temporary or permanent disconnection of system motherboard circuitry from the smart battery pack of the battery-powered information handling system. Such a detected occurrence of a tampering and/or intrusion event may be reported to a remote human user of remote system and/or to a local human user of the local system.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 8, 2022
    Assignee: Dell Products L.P.
    Inventors: Nicholas D. Grobelny, Geroncio O. Tan, Richard C. Thompson, Adolfo S. Montero
  • Patent number: 11487574
    Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how interrupts may be provided to targeted virtual processors, regardless of where the virtual processors are currently executing. That is, when an interrupt is received, the interrupt may be delivered to a specified virtual processor regardless of which logical processor is currently hosting the virtual processor.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: November 1, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aditya Bhandari, Bruce J. Sherwin, Jr., Xin David Zhang
  • Patent number: 11467892
    Abstract: A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 11, 2022
    Assignee: Nordic Semiconductor ASA
    Inventors: Anders Nore, Joar Rusten, Steffen Wiken
  • Patent number: 11461104
    Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 4, 2022
    Assignee: ARM LIMITED
    Inventors: Michael John Williams, Richard Roy Grisenthwaite, Simon John Craske
  • Patent number: 11449367
    Abstract: A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 20, 2022
    Assignee: International Business Machines Corporation
    Inventors: Matthias Klein, Simon Weishaupt, Anthony Thomas Sofia, Jonathan D. Bradbury, Mark S. Farrell, Mahmoud Amin, Timothy Slegel
  • Patent number: 11451432
    Abstract: Timer configurations for new radio (NR) unlicensed (NR-U) and NR shared spectrum (NR-SS) operations are disclosed. In NR-U and NR-SS operations, certain event timers may be interrupted by a user equipment (UE) when it detects that its serving base station has failed a listen before talk (LBT) procedure, thereby losing access to the shared communication spectrum. When the UE detects a subsequent successful LBT, it resumes the progression of the event timer. In NR-SS operations, the UE may also interrupt the applicable timers either in all slots dedicated to another operator or in all slots in which the serving base station does not have transmission access.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 20, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Srinivas Yerramalli, Xiaoxia Zhang
  • Patent number: 11436040
    Abstract: A new approach of systems and methods to support a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling is proposed. The hierarchical interrupt propagation scheme organizes a plurality of slave interrupt handlers associated functional blocks in a chip in a hierarchy. When an exception or error condition occurs in a functional block, a slave interrupt handler associated with the functional block creates an interrupt packet as an interrupt notification and utilizes pre-existing input and output interfaces that have already been utilized for accessing registers of the functional block to transmit the created interrupt packet to a central interrupt handler through the hierarchy without running dedicated interconnect wires out of the functional block.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 6, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Saurabh Shrivastava, Guy T. Hutchison
  • Patent number: 11429426
    Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 30, 2022
    Assignee: Arm Limited
    Inventors: Timothy Nicholas Hay, Martin Weidmann, Michael Alexander Kennedy, Andrew John Turner
  • Patent number: 11429550
    Abstract: An extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: August 30, 2022
    Assignee: Futurewei Technologies, Inc.
    Inventor: Wesley Shao
  • Patent number: 11397815
    Abstract: A method for secure data protection includes storing secured data, associated with a computer application, using a security co-processor. The secured data is associated with a platform state policy that indicates an expected platform state. The secured data is associated with a version counter policy that indicates an expected version counter. A platform state of a computing platform is stored in the security co-processor. A version counter of the platform state is stored in the security co-processor. A request for the secured data is received from the requester. The platform state is determined to be in a known good state based on the platform state policy, the version counter policy, the platform state, the expected platform state, the version counter, and the expected version counter. The secured data is provided for the requester based on the determination.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ludovic Emmanual Paul Noel Jacquin, Hamza Attak
  • Patent number: 11392516
    Abstract: A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after an operation indicated by the first type command has been completed by the memory circuits.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 19, 2022
    Assignee: Adesto Technologies Corporation
    Inventor: Paul Hill
  • Patent number: 11392406
    Abstract: Alternative reporting channels are implemented for interrupts to a microcontroller device. An access device for a microcontroller may support performing requests from a microcontroller to controlled devices via an interconnect. The access device may have a separate communication channel with at least one of the controlled devices to receive interrupts. When an interrupt is signaled, an indication of the interrupt may be stored at a storage device at the access device. The microcontroller may read from the storage device at the access device to obtain the indication of the interrupt.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: July 19, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A Volpe, Mark Banse
  • Patent number: 11385927
    Abstract: A method for handling an interrupt includes receiving, in hardware or in firmware, a request from a task executing in userspace, where the request is to assign a function in the task and state information for the task to an interrupt. The hardware or firmware records the state information for the task, and assigns defined state information for the function to an event caused by the interrupt. When the interrupt occurs, the interrupt is serviced by saving context including the state information for the task in the memory, loading the defined state information for the function into registers, running the function, and then returning to the task preempted by the interrupt.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 12, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Alexander Belits, Prasun Kapoor
  • Patent number: 11379024
    Abstract: As described herein, a method performed in response to a client device undergoing an at least partial warm reset or reboot may include receiving a firmware commit request from a client device. The method may also include writing, at a first time, a firmware image associated with the client device into execution memory of volatile memory. The method may also include writing, at a second time, the firmware image associated with the client device into a memory slot of non-volatile memory.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shalu Agrawal, Ashok Kumar Yadav, Shaileshkumar Vasu, Vismay Ajaykumar Desai
  • Patent number: 11340671
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 24, 2022
    Assignee: Google LLC
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Jaymin Patel
  • Patent number: 11321253
    Abstract: An interrupt rate limiter limits the rate of interrupt signals being transmitted from a first node to a second node of a computer system. In certain implementations, a first logic block compares an accumulator value to a threshold value to determine whether to (i) block an interrupt signal received from the first node from reaching the second node or (ii) allow the interrupt signal to reach the second node, an accumulator register stores the accumulator value, which is (i) increased whenever the first logic block allows an interrupt signal to reach the second node and (ii) otherwise periodically decreased, a summation node receives the accumulator value and one or more values that determine whether the accumulator value is to be increased or decreased, and a second logic block determines whether to increase or decrease the accumulator value based on whether an interrupt signal has been transmitted to the second processor.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 3, 2022
    Assignee: NXP B.V.
    Inventor: Martin Kessel
  • Patent number: 11318618
    Abstract: A robotic surgical system and method are disclosed for handling real-time and non-real-time traffic. In one embodiment, a surgical robotic system is provided comprising at least one robotic arm coupled to an operating table; and a control computer comprising a processor and a hardware interface, wherein the processor is configured to: receive a notification about real-time data from the operating table at the hardware interface; process the real-time data immediately upon receiving the notification; and poll the hardware interface for non-real time data from the operating table only when not processing the real-time data. Other embodiments are provided.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: May 3, 2022
    Assignee: Verb Surgical Inc.
    Inventor: Jignesh Desai
  • Patent number: 11314864
    Abstract: Techniques for monitoring based on a memory layout of an application are disclosed. A memory layout may be received, obtained, and/or generated from an application executing on a computer. Based on one or more attributes of a plurality of memory regions of the memory layout a memory layout fingerprint is generated. Additionally, memory region fingerprints are generated based on the one or more attributes for respective memory regions. The memory layout fingerprint and the memory region fingerprints are compared to respective previous memory layout fingerprints and the memory region fingerprints in order to determine whether malicious code and/or application drifting has occurred.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 26, 2022
    Assignee: PayPal, Inc.
    Inventor: Shlomi Boutnaru
  • Patent number: 11314538
    Abstract: An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christoph Raisch, Marco Kraemer, Bernd Nerz, Donald William Schmidt, Peter Dana Driever
  • Patent number: 11314484
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: April 26, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takeshi Aoki, Seiichi Yoneda, Yoshiyuki Kurokawa
  • Patent number: 11315626
    Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a sort operation in a memory. An example apparatus might include a a first group of memory cells coupled to a first sense line, a second group of memory cells coupled to a second sense line, and a controller configured to control sensing circuitry to sort a first element stored in the first group of memory cells and a second element stored in the second group of memory cells by performing an operation without transferring data via an input/output (I/O) line.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kyle B. Wheeler
  • Patent number: 11301132
    Abstract: One or more usage parameter values are received from a host system. The one or more parameter values correspond to one or more operations performed at the memory sub-system. Based on the one or more usage parameter values, a first expected time period is determined during which a first set of subsequent host data will be received from the host system and a second expected time period is determined during which a second set of subsequent host data will be received from the host system. A media management operation is scheduled to be performed between the first expected time period and the second expected time period.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 12, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Poorna Kale, Ashok Sahoo
  • Patent number: 11294695
    Abstract: A computer-implemented method for termination of programs associated with different addressing modes includes receiving a call to an external interface to execute a target callee program from a caller program executing in a primary runtime environment. The external interface allocates an interoperability term area (ITA) in a primary runtime environment. The ITA is accessible by the primary runtime environment and a secondary runtime environment. The external interface executes the target callee program in the secondary runtime environment. The target callee program sets a termination reason parameter in the ITA. In response to the target callee program setting the termination reason parameter, a termination action in the primary runtime environment is performed. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiao Yan Tang, Naijie Li, Jing Lu, Ming Ran Liu, Kershaw S. Mehta
  • Patent number: 11288095
    Abstract: A technique for synchronizing workgroups is provided. The techniques comprise detecting that one or more non-executing workgroups are ready to execute, placing the one or more non-executing workgroups into one or more ready queues based on the synchronization status of the one or more workgroups, detecting that computing resources are available for execution of one or more ready workgroups, and scheduling for execution one or more ready workgroups from the one or more ready queues in an order that is based on the relative priority of the ready queues.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexandru Dutu, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood
  • Patent number: 11281508
    Abstract: Systems and methods for low memory killer protection are disclosed. According to one embodiment, in an information processing apparatus comprising at least one computer processor and executing an operating system including a LMK subsystem, a method for providing low memory killer (LMK) protection may include: (1) a non-system application embedded with a SDK initiating a foreground service at the beginning of a use case session; (2) the non-system application causing the foreground service to create an ongoing notification with the operating system, wherein the ongoing notification causes the non-system application to have no lower than a perceptible LMK status during the use case session; (3) the non-system application completing the use case session; and (4) the non-system application causing the foreground service to remove the ongoing notification.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 22, 2022
    Assignee: VERIFONE, INC.
    Inventors: Joshua David Galicia, Nicholas James Versino, Christopher Scott Gremo, Robert Ferguson
  • Patent number: 11281607
    Abstract: According to one example, a method includes, with a hypervisor, advertising a paravirtualized cluster mode for a guest using a legacy Advanced Programmable Interrupt Controller (APIC), the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight. The method further includes, associating each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2N different values. The method further includes, with the hypervisor, in response to receiving an interrupt for the virtual machine, determining to which of the plurality of virtual cores the interrupt should be sent based on at least a subset of bits in a destination address of the interrupt.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 22, 2022
    Assignee: RED HAT, INC.
    Inventor: Bandan Das
  • Patent number: 11281490
    Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse Arroyo, Prathima Kommineni, Timothy M. Schimke, Shyama Venugopal
  • Patent number: RE49439
    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Surhud Khare, Dinesh Somasekhar, Shekhar Y. Borkar